AC converter - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 2, APRIL 2006

467

Control of the Single-Phase Three-Leg AC/AC Converter Cursino Brandão Jacobina, Senior Member, IEEE, Talvanes Meneses Oliveira, Member, IEEE, and Edison Roberto Cabral da Silva, Fellow, IEEE

Abstract—This paper investigates the control of a single-phase three-leg ac/ac reversible converter in which a leg is shared by both the grid and the load side. Pulsewidth-modulation (PWM) techniques based on scalar and vector approaches are developed, introducing the concept of local and general apportioning factor and, also, a complete equivalence between scalar and space vector PWM. A hysteresis current controller capable of taking into account the shared leg is developed and a zero current error linear controller is presented. Furthermore, a control strategy to obtain maximum utilization of the dc-bus voltage is proposed. In addition, several relevant characteristics of the converter are addressed, such as voltage rating, harmonic distortion, shared leg and capacitor currents, and power rating. The converter is compared to four-leg and two-leg converters. Experimental results are presented. Index Terms—AC/AC converter, converter control, reduced switch count.

I. I NTRODUCTION

I

T IS POSSIBLE to implement inverter and rectifier systems employing minimized component converters as proposed in the case of single-phase to three-phase ac/ac converters [1] and three-phase to three-phase ac/ac converters [2], [3]. An indirect single-phase ac/ac reversible converter can use single-phase four-leg (eight switches) converters (i.e., two full-bridge topologies) with a dc-bus capacitor link, as shown in Fig. 1(a). However, such a converter has a relatively large number of power devices. An alternative to this is a single-phase ac/ac converter system employing a two-leg (four switches) converter (i.e., two half-bridge topologies) [see Fig. 1(b)]. Another interesting alternative is the three-leg (six switches) converter [4]–[12] (see Fig. 2). In these papers, several aspects concerning the three-leg converter are presented. This paper investigates the control of a three-leg single-phase ac/ac converter. Comparatively to previously referred papers, this work presents several other relevant aspects that have not been previously examined. 1) Pulsewidth-modulation (PWM) control methods based on scalar and space-vector approaches, introducing the concept of local and general apportioning factor (suitable for harmonic distortion reduction) and a complete Manuscript received December 1, 2004; revised April 19, 2005. Abstract published on the Internet January 25, 2006. This work was supported by the Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) of Brazil. The authors are with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande 58109.970, Brazil (e-mail: [email protected]). Digital Object Identifier 10.1109/TIE.2006.870655

equivalence between scalar and space-vector PWM. Furthermore, hardware implementation for PWM control is proposed. 2) A hysteresis current controller capable of operating with the leg shared between the grid side and the load side and a linear digital current controller, which provides zero error at the fundamental frequency. 3) A control strategy for output voltage-regulated applications in order to obtain maximum utilization of the dc-bus voltage, based on the synchronization between input and output converter voltages. In addition, relevant characteristics of the converter are presented, such as voltage rating, harmonic distortion, capacitor current, shared-leg current, and power rating. The converter is compared to four-leg and two-leg converters. Experimental results are presented. II. T HREE -L EG C ONVERTER V OLTAGES The basic scheme of the ac/ac converter presented in this paper is shown in Fig. 2. It comprises three legs (six semiconductor switches) and a capacitor bank at the dc bus. Subconverter G is composed of switches qg , q g , qa and q a . Subconverter L is composed of switches ql , q l , qa , and q a . The leg qa −q a is shared by both subconverters. The conduction state of all switches can be represented by a homonymous binary variable qg , q g , ql , q l , qa , and q a ∈ {0, 1}, where q = 1 indicates a closed switch while q = 0 indicates an open one. Pairs qg −q g , ql −q l , and qa −q a are complementary and, therefore, q g = 1 − qg , q l = 1 − ql and q a = 1 − qa . The pole voltages vg0 , vl0 , and va0 depend on the states of the power switches and may be expressed in terms of previously defined binary variables qg , ql , and qa as E 2 E vl0 = (2ql − 1) 2 E va0 = (2qa − 1) 2 vg0 = (2qg − 1)

(1) (2) (3)

where E is the dc bus voltage (i.e., E = vc ). The phase voltages vg and vl are given by

0278-0046/$20.00 © 2006 IEEE

vg = vg0 − va0

(4)

vl = vl0 − va0 .

(5)

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Fig. 1. Single-phase ac/ac converters. (a) Four-leg converter (two full bridges). (b) Two-leg converter (two half bridges).

Since va0 contributes for both vg and vl , it cannot be calculated independently from (4) and (5). III. PWM C ONTROL The pulsewidths of the gating signals can be directly calculated from pole voltages, which are given by the desired voltages for the grid and the load. If the desired phase voltages are represented as vg∗ and vl∗ , then the reference pole voltages can be expressed as ∗ ∗ vg0 = vg∗ + va0

(6)

∗ ∗ vl0 = vl∗ + va0 .

(7)

∗ Note that these equations cannot be solved unless va0 is specified. The pole voltages satisfy the inequalities

∗ E vg0 ≤ 2

∗ |vl0 |≤

E 2

∗ |va0 |≤

E . 2

(8)

Consequently, the voltage difference must also satisfy a similar inequality, given by ∗ vg − vl∗ ≤ E. (9) Three possible approaches to generate PWM control of the converter are presented next. A. Method I: Constant Shared-Leg Voltage ∗ ∗ An independent control of vg0 and vl0 can be obtained by ∗ specifying that va0 = 0. In this case, from (6) and (7), it follows that ∗ vg0 = vg∗ ∗ vl0 = vl∗ .

(10) (11)

Consequently, the phase voltages vg∗ and vl∗ will be effectively controlled if the following inequalities are valid, i.e., ∗ E vg ≤ 2

and

|vl∗ | ≤

E . 2

(12)

JACOBINA et al.: CONTROL OF THE SINGLE-PHASE THREE-LEG AC/AC CONVERTER

Fig. 2.

469

Single-phase ac/ac three-leg converter.

In this case, the converter has the same voltage rating as obtained for the two-leg configuration shown in Fig. 1(b). The pulsewidths τg , τl , and τa , during which switches qg , ql , and qa must be kept conducting, are T ∗ T , τj = + vj0 2 E

j = g, l, or a.

for

(13)

These pulsewidth values are used in a digital control system that generates the gate command signals (see Section III-B). It is also possible to conceive strategies that permit to vary the voltage rating and harmonic distortion between subconverters ∗ . G and L by using an appropriate selection of va0 B. Method II: Variable Shared-Leg Voltage (Scalar PWM) Relations (6) and (7) can be formulated as ∗ vg0 = vg∗ + vµ∗

(14)

∗ vl0 = vl∗ + vµ∗

(15)

∗ va0

(16)

= vµ∗ . ∗ vg0 ,

∗ solved is how to determine vl0 , and ∗ once the desired voltages vg and vl∗ have

The problem to be ∗ va0 from (14)–(16) been specified. Two approaches can be proposed to solve this problem. Method II-A—General Apportioning Factor: The voltage vµ∗ can be calculated by taking into account the general apportioning factor µ, that is, vµ∗

1 =E µ− 2

The apportioning factor µ (0 ≤ µ ≤ 1) is given by µ=

toi to

(18)

and indicates the distribution of the general free-wheeling period to (period in which voltages vg0 , vl0 , and va0 are equal) between the beginning (toi = µto ) and the end (tof = (1 − µ)to ) of the switching period [13], [14]. The apportioning factor can be changed as a function of the modulation index (mi) to reduce the total harmonic distortion (THD) of converter voltages [13], [14]. In this case, the proposed algorithm is as follows. Step 1) Choose the general apportioning factor µ and calculate vµ∗ from (17). ∗ ∗ ∗ , vl0 , and va0 from (14)–(16). Step 2) Determine vg0 ∗ ∗ , vl0 , Step 3) Calculate pulsewidths τg , τl , and τa from vg0 ∗ and va0 by using (13) and use programmable timers to generate the gate command for the switches. Method II-B—Local Apportioning Factor: The voltage vµ∗ can also be calculated by taking into account the local apportioning factor µs . 1) For the grid (µs = µg ), split the period tog (in which voltages vg0 and va0 are equal) at the beginning (toig = µg tog ) and at the end [tof g = (1 − µg )tog ] of the switching period. 2) For the load (µs = µl ), split the period tol (in which voltages vl0 and va0 are equal) at the beginning (toil = µl tol ) and at the end [tof l = (1 − µl )tol ] of the switching period. That is,

−

∗ µvmax

+ (µ −

∗ 1)vmin

(17)

∗ ∗ where vmax = max V and vmin = min V , where V = ∗ ∗ {vg , vl , 0}. Equation (17) was derived by using the same approach as used to obtain the equivalent one for the threephase PWM modulator [13], [14].

1 ∗ vµs = E µs − − µs vs∗ max + (µs − 1)vs∗ min 2

(19)

where vs∗ max = max Vg and vs∗ min = min Vg if s = g, or vs∗ max = max Vl and vs∗ min = min Vl if s = l, with Vg = ∗ must {vg∗ , 0} and Vl = {vl∗ , 0}. Besides (19), the voltage vµs

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also obey the other converter side. Then, from (14) and (15), ∗ , for s = g and s = l, can be calculated, the limits of vµs respectively, as E − vl∗ , if s = g 2 E = − − vl∗ 2 E = − vg∗ , if s = l 2 E = − − vg∗ . 2

∗ vµs max =

(20)

∗ vµs min

(21)

∗ vµs max ∗ vµs min

(22) (23)

In this case, it is possible to control how the harmonic distortion is split between subconverters G and L. The proposed algorithm is as follows. Step 1) Choose the local apportioning factor µs so that the grid or load subconverter is optimized, and calculate ∗ from (19). vµs ∗ ∗ ∗ limits, vµs Step 2) Determine vµs max and vµs min , from (20) ∗ ∗ to vµs and (21) or (22) and (23). Limit vµs max if ∗ ∗ ∗ ∗ ∗ ∗ vµs > vµs max , and vµs to vµs min if vµs < vµs min . ∗ ∗ ∗ , vl0 , and va0 from (14)–(16) using Step 3) Determine vg0 ∗ . vµ∗ = vµs Step 4) Use Step 3) of Method II-A. Hardware Implementation: The PWM techniques can be adapted for hardware implementation. For example, Fig. 3(b) presents a block diagram for the modulator for method II-B, in which the apportioning factor µg of the grid side is specified. ∗ is calculated from (19). In Fig. 3(b), the initial value of vµs ∗ is obtained by using (20) and (21) The final value of vµs ∗ , vg∗ and vl∗ modulating and the block limitation. From vµs ∗ ∗ ∗ reference signals va0 , vg0 , and vl0 are obtained. The switch command signals are obtained by comparing the three modulat∗ ∗ ∗ , vg0 , and vl0 ) to a high-frequency triing reference signal (va0 angular carrier signal (r = [t/T − 1/2]E for positive derivative and r = [−t/T + 1/2]E for negative derivative). An example of typical signals in that comparison is shown in Fig. 3(a). The block diagram in Fig. 3(b) can be implemented with a specialized integrated circuit. ∗ , Fig. 3. (a) Triangular carrier signal (r), modulating reference signal (vg0 ∗ ∗ va0 , and vl0 ), and switch states qg , ql , and qa . (b) Block diagram for hardware implementation.

C. Method III: Variable Shared-Leg Voltage (Space Vector PWM) The voltages supplied by the power converter can be displayed in the g × l space-vector plane. This vector plane is defined such that voltages vg and vl coincide with the real axis (Re) and the imaginary axis (Im), respectively. A voltage vector in this plane can be represented by vn = vg + jvl

(24)

with n = 1, 2, . . . , 6 as shown in Fig. 4(a). All the instantaneous voltage vectors, which can be generated by the converter topology shown in Fig. 2, are listed in Table I. This table also shows the binary states of the power switches. There are eight voltage vectors: four vectors with amplitude √ E (v1 , v3 , v4 , and v6 ), two vectors with amplitude 2E (v2

and v5 ), and two null vectors (v0 and v7 ), as shown in Table I and Fig. 4(a). These vectors define six sectors associated to each value of K = 1, 2, . . . , 6. The voltages vg and vl take only three different values: E, 0, or −E. Let v∗ = vg∗ + jvl∗ represent the reference voltage to be synthesized by the inverter within one switching cycle of length T . According to the space vector technique [15], [16], the reference vector located in sector K must be synthesized by using two adjacent vectors that define this sector and the zero vectors. Then, for the sector K, it can be written that v ∗ = vn

tn tn+1 t0 t7 + vn+1 + v0 + v7 T T T T

(25)


Fig. 4.

471

(a) Space vectors generated by the converter, sectors, and the reference vector in gl plane. (b) Pulsewidths for sector K = 6. TABLE I VECTOR AND VOLTAGES GENERATED BY THE CONVERTER

Using the general apportioning factor µ for the full converter introduced in the scalar methods, t0 and t7 can be chosen, that is, t0 = tof = (1 − µ)to t7 = toi = µto

with the time weights for each vector being tn , tn+1 , t0 , t7 and restricted to T = tn + tn+1 + t0 + t7 (n = K and n + 1 = 1 if K = 6). By using v∗ = vg∗ + jvl∗ and since v0 = 0 and v7 = 0, it follows from (25) that T , if K = 1 ⇒ t1 = vg∗ − vl∗ E T if K = 2 ⇒ t2 = vg∗ , E ∗T if K = 3 ⇒ t3 = vl , E T ∗ if K = 4 ⇒ t4 = vl − vg∗ , E T if K = 5 ⇒ t5 = −vg∗ , E T if K = 6 ⇒ t6 = −vl∗ , E

t2 = vl∗

T E

T t3 = vl∗ − vg∗ E ∗T t4 = −vg E ∗T t5 = −vl E T ∗ t6 = vg − vl∗ E ∗T t 1 = vg . E

(26) (27) (28)

if

vg∗

D. Equivalence Between Scalar and Space-Vector PWM (30) (31)

> 0,

if vg∗ ≤ 0, if

vg∗

if

vg∗

if

vg∗

vl∗ ≥ 0,

vg∗ > vl∗ ⇒ K = 1

(32)

vl∗

vg∗

(33)

≥ 0,

≤

vl∗

⇒K=2

vl∗ > 0 ⇒ K = 3

< 0,

vl∗

≤ 0,

vg∗

< 0,

vl∗

< 0,

vg∗

≥ 0,

vl∗

< 0 ⇒ K = 6.

where to is a general free-wheeling time to = T − tn − tn+1 . In this case, the relations among µ, µg , and µl , given by (45)–(59) (see next section), can be used to determine µ as a function of the local apportioning factors µg or µl . The space vector modulation technique can be implemented by executing the following steps. Step 1) Given vg∗ and vl∗ , determine K from (32)–(37) and tn and tn+1 from (26)–(31). Step 2) If a general apportioning factor is chosen, use the given µ. If a local apportioning factor is chosen, from (48) and (49) or (53) and (54) or (58) and (59), and given µg or µl —chosen in the allowed range—compute µ [for example, to use a given µg for K = 6, then µ = µg + (µg − 1)t6 /to with t6 /(to + t6 ) ≤ µg ≤ 1]. Step 3) Compute t0 and t7 from (38) and (39), respectively.

(29)

Considering the magnitudes of the components of vector v∗ , i.e., vg∗ and vl∗ , the sector in which v∗ is located can be identified as follows: if vg∗ > 0,

(38) (39)

(34)

ξl /hl and qa = qal if ξg /hg ≤ ξl /hl , where hg and hl are the hysteresis bands for the grid and load side, respectively.

IV. C URRENT C ONTROLLER

V. R ELEVANT C HARACTERISTICS OF THE C ONVERTER

The control of the grid and load current can be realized by using the previous PWM controller with a digital current controller in the outer loop or a hysteresis current control.

Voltage Rating: For sinusoidal voltages and va0 = 0, the voltage amplitude is Vg ≤ E/2 for subconverter G and Vl ≤ E/2 for subconverter L. However, by using previous PWM

µ = µx

(to + t31 ) , to

µ = µz + (µz − 1)

0 ≤ µx ≤ t46 , to

to (to + t31 )

(58)

t46 ≤ µz ≤ 1 (59) (to + t46 )


methods II and III, we can achieve Vg ≤ (1 − n)E and Vl ≤ nE, where parameter n is restricted to (0 ≤ n ≤ 1). For example, if n = 2/3, this implies Vg ≤ (1/3)E and Vl ≤ (2/3)E. In this case, the voltage rating of the output inverter approaches the value obtained for the four-leg converter [Fig. 1(a)]. The increase of the voltage capability of one of the subconverters can be very useful in order to increase the degree of freedom in the design of the subconverters. Capacitor Current: The ac capacitor current contains a second harmonic plus higher frequencies, due to the switching frequency, similar to the four-leg converter [Fig. 1(a)]. Note that the capacitor current in the two-leg converter [Fig. 1(b)] presents, besides the second and higher harmonic frequencies, a fundamental ac current. Shared-Leg Current: The average current iqa (in period T ) for the switch qa is given by ∗ va0 1 + iqa = (63) (ig − il ). E 2 Then, the current flowing through the switch of the shared leg is greater than the current in the other switches. The analysis for switch q a is similar. Ratings of the Converter: The converters shown in Figs. 1(b) and 2 must have a dc-bus voltage that is twice that of the converter shown in Fig. 1(a) in order to provide the same maximum voltage amplitude at the grid and load sides. The maximum current of the switches qg and ql of the three singlephase to single-phase configurations is equal. Because the dc bus voltage twice as much, the power ratings of switches qg and ql of the converters shown in Figs. 1(b) and 2 are equal, but they are twice as much as that for the equivalent switch in the converter in Fig. 1(a). The power rating of switch qa in the three-leg configuration is double that of the sum of the power ratings of qg2 and ql2 in the configuration in Fig. 1(a). For the complementary switches q g , q a , and q l , the analysis of power ratings is similar. VI. S YNCHRONIZATION Converter rating can be improved if it can operate with the same value of the dc bus voltage of the converter shown in Fig. 1(a). It is possible to increase the voltage rating of the threeleg ac/ac converter by using a type of synchronism between input and output converter voltages. This can be used when the grid presents a low rate in the frequency variation and the voltage demanded by the load is sinusoidal with the same frequency of the grid. Considering that vg = Vg cos (ωt − θg ) and vl = Vl cos (ωt − θg − ε), the voltage amplitude is Vg ≤ E for subconverter G and Vl ≤ E for subconverter L if −60◦ ≤ ε ≤ 60◦ .

(64)

That is, the same voltage rating of the four-leg converter can be obtained if the output voltage is synchronized with the input voltage with a margin of 60◦ . For usual converter parameters [1], the variation angle θg (phase angle between eg and vg ) is much smaller than 60◦ .

473

Fig. 6. Block diagram of the control scheme.

This is the case when the system goes from no-load to fullload, for example. Consider that ωl = ωlN + ∆ωl max , where ωlN is the nominal frequency and ∆ωl max is the maximum variation tolerance. Then, the angle |ε|—after its increase due to the variation in θg associated to the power change—can be reduced using the load frequency tolerance ∆ωl max . It is important to consider the case in which only part of the output voltage can be synchronized with the input voltage. For example, this occurs when nonlinearities of the load imply nonfundamental components in vl when a load filter is used (Zf ). In this case, it can be written that vl = vf + el

(65)

where el is the load voltage and vf is the voltage drop across the filter impedance Zf . In this case, it is preferable to synchronize el , instead of vl , with vg . To generate the part related to the voltage vf , it is necessary to add the dc bus voltage by the maximum absolute value of vf (i.e., |vf max |). Then, the dc bus voltage becomes E = E + |vf max |, where E is the dc bus voltage for the case where vf = 0. In this case, if a full-bridge four-leg converter is used, there is a need of the same dc bus voltage. VII. O VERALL C ONTROL S YSTEM Fig. 6 presents the converter control block diagram. The capacitor dc bus voltage vc (vc = E) is adjusted to a reference value by using the controller Rc , which is a standard PI-type controller. This controller provides the amplitude of the reference current Ig∗ . To have power factor control, the instantaneous reference current i∗g must be synchronized with voltage eg . This is obtained via blocks SYN-g and GEN-g. The output angle δg of block SYN-g indicates the instantaneous phase of voltage eg . Synchronization is given by detection of zero crossing of eg associated with a phase-locked loop (PLL) scheme. From the synchronization angle and the amplitude Ig∗ , the current i∗g is generated from block GEN-g. The current

474


controller is implemented by using the controller indicated by the block Ri . The controller Ri used was the digital current controller presented in Section IV-A. The current controller defines the input reference voltage vg∗ . Either the regulation of the load voltage or the operation in open loop is chosen by connection of switch k1 to points a or b; i.e., for an open loop, k1 is connected to point a, for closed loop, k1 is connected to point b. When the output voltage does not need to be regulated, the output reference voltage vl∗ is defined directly from the reference load voltage e∗l . Block Gz permits to include the necessary gain to compensate the additional voltage drop caused by the load filter Zf , when it is used. For closed loop voltage, the controller Rel defines vl∗ . If the load current il , instead of the load voltage, has to be regulated, voltage vl∗ is defined by the current controller Ril and the switch k1 is connected to point c. PWM control is implemented by using one of the methods introduced before. The output reference voltage can be without synchronization (switch k2 is connected to point b) or with synchronization (switch k2 is connected to point a). For the case without synchronization, the instantaneous phase of the output voltage is generated independently by integrating the reference load frequency ωl∗ . When the synchronization mode is used, e∗l (which becomes vl∗ when the load filter Zf is not used) is synchronized with vg∗ . Synchronization is achieved by using the block SYN-l. Block GEN-l is similar to block GEN-g. Block SYN-l is also similar to block SYN-g, but with a limitation in load frequency variation, i.e., ωl = ωlN ± ∆ωl max , where ∆ωl max is the maximum variation chosen for ωl . VIII. H ARMONIC D ISTORTION Fig. 7 presents the load voltage THD for the grid side as a function of the modulation index (mi) employing two-leg, three-leg, and four-leg converters. The weighted THD presented in Fig. 7 has been calculated by p ai 2 100 THD = a1 i i=2

(66)

where a1 is the amplitude of the fundamental voltage component, ai is the amplitude of the ith harmonic, and p is the highest harmonic taken into consideration. Fig. 7(a) presents the THD for two-leg, three-leg, and four∗ =0 leg converters. The three-leg converter operates with va0 (method I), and the four-leg converter operates with µg = 0.5. The switching frequency used was 5 kHz and p = 300. It can be seen that the THD obtained with the three-leg converter is slightly higher than that of the four-leg converter and much smaller than that of the two-leg converter. Fig. 7(b) presents the THD for three-leg converters operating with µg = 0.5 (or the ∗ = 0. value more closed when that value is not possible) and va0 It can be seen that the THD of the converter is improved when it operates with µg = 0.5. These THD results were obtained for vl∗ = −vg∗ (operation in sectors K = 3 and K = 6). When synchronization is used, the THD of the three-leg converter approaches that of the four-leg converter.

Fig. 7. THD of the voltage vg . (a) Two-leg converter (o), three-leg converter for va0 = 0(∗), and four-leg converter (x). (b) Three-leg converter for va0 = 0(∗) and µg = 0.5(+).

IX. E XPERIMENTAL R ESULTS The single-phase ac/ac converters in Figs. 1(b) and 2 have been tested by using a microcomputer-based (Pentium) system. In the experimental tests lg = 6 mH, the capacitors were selected as C = 2200 µF, and the switching frequency employed was 10 kHz. In the experimental results for the three-leg converter, it used method II-A and linear current control. Fig. 8 presents the experimental results (i.e., eg , 10ig , vc , and vl low-pass filtered) for the three-leg converter (Fig. 2) without voltage or current load control supplying an RL load with ωg = 120 πrad/s and ωl = 120 πrad/s. Both capacitor voltage and power factor control are effective, even in presence of some noticeable grid voltage distortions. The load voltage is also adequate. Fig. 9 presents the second experimental results (i.e., eg , 10ig , vc , il and i∗l ) with current load control for ωg = 120 πrad/s and ωl = 60 πrad/s. Besides the input controls, the load current control is effective. It is important to note that it is possible to apply the same approach to obtain a three-phase to three-phase ac-ac converter


Fig. 8. Experimental waveforms for the three-leg converter without voltage or load current control. (a) Voltage and current grid. (b) Capacitor voltage. (c) Load voltage.

475

Fig. 9. Experimental waveforms for the three-leg converter with load current control. (a) Voltage and current grid. (b) Capacitor voltage. (c) Real and reference load currents.

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using five legs—at the place of a standard six-leg converter— sharing a leg between the rectifier and the inverter [19]. This converter has characteristics similar to those of the singlephase converter discussed in this paper. Also, the control strategies discussed here can be adapted for the three-phase case. X. C ONCLUSION This paper has discussed the control of the three-leg singlephase ac/ac reversible converter. The investigation showed that the topology presents a superior performance when compared to the two-leg converter. The PWM control techniques, hysteresis and linear current controls, and the overall control system, including a synchronism strategy to improve the converter rating, have been presented. The concept of local and general apportioning factor has also been proposed. It showed that the choice of the value of the apportioning factor can improve the THD of one of the subconverter voltages. The experimental results showed that the converter operates adequately. R EFERENCES [1] P. Enjeti and A. Rahman, “A new single phase to three phase converter with active input current shaping for low cost ac motor drives,” IEEE Trans. Ind. Appl., vol. 29, no. 2, pp. 806–813, Jul./Aug. 1993. [2] G.-T. Kim and T. Lipo, “Vsi-pwm rectifier/inverter system with a reduced switch count,” in Conf. Rec. IEEE-IAS Annu. Meeting, 1995, pp. 2327–2332. [3] R. L. A. Ribeiro, C. B. Jacobina, E. R. C. da Silva, and A. M. N. Lima, “AC/AC converter with four switch three phase structures,” in Proc. IEEE Power Electronics Specialists Conf. (PESC), 1996, pp. 134–139. [4] I. Ando, A. Moriyama, and I. Takahashi, “Development of a highefficiency flywheel UPS using a 3-arm inverter/converter,” Trans. Elect. Eng. Jpn., vol. 120, no. 1, pp. 77–84, Jul. 1997. [5] I. Ando, I. Takahashi, Y. Tanaka, and M. Ikchara, “Development of a high efficiency UPS having active filter ability composed of a three arms bridge,” in Proc. IEEE IECON, 1997, vol. 2, pp. 804–809. [6] E. B. Shen, “Alternative topological approaches to the electronic ballast,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., MIT, Cambridge, MA, 1997. [7] H. Uematsu, T. Ikeda, N. Hirao, S. Totsuka, T. Ninomiya, and H. Kawamoto, “A study of high performance single phase UPS,” in Proc. IEEE Power Electronics Specialists Conf. (PESC), 1998, vol. 2, pp. 1872–1878. [8] N. Hirao, T. Satonaga, T. Uematsu, T. Kohama, T. Ninomiya, and M. Shoyama, “Analytical considerations on power loss in a three-arm type uninterruptible power supply,” in Proc. IEEE Power Electronics Specialists Conf. (PESC), 1998, vol. 2, pp. 1886–1891. [9] S. J. Park, H. W. Park, J. I. Bae, M. H. Lee, and C. U. Kim, “Development of a high performance single-phase voltage regulator composed of 3 arms bridge,” in Proc. IEEE Int. Symp. Industrial Electronics (ISIE), 1999, vol. 2, pp. 700–705. [10] S. J. Chiang, T. S. Lee, and J. M. Chang, “Design and implementation of a single phase three-arms rectifier inverter,” Proc. Inst. Elect. Eng.— Electr. Power Appl., vol. 145, no. 5, pp. 379–374, Sep. 2000. [11] H. Pinheiro, R. Blume, and P. Jain, “Comparison of SV modulation methods for single phase on-line three-leg UPS,” in Proc. IEEE IECON, 2000, vol. 2, pp. 1328–1333. [12] H. W. Park, S. J. Park, J. G. Park, and C. U. Kim, “A novel high-performance voltage regulator for single-phase ac sources,” IEEE Trans. Ind. Electron., vol. 48, no. 3, pp. 554–562, Jun. 2001. [13] C. B. Jacobina, A. M. N. Lima, E. R. C. da Silva, R. N. C. Alves, and P. F. Seixas, “Digital scalar pulse width modulation: A simple approach to introduce non-sinusoidal modulating waveforms,” IEEE Trans. Power Electron., vol. 16, no. 3, pp. 351–359, May 2001. [14] V. Blasko, “Analysis of a hybrid pwm based on modified space-vector and triangle-comparison methods,” IEEE Trans. Ind. Appl., vol. 33, no. 3, pp. 756–764, May/Jun. 1996. [15] J. Holtz, “Pulsewidth modulation for electronic power conversion,” Proc. IEEE, vol. 82, no. 8, pp. 1194–1214, Aug. 1994.

[16] H. W. Van der Broeck and J. D. Van Wyk, “A comparative investigation of three-phase induction machine drive with a component minimized voltage-fed inverter under different control options,” IEEE Trans. Ind. Appl., vol. IA-20, no. 1, pp. 309–320, Mar./Apr. 1984. [17] C. B. Jacobina, M. B. R. Correa, T. M. Oliveira, A. M. N. Lima, and E. R. C. da Silva, “Current control of unbalanced electrical systems,” in Conf. Rec. IEEE-IAS Annu. Meeting, 1999, pp. 1011–1017. [18] H. Buhler, Reglages echantillonnes, vol. 1, 1st ed. Lausanne, Switzerland: Presses Polytechnique Romandes—Dunod, 1983. [19] C. B. Jacobina, R. L. A. Ribeiro, E. R. C. da Silva, A. M. N. Lima, and T. M. Oliveira, “A reduced switch count three-phase ac motor drive,” in Proc. IEEE APEC, 2001, pp. 378–384.

Cursino Brandão Jacobina (S’78–M’78–SM’98) was born in Correntes, Brazil, in 1955. He received the B.S. degree in electrical engineering from the Federal University of Paraíba, Campina Grande, Brazil, in 1978, and the Diplôme d’Etudes Approfondies and Ph.D. degrees from the Institut National Polytechnique de Toulouse, Toulouse, France, in 1980 and 1983, respectively. From 1978 to March 2002, he was with the Electrical Engineering Department, Federal University of Paraíba. Since April 2002, he has been with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande, Brazil, where he is currently a Professor of electrical engineering. His research interests include electrical drives, power electronics, and control systems.

Talvanes Meneses Oliveira (M’96) was born in Aracaju, Brazil, in 1964. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Federal University of Paraíba, Campina Grande, Brazil, in 1987, 1989, and 2001, respectively. From 1994 to March 2002, he was with the Electrical Engineering Department, Federal University of Paraíba. Since April 2002, he has been with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande, Brazil, where he is currently a Professor of electrical engineering. His research interests include electrical drives, power electronics, and control systems.

Edison Roberto Cabral da Silva (SM’95–F’03) was born in Pelotas, Brazil, in 1942. He received the B.C.E.E. degree from the Polytechnic School of Pernambuco, Recife, Brazil, in 1965, the M.S.E.E. degree from the University of Rio de Janeiro, Rio de Janeiro, Brazil, in 1968, and the D. Eng. degree from the University Paul Sabatier, Toulouse, France, in 1972. From 1967 to March 2002, he was with the Electrical Engineering Department, Federal University of Paraíba, Campina Grande, Brazil. In 1990, he was with COPPE, Federal University of Rio de Janeiro, and from 1990 to 1991, he was with WEMPEC, University of Wisconsin, Madison, as a Visiting Professor. Since April 2002, he has been with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande, Brazil, where he is a Professor of electrical engineering and the Director of the Research Laboratory on Industrial Electronics and Machine Drives. His current research work is in the area of power electronics and motor drives. Dr. Da Silva was the General Chairman of the 1984 Joint Brazilian and Latin-American Conference on Automatic Control, sponsored by the Brazilian Automatic Control Society, and was General Chairman of the IEEE Power Electronics Specialists Conference, PESC’05.