Current-Doubler-Rectifier ZVS PWM Hybrid Full-Bridge Three-Level Converter Wu Chen, Student Member, IEEE and Xinbo Ruan, Senior Member, IEEE Aero-Power Sci-tech Center College of Automation Engineering Nanjing University of Aeronautics and Astronautics Nanjing, 210016, Jiangsu Provice, China Phone: 0086-25-84892053, Fax: 0086-25-84893500 E-mail:
[email protected] Abstract—This paper proposes a zero-voltage-switching (ZVS) PWM hybrid full-bridge three-level converter with currentdoubler-rectifier (CDR), which achieves ZVS for all the switches under wide load range which the use of the energy stored in the output filter inductance, and meanwhile the rectifier diodes commutate naturally, therefore no voltage oscillation across the rectifier diodes occurs. The output current ripple can be reduced significantly compared with traditional full-bridge converter with CDR over the input voltage range. It is very attractive for wide input voltage range applications. The operation principle of the proposed converter is analyzed in this paper, and the condition of ZVS and reduction of output current ripple are discussed. The experimental results are presented to verify the validity of proposed converter.
well. The H-FB TL converter is similar to the hybrid full-bridge converter, the improvement is that is uses only one transformer with the same VA rating as that in conventional full-bridge converter. The dual-bridge dc-dc converter also characterizes significant reduction in the filter inductance and has only one transformer, very similar to the H-FB TL converter [12]. The H-FB TL converter has two bridge legs, one is a TL leg, and the other is a two-level leg. It is easy to achieve ZVS for the switches of the TL leg in a wide load range. However the switches of the two-level leg are difficult to achieve ZVS because only the energy stored in the leakage inductance is used, they will lose ZVS at light load. Voltage oscillation occurs across the rectifier diodes due to the reverse recovery. FB converter with current-doubler-rectifier (CDR) not only achieves ZVS for all the switches in a wide load range, also the rectifier diode commutes naturally without any voltage oscillation [13]. CDR is successfully applied to the half-bridge TL converter with the same features [14]. In this paper the CDR is introduced to the H-FB TL converter, all the switches can realize ZVS in a wide load range and in a wide line range, and the voltage oscillation across the rectifier diodes is eliminated. Moreover, the output inductance current ripple and output current ripple can be reduced compared to the FB converter with CDR.
I. INTRODUCTION In the past decade, switching-mode power supplies are widely used in telecommunication, computer, and other related fields. Phase-shifted full-bridge (FB) converter is a popular topology because zero-voltage-switching (ZVS) or zero-current-switching (ZCS) can be achieved with the leakage inductance of the transformer and the intrinsic capacitors of the power switches [1]-[7]. Moreover the switching frequency is constant, so the optimal design can be obtained. However the output rectified voltage of the FB converter is a two-level waveform. The output inductance increases with the input voltage to limit the maximum current ripple of the output inductance. The hybrid full-bridge converter is a combination of two full-bridge sections sharing a phase leg [8], [9]. When the input voltage is low, the left full-bridge section outputs a voltage waveform with full duty cycle, the right one is phase-shifted controlled; while at high line, the right section operates with zero pulse-width and the left section is phase-shifted controlled. It features significant reduction in the filter requirement. However the combined VA rating of two transformers is larger than the rating of single transformer in conventional full-bridge converter. This depletes the savings gained in the filter component. [10] and [11] proposed a hybrid full-bridge (H-FB) threelevel (TL) converter. It can operate in three-level (3L) mode and two-level (2L) mode, the secondary rectified voltage is close to the output voltage over the input voltage range, so the output inductance can be reduce significantly. The voltage stress of the rectifier diodes can also be reduced as
II. OPERATION PRINCIPLE The proposed ZVS PWM H-FB TL converter with CDR is shown in Fig.1, Cd1 and Cd2 are equal and large enough to share the input voltage Vin evenly, i.e, Vcd1=Vcd2=Vin/2. The switches Q1~Q4, diodes D7 and D8 and flying capacitor Css form the 3L leg. The switches Q5 and Q6 form the 2L leg. Llk is the leakage inductance of the transformer. Cb is the blocking capacitor. Diodes DR1 and DR2, and filter inductances Lf1 and Lf2 form the CDR. Cf is the filter capacitor. Q5 and Q6, Q1 and Q4, and Q2 and Q3 are all 50% duty ratio complementary controlled. When the input voltage is low, there is a small fixed phase-shifted time Tzero between Q2 and Q6, and also between Q3 and Q5, during which the primary current decays rapidly to make the rectifier diodes commutate naturally. Q1 and Q4 are phase-shifted controlled corresponding to Q2 and Q3 respectively. We define the converter operating in 3L mode. When the input voltage increases, or during start-up, overload or short-circuit, Q4 and Q1 are phase-shifted to lagging a little angle α corresponding to Q6 and Q5 respectively. Then Q2 and Q3 are phase-shifted controlled
This work was supported by the National Natural Science Foundation of China (50177013) and the National Natural Science Foundation of Jiangsu Province, China (BK2003419).
0-7803-9033-4/05/$20.00 ©2005 IEEE.
413
Q1
Cd1
D7 Q 2
Vin
A Css D8 Q 3 Cd2
Q4
We define Q1 and Q4 as leading switches, Q2 and Q3 as medium switches，and Q5 and Q6 as lagging switches. Before the analysis, we make the following assumptions: 1) all the switches and diodes are ideal, 2) all inductances, capacitors and transformer are ideal; 3) flying capacitor Css is large enough to be treated as a voltage source with value of Vin/2; 4)output capacitor Cf is large enough to be treated as a voltage source with value of Vo, Vo is output voltage; 5) C1=C2=C3=C4=C3L, Lf1=Lf2=Lf ,C5=C6=C2L.
C1
D1
C2 Cb
D2
+
Llk
_
vCb
Q5
ip
C4
is
B
DR2
RLd + Vo _
Lf 2
C6
Q6
D4
Cf + Lf 1 _
DR1 vDR1
*
*
C3
D3
C5 Tr
D5
D6
Fig.1. Schematic of H-FB TL converter CDR. Q1
Q4
Q2
Q3 Q6
vAB
t
Q2 Q5
t
Q6
Tzero
Vin
A. Three-Level Mode Fig.2(a) shows the key waveforms of the three-level mode. There are 14 switching stages in a switching period, and its equivalent circuits are shown in Fig.3. 1) Stage 1 [t1, t2] [Refer to Fig.3(a)]: Before t1, Q1, Q2 and Q6 conduct, vAB=Vin. DR1 conducts and DR2 is off, the primary side powers the load. At t1, Q1 is turned off, the filter inductance Lf1 is reflected to the primary side to be in series with Llk to charge C1 and discharge C2 via Css. Q1 is turn-off with zero-voltage thanks to C1 and C4. At t2, the voltage of C1 increases to Vin/2, D7 conducts naturally. 2) Stage 2 [t2, t3] [Refer to Fig.3(b)]: At t2, the voltage of C4 is clamped at zero due to the voltage of Css is Vin/2. Thus we can turn on Q4 with zero-voltage. 3) Stage 3 [t3, t4] [Refer to Fig.3(c)]: At t3, Q2 is turned off, the filter inductance Lf1 is reflected to the primary to be in series with Llk to charge C2 and discharge C3 via Css. Q2 is turn-off with zero-voltage thanks to C2 and C3. At t4, vC2=Vin/2, vC3=0, vAB = 0. The current of the Lf1 reaches the maximum value ILfmax_3L. 4) Stage 4 [t4, t5] [Refer to Fig.3(d)]: At t4, D3 conducts, thus we can turn on Q3 with zero-voltage. During this interval, vAB = 0, vcb forces ip to decrease, is decreases correspondingly, which makes DR1 conduct. As the two rectifier diodes conduct simultaneously, both the primary and the secondary side of the transformer are clamped at zero. So vcb is fully applied to Llk, Cb resonates with Llk. -Vo is applied on the two filter inductances respectively, iLf1 and iLf2 decrease linearly.
Q1
t
Tzero
Vin/2
t
Vin/2
Vin ip
t
vCb
iLf1
ILfmax_3L
t
iLf2
iLf1+iLf2
t
ILfmin_3L
iDR2 t0
iDR1
t1 t2 t3 t4 t5 t6 t7 t8
iDR2 t
t9 t10 t11 t12 t13 t14 t15
t16
(a) key waveforms in 3L mode Q4
Q1
Q2
α
Q6
Q4
Q3
α
Q2
Q5
t
Q3
t
Q6
t Vin
Vin/2
vAB
Vin/2
Vin
t
ip
t
vCb iLf1
iLf2
iLf1+iLf2
where ω = 1
Vin/K
Vin/2K t0
t1t2 t3
t4 t5 t6 t7
t8 t9 t10 t11 t12t13 t14
Vin/2K t15t16 t17
t18
(1) (2)
Llk Cb .
Before or during this stage, iLf2 decreases to be negative, and at t5, is decreases to be equal -iLf2, DR2 turns off naturally, and DR1 continues conducting, so the two rectifier diodes commutate naturally. 5) Stage 5 [t5, t6] [Refer to Fig.3(e)]: Q3, Q4 and Q6 continue conducting, vAB = 0. vCb is so small compared with the reflected output voltage that it can be neglected. So the voltage applied on the two filter inductance is approximately -Vo, thus iLf1 and iLf2 continue decreasing linearly. During this interval, is=-iLf2, so ip=-iLf2/K. Because iLf2 decreases and its value is negative, ip is forced
t
ILfmin_2L iDR2
t vDR1
VCb (t4 ) sin ω (t − t4 ) + I p (t4 ) cos ω (t − t4 ) ω Llk
vcb (t) = ωLlk I p (t4 )sin ω(t − t4 ) +VCb (t4 )cosω(t − t4 )
t
ILfmax_2L
iDR1
iDR2
i p (t ) = −
t
(b) key waveforms in 2L mode Fig.2. Key waveforms of the proposed converter.
corresponding to Q6 and Q5 respectively. We define the converter operating in 2L mode.
414
Q1 Vin/2
D7
Q2 Css
D8
A
Q3
Vin/2 Q4
D1
C1 C2 Cb
D2
D3 D4
Q5
Llk
C5 Tr
D5 ip
*
DR1
C4
Q6
Vin/2
+ _ Vo
D8
Lf2 DR2
C6 D6
D7
Q2 Css
is
B
C3
Lf1
*
Q1
iLf1
A
Q3
Vin/2
iLf2
Q4
D1
C1 C2 Cb
D2
D3 D4
Q1 D7
Q2 Css
D8
A
Q3
Vin/2 Q4
D1
Cb
D2
D3 D4
Q5 Llk
C5 Tr
D5 ip
*
DR1
C4
Q6
Q1
iLf1 Lf1
*
Vin/2 +_ V o
D8
Lf2 DR2
C6 D6
Q1 D7
Q2 Css
D8
A
Q3
Vin/2 Q4
D1
C2 Cb
D3 D4
Q5 Llk
C4
C5 Tr
D5 ip
C4
Q6
Q1 D7
Q2 Css
D8
A
Q3
Vin/2 Q4
D1
*
DR1
C2 Cb
D3 D4
Q5 Llk
Lf1
* is
+ _ Vo
Lf2 DR2
C6 D6
C5 Tr
D5 ip
*
DR1
iLf2
C4
Q6
iLf1 Lf1
*
+_ V o
is
B
C3
DR2
C6 D6
Lf2 iLf2
(d) [t4，t5] Q1 Vin/2 D7
Q2 Css
D8
A
Q3
Vin/2 Q4
D1
C1 C2 Cb
D2
Q5 Llk
C5 Tr
D5 ip
*
DR1
D4
C4
+_ V o
is Lf2
C3 Q6
iLf1 Lf1
*
B D3
DR2
C6 D6
iLf2
(e) [t5，t6] Q1 Vin/2 D7
Q2 Css
D8
A
Q3
Vin/2 Q4
D1
C1 C2 Cb
D2
Q5 Llk
C5 Tr
D5 ip
*
DR1
D4
Q6
+_ V o
is Lf2
C3 C4
DR2
C6 D6
iLf2
(f) [t6，t7] Q1 Vin/2
D7
Q2 Css
D8
A
Q3
Vin/2 Q4
D1
C1 C2 Cb
D2
D3 D4
Q5 Llk
C3 C4
C5 Tr
D5 ip
*
DR1
iLf1 Lf1
* is
B
Q6
+_ V o
Lf2 C6 D6
+ _ Vo
Lf2 DR2
C6 D6
iLf2
D1
C1 C2 Cb
D2
Q5 Llk
C5 Tr
D5 ip
*
D4
Q6
+_ V o
is Lf2
C3 C4
iLf1 Lf1
*
B D3
DR1
C6 D6
DR2
iLf2
B. Two-Level Mode. Fig.2(b) shows the key waveforms of the 2L mode. There are 14 switching stages in a switching period, among which [t1, t6] is the same as [t3, t8] in the 3L mode. In the following, only the operation during [t6, t8] is analyzed. Fig.4 shows the equivalent circuits of [t6, t8]. 1) Stage 1 [t6, t7] [Refer to Fig.4(a)]: At t6, ip increases in the negative direction, charging C4 and discharging C1 via Css. Both the primary and secondary windings voltage begin to decrease until the voltage of C4 increase to Vin/2, i.e., vC4= Vin/2, vC1= 0, so Q1 can be turned on with zero-voltage. vAB =-Vin/2, then D8 conducts naturally. 2) Stage 2 [t7, t8] [Refer to Fig.4(b)]: Q3, Q5 and D8 conduct, vAB=-Vin/2, DR1 conducts and DR2 is off, the primary side powers the load.
iLf1 Lf1
*
B D3
is
to increase. At t6, the current of the L f12 reaches the minimum value I Lfmin _ 3L , and it is a negative value. 6) Stage 6 [t6, t7] [Refer to Fig.3(f)]: At t6, Q6 is turned off. ip charges C6 and discharges C5, Q6 is zero-voltage turn-off thanks to C5 and C6. At t7, vC6=Vin, vC5=0, vAB = -Vin, so D5 conducts naturally. The time period of stage 6 is: t67 = 2C2 LVin I p (t6 ) = −2 KC2 LVin I Lf min_ 3L (3) where K is the ratio of primary and secondary windings of the transformer. 7) Stage 7 [t7, t8] [Refer to Fig.3(g)]: As D5 conducts, Q5 can be turned on with zero-voltage. During this interval, vAB = -Vin, Llk is quite small, vcb can be neglected compared with Vin, so iLf1 decreases and iLf2 increases linearly. Because ip= - iLf2/K, ip decreases linearly. The voltage of Cb continues increasing. At t8, ip decreases to zero, and the voltage of Cb reaches its maximum value. After this stage, ip increases in the negative direction, and the voltage of Cb begins to decrease. At t9, Q4 is turned off, starting the second half cycle, which is similar to the first half cycle.
iLf1
C1
D2
Q3
Vin/2
iLf2
(c) [t3，t4]
Vin/2
Q6
Lf1
*
B
C3
iLf1
(b) [t7，t8] Fig.4. Equivalent circuits of switching stages during [t6, t8] in 2L mode.
B
C3
A
Q4
C1
D2
Q2 Css
(b) [t2，t3]
Vin/2
D7
is
B
C3
*
DR1
(a) [t6，t7]
C1 C2
C5 Tr
D5 ip
(a) [t1，t2]
Vin/2
Q5 Llk
DR2
iLf2
(g) [t7，t8] Fig.3. Equivalent circuits of switching stages in 3L mode.
415
III. REALIZATION OF ZVS FOR THE SWITCHES
current of output filter inductance reaches its minimum value, which is negative, e.g., at t4 as shown in Fig.2(b). Refer to Fig.2(b), we can obtain t6 t9 t18 I o ⋅ Ts (10) = ∫ iLf 2 (t )dt + ∫ iLf 2 (t ) dt + ∫ iLf 2 (t ) dt 4 6 9 t t t 2 V D I Lf max_ 2 L − I Lf min_ 2 L = o (1 − 2 L )Ts (11) Lf 2
A. Three-Level Mode From the above analysis, we can get that the leading leg realizes ZVS with the energy stored in the output filter inductance, at t1 as shown in Fig.2(a). Medium leg realizes ZVS using the energy stored in the output filter inductance when the current of output filter inductance reaches its maximum value, e.g., at t3 as shown in Fig.2(a). Lagging leg realizes ZVS using the energy stored in the output filter inductance when the current of output filter inductance reaches its minimum value, e.g., at t6 as shown in Fig.2(a). t2 t4 t14 Io ⋅ Ts (4) = ∫ iLf 1 (t )dt + ∫ iLf 1 (t )dt + ∫ iLf 1 (t )dt t0 t2 t4 2 V I Lf max_ 3L − I Lf min_ 3 L = o ( 1 + Tzero ⋅ f s )Ts (5) Lf 2
Vin V (12) ( D2 L − ∆D2 L ) + in ∆D2 L 4⋅ K 2⋅ K where D2L is the duty cycle in 2L mode represented by Vo =
D2 L = (t8 − t4 ) ILfmin_2L =
(8)
Ilead = I Lf max_3L −
Vin − 2 ⋅ K ⋅Vo 2K ⋅Vo ⋅ Ts (1 − 2T ' − ) 2 ⋅ K ⋅ Lf V in
(9)
V ⋅ (V − 3Vo ) ⋅ Ts Vin − 2K ⋅Vo = o in + ⋅ I Lf min_2L Vin ⋅ L f Vin − K ⋅Vo
(14)
IV. DESIGN CONSIDERATIONS The input specifications: Vin=200~400VDC, Vo=54VDC, Io=10A, K=1.5, fs=100kHz. From the above analysis, we can know that the output filter inductance Lf, blocking capacitor Cb and Tzero are coupled together, and their values are desired by certain tradeoff principle, and calculated synthetically. As a filter inductance, it is better to be larger. However in order to realize ZVS for the lagging leg at full load, it should be quite small. So we should determine the maximum value of the filter inductance to ensure ZVS for the lagging leg at full load. In 3L mode, Eqs.(3) and (7) can lead to Eq.(15), and in the same way, can lead to Eqs.(16) in two-level mode.
where T ' = Tzero ⋅ f s , Ilead is the output filter inductance current when leading switch is turned off, e.g., at t1 as shown in Fig.2(a). From Eqs. (7), (8) and (9), we can deduce that the larger the output current is, the larger ILfmax_3L and Ilead is, while the smaller |ILfmin_3L| is, so the leading leg and medium leg is easier to realize ZVS at heavy load than at light load, while the lagging leg is easier to realize ZVS at light load than at heavy load. From the above analysis, we can know that the worst case is to achieve ZVS for the lagging leg at full load.
Lf
max_ 2 L
=
−Λ+
4 ∆ 2 ⋅ V o ⋅ K ⋅ (V in − 3V o ) + Λ 2 2 ∆ 2 ⋅ K ⋅ V in ⋅ f s V in − K ⋅ V o
(16)
Where ∆ = −2 K ⋅ C2 L ⋅Vin , Λ=2∆⋅(2K⋅Vo −Vin)+Iomax⋅(Vin −K⋅Vo). t45
Eqs.(15) and (16) illuminate that Lfmax is determined by Vin, Tzero and t67 (or t45, essentially the same). The chosen MOSFET (IRFP450) as the switches of the lagging leg, its turn-off time tf = 44ns, intrinsic capacitor Coss=720pF at Vds=25V, Coss is non-linear and inversely proportional to the square root of the voltage [15], so the intrinsic capacitor can be expressed approximately as (17) Coss = 720 × 10−12 × 25 Vds
B. Two-Level Mode In 2L mode, medium leg realizes ZVS using the energy stored in the output filter inductance when the current of output filter inductance reaches its maximum value, e.g., at t1 as shown in Fig.2(b). Lagging leg realizes ZVS using the energy stored in the output filter inductance when the L f max_3L =
(13)
From (13) and (14), we can obtain the same conclusion as in the 3L mode.
, Tzero is the fixed
Vo 1 ' ( + T )Ts Lf 2
.
Vin −2K⋅Vo − (Vin −2K⋅Vo)2 −Vin⋅ Lf ⋅ K⋅ Io ⋅ fs +Vo ⋅ K⋅(Vin −3Vo) K⋅Vin⋅ Lf ⋅ fs
I Lf max_2L
phase-shifted time between the medium leg and lagging leg, during which vAB= 0, primary current ip decrease rapidly and force two rectifier diodes commutate naturally. From Eqs. (4), (5) and (6), we can obtain I V (1 + 2T ' ) I Lf min_ 3L = o − o + 2 4L f ⋅ fs (7) Vin 2 (1 − 2T ' )2 + 8 K 2Vo 2 − 6 KVoVin (1 − 2T ' ) 8L f ⋅ f s ⋅ Vin ⋅ K ILf max_3L = ILf min_3L +
Ts 2
Vin −K⋅Vo
Vin V (6) ⋅ D3L + in (1 − 2Tzero ⋅ f s − D3L ) 2K 4K Where Ts is the switching period, fs is the switching frequency, D3L is the duty cycle in three-level mode
represented by D3 L = (t1 − t0 )
and ∆D2 L = (t6 − t4 )
From Eqs. (10), (11) and (12), we can obtain
Vo =
Ts 2
Ts 2
The effective intrinsic capacitance value is Coss multiplied by a factor 4/3, so C2L can be expressed as
2t67 ⋅ K ⋅Vo ⋅Vin ⋅ (1 + 2T ' ) − t67 ⋅ [Vin2 (1 − 2T ' )2 + 8K 2Vo2 − 6KVoVin (1− 2T ' )] 16K 2 ⋅ C2L ⋅Vin2 ⋅ fs + 4Io max ⋅ t67 ⋅ fs ⋅ K ⋅Vin
416
(15)
30 (uH) Lfmax (Vin,0.4)
12 (A) ILfmax (200 , Io)
10
ILfmax (300 , Io)
28
ILfmax (400 , Io)
Lfmax(Vin,0.6)
8
−ILfmin ( 200 , Io) −ILfmin ( 300 , Io)
Lfmax(Vin,0.8) 26
6
−ILfmin (400, Io) Ilead (200, Io)
24 200
Fig.5. The curves of Lfmax versus Vin and Tzero.
300 Vin(V)
400
1.3
0
5
y_3L (300,10 , Cb,0.6 )
VCb (Vin , I o , Cb , Tzero ) =
0
5
10
0.3
1
2
Cb(uF)
3
4
4 4 C2 L = × 720 × 10−12 × 25 Vds = × 720 × 10−12 × 25 Vin 3 3
6
8
I Lf max_ 3 L ⋅ sin ωTzero ⋅ ω ⋅ Llk K (1 + cos ωTzero )
X(Vin, Io,Cb,Tzero ) = Io ⋅Ts −(Ts + 2Tzero)⋅ ILf min_3L −
10
+
(22)
From Eqs.(1) and (19), we can obtain −ILf min_3L −VCb (t4 ) sinω(t6 −t4) + I p (t4 ) ⋅ cosω(t6 −t4) ≤ ωLlk K max_ 3 L
(20)
K , t6-t4=Tzero.
Eq.(20) can lead to y _3LV ( in, Io,Cb,Tzero) = ILf min_3L + ILf max_3L
ω⋅Tzero ω
⋅ ⋅ X(Vin, Io,Cb,Tzero) ≤ 0 2 2
Vo ⋅ (Ts + 2Tzero)2 4Lf
In the same way, we can obtain in 2L mode
(18)
In order to reduce the turn-off loss of the lagging leg at light load, we choose t67=6tf at full load. The value of Lfmax is determined only by Vin and Tzero when t67 is chose. Assuming Dsecmax=0.8 at lowest input voltage, Tzero should not be larger than 0.8µs when we think of the dead time. Fig.5 shows the plot of Lfmax versus input voltage Vin and Tzero. In order to realize ZVS within the whole voltage range, Lfmax should be smaller than 24.3µH when Tzero=0.4µs, smaller than 25µH when Tzero=0.6µs, smaller than 25.5µH when Tzero=0.8µs, respectively. However when Tzero choose 0.8µs or larger, the maximum secondary duty cycle will be limited, and it is disadvantageous for the optimum design to the converter. So we temporarily choose 24.3µH as the value of Lfmax. which is the smaller one of the two former. As shown in Fig.2(a), the rectifier diodes finish commutation at t5 in three-level mode, The worst case is that t5 = t6, at which ip reduces to –ILfmin_3L/K. I p (t6 ) = − I Lf min_ 3L K (19)
−tg
Io (A)
where
5
Fig.6. The curves of y_3L(Vin,Io,Cb,Tzero) and y_2L(Vin,Io,Cb).
where I p ( t 4 ) = I Lf
4
cos ωTzero ⋅ X (Vin , I o , Cb , Tzero ) 2 K (1 + cos ωTzero ) ⋅ Cb
y_2L (400, 10, Cb ) 0
2
Fig.7. ILfmax，-ILfmin and Ilead at different load current under the minimum, nominal and maximum input voltage.
y_3L (200,10 , Cb,0.6 )
y_3L (300, 10, Cb, 0.4)
2 0
10
y_3L (200, 10, Cb,0.4 )
4
Ilead (300, Io)
(21)
417
y _ 2 L(Vin , I o , Cb ) = I Lf max_ 2 L + I Lf min_ 2 L + (2 − D2 L ) ⋅ [(2 − D2 L )Vo ⋅ Ts + 4 I Lf min_ 2 L ⋅ L f )] f s ⋅ ctg
8L f Ts (1 − D2 L ) 4 Llk Cb
−
Io 2
(23) ≤0
⋅ Llk Cb
From the above analysis, we can know that the worst case for lagging leg realizing ZVS is at full load. So Io in both functions is selected with value of 10A in Fig.6. From Fig.6, we can see that when the input voltage is the same, the smaller the Tzero is, the smaller Cb is. If Tzero=0.4µs, Cb should be smaller than 0.8µF and 0.5µF is selected in practice, and vcb is approximate 16V obtained from Eq.(22). If Tzero=0.6µs, Cb should be smaller than 1.3µF and 1µF is selected in practice, and vcb is approximate 8V obtained from Eq.(22). Calculating synthetically, we select Tzero=0.6µs and Cb=1µF. Cb=1µF also meets the requirement of realizing ZVS in 2L mode. Refer to Fig.5, we select Lfmax=25µH. As the filter inductance Lf is determined, from Eqs.(7), (8), (9), (13) and (14), we can obtain the relationship of ILf_max, -ILf_min and Ilead versus Vin and Io, as shown in Fig.7. Fig.7 illuminates that providing the lagging leg can realize ZVS at the full load under the minimum input voltage, both the medium leg and lagging leg can realize ZVS from nearly no load to full load under the input voltage range. There are some inflexions in the curves which are corresponding to the critical current between continuous current mode (CCM) and discontinuous current mode (DCM). The calculation process of DCM is omitted due to the space limit. Fig.7 also illuminates that the leading leg can realize ZVS under wide load range in 3L mode. It also can realize ZVS
converter with CDR and H-FB TL converter with CDR. It can be seen that both the filter inductance current ripple and the output current ripple of the proposed converter are reduced significantly compared to FB converter with CDR. It is helpful to the design of the output filter and loss reduction.
in 2L mode from the analysis of Section II. V. RIPPLE CURRENT COMPARISON A. Comparison of Filter Inductance Current Ripple The filter inductances of the two converter (one is the FB converter with CDR [13] and another is the proposed H-FB TL converter with CDR) are approximately the same. The filter inductance of FB converter is 28µH and it is 25µH in the proposed converter. From FB converter with CDR, we can obtain 2V ⋅ K DFB = o (24) Vin
∆I _ L f _ FB =
Vo ⋅ Ts D ⋅ (1 − FB ) 2 L f _ FB
VI. EXPERIMENTAL RESULTS
(25)
From above analysis about H-FB TL converter with CDR, in 3L mode, we can get V ⋅T 1 T ∆I _ L f _ HFB _ 3L = o s ⋅ ( + zero ) (26) L f _ HFB 2 Ts In 2L mode, we can obtain 4V ⋅ K DHFB _ 2 L ≈ o Vin ∆I _ L f _ HFB _ 2 L =
(27)
DHFB _ 2 L Vo ⋅ Ts ) ⋅ (1 − 2 L f _ HFB
B. Comparison of Output Current Ripple From FB converter with CDR, we can obtain V ⋅T ∆I o _ FB = o s ⋅ (1 − DFB ) L f _ FB
(28)
(29)
From above analysis about H-FB TL converter with CDR, in 3L mode, we obtain D ⋅T V ∆I o _ HFB _ 3L = 3 L s ⋅ ( in − 2Vo ) (30) 2 L f _ HFB K In 2L mode, we can obtain V ⋅T ∆I o _ HFB _ 2 L = o s ⋅ (1 − DHFB _ 2 L ) L f _ HFB
vDR1: [100V/div]
vAB: [250V/div]
ip: [10A/div]
vcb: [20V/div]
(31)
iLf1: [10A/div]
iDR2: [5A/div]
iDR1: [5A/div]
iLf2: [10A/div]
Fig.8 shows the current ripple comparison between FB
Time: [2us/div]
Time: [2us/div]
9(a) vAB, ip, vCb, iLf1 and iLf2
20 (A) ∆Io_FB ( Vin )
In order to verify the operation principle of the proposed converter, a 540W (54V, 10A) output power prototype converter was built in our lab. The parameters of the converter are: Vin=200~400VDC; Vo=54VDC; Io=10A; fs=100kHz; Llk = 0.59µH; Cb = 1µF; Lf1 = Lf2 = 25µH. Fig.9 and Fig.10 show the experimental results at full load under 250V and 400V input voltage respectively. Fig.9 (a) and Fig.10(a) show vAB, the primary current ip, the blocking capacitor voltage vCb and the currents of the two filter inductance iLf1 and iLf2, which illustrates that when vAB=0, vCb forces ip to decrease rapidly to make the rectifier diodes commutate naturally. It can be seen that there is no voltage spike and oscillation on the rectifier diodes from Fig.9(b) and Fig.10(b). Fig.11 and Fig.12 show the gate drive signal vGS, the voltage across the drain and source vDS and the current flow through the switch iD of the leading switch Q4, medium switch Q3 and lagging switch Q5 at light load (1A) under 250V and 400V input voltage respectively., which illustrate that all the switches realize ZVS and the voltage stress on both chopping switch and leading switch is the half of the input voltage. Fig.13 shows the conversion efficiency at different load current under different input voltage. The maximum efficiency is 93.2%.
9(b) vDR1, iDR1 and iDR2
Fig.9. Experimental results at Vin =250V and Io =10A.
16 vAB: [250V/div]
∆ Io_HFB( Vin ) 12
vDR1: [100V/div]
ip: [10A/div]
∆ I_Lf_FB(Vin )
8
vcb: [20V/div]
∆ I_Lf_HFB ( Vin )
iLf2: [10A/div]
4
iLf1: [10A/div] iDR1: [5A/div]
Time: [2us/div]
0
200
250
300 Vin (V)
350
10(a) vAB, ip, vCb, iLf1 and iLf2
400
iDR2: [5A/div]
Time: [2us/div]
10(b) vDR1, iDR1 and iDR2
Fig.10. Experimental results at Vin =400V and Io =10A.
Fig.8. Ripple current comparison between FB converter with CDR and H-FB 3L converter with CDR..
418
vGS (Q4): [25V/div]
vGS (Q3): [20V/div]
vDS (Q4): [100V/div]
vDS (Q3): [100V/div]
- The voltage stress of the switches of the three-level leg is the half of the input voltage. - All the switches can realize ZVS in a wide load range with the energy of the filter inductances. - The rectifier diodes commutate naturally without voltage oscillation and voltage spike. - Reducing the filter inductance current ripple and output current ripple. - It is suited for wide line voltage range. The operation principle of the proposed converter is verified by a 540W prototype converter, and the experimental results are also included in this paper.
iD (Q4): [2A/div] iD (Q3): [5A/div] Time: [2us/div]
Time: [2us/div]
11(a) vGS, vDS and iD of Q4
11(b) vGS, vDS and iD of Q3
vGS (Q5): [25V/div] vDS (Q5): [250V/div]
REFERENCES [1] iD (Q5): [5A/div]
[2]
Time: [2us/div]
11(c) vGS, vDS and iD of Q5 Fig.11. Experimental results at Vin =250V and Io =1A. [3] vGS (Q3): [20V/div]
vGS (Q4): [25V/div]
[4]
vDS (Q3): [100V/div]
vDS (Q4): [100V/div]
[5] [6]
iD (Q3): [5A/div]
iD (Q4): [5A/div] Time: [2us/div]
Time: [2us/div]
12(a) vGS, vDS and iD of Q4
12(b) vGS, vDS and iD of Q3 [7]
vGS (Q5): [25V/div] vDS (Q5): [250V/div]
[8] iD (Q5): [5A/div]
[9]
Time: [2us/div]
12(c) vGS, vDS and iD of Q5 Fig.12. Experimental results at Vin =400V and Io =1A. [10]
95 90
[11]
Efficiency (%)
85 80
[12]
75 70
[13]
200V 300V 400V
65 60
[14]
55 0
2
4 6 8 10 Output Currnet (A) Fig.13. Conversion efficiency of the proposed converter.
12
[15]
VII. CONCLUSIONS This paper proposes a CDR ZVS PWM H-FB TL converter, which has following advantages:
419
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