Design Challenges and Methodologies in 3D Integration for Neuromorphic Computing Systems M. Amimul Ehsan1, Hongyu An1, Zhen Zhou2, and Yang Yi1 1
Department of Electrical Engineering and Computer Science, University of Kansas, Lawrence, KS 66045 2 Intel Corporation, 3600 Juliette Ln, Santa Clara, CA 95054, USA 1
[email protected],
[email protected],
[email protected],
[email protected] and nano-device technologies, the energy efficient hardware implementation of neuromorphic system is quite demanding. However, current two dimensional (2D) integrated circuit technology is approaching its physical and material limits [57]. Only way forward is the integration in the third dimension [8] [9]. Three dimensional (3D) integration is a promising solution, which provides high system speed, high density, low power consumption, and small footprint [10] [11]. In a 3D neuromorphic system, the neural layers are enabled by using through silicon vias (TSVs) which are composed of metal conductor and isolated by dielectrics from the semiconductor substrate. This high aspect ratio vertical interconnects route the signals through the layers of neuron chip and provides lower interconnect length and smaller footprint. Due to the massive number of TSVs involved to realize huge parallelism, the electromagnetic coupling might be significant in TSV arrays among the stacking. Crosstalk induced in 3D IC is one of the biggest reliability issues [12] because strong coupling network among the TSVs can cause the system to malfunction. Comparing to the magnetic coupling, the electrical coupling is stronger in 3D neuromorphic system attributing to the silicon substrate conductance and the thickness of the dielectric material used in TSVs. For pursuing large bandwidth and high density TSV array design, the size of TSVs is shrinking down continuously and is approaching nanometer scale [13]. It can causes an increase in crosstalk and limits the performance of the device if the improper physical design and geometric arrangement of TSV arrays are employed. Therefore, it is very important to build reliable and efficient TSV arrays in 3D neuromorphic chip for proper signal transmission and power dissipation. To accomplish this, it is necessary to have a critical investigation to maintain appropriate signal/ground TSV to minimize the crosstalk and maintains the parallelism between the layers as well. It is challenging to find out an optimal differential signal assignment from a massive number of arrays that will reduce the crosstalk. In this work, we have studied the force directed optimization algorithm that compares the electrical performance of differential signal pairs of TSV array with the distributed ground and find out the optimal one. An electrical model of the optimal differential signal TSV array is proposed and the investigation of crosstalk is carried out to obtain a full S parameter description in frequency domain.
Abstract Neuromorphic computing is an emerging technology that describes the biological neural systems and implementation of its electrical model in complementary metal–oxide– semiconductor (CMOS) VLSI systems. As the neural networks are wire dominated complicated system with myriad interconnected elements, it requires massively parallel processing for the computational task. However, the hardware implementation experiences some critical challenges and unsurmountable obstacles by using 2D planar circuits. Therefore, the potential three dimensional integration technology can be applied in hardware implementation of neuromorphic computing that provides a sustainable and promising alternative to the existing conventional integrated circuit (IC) technology by allowing vertical stacking of dies. 3D hardware interconnection between the neural layers not only offer high device interconnection density with greater reduction in parasitic, it also provides improved channel bandwidth using fast and energy efficient links with excellent distribution and communication among the neuron layers. Beyond these opportunities, it needs a thorough investigation to explore all the design issues and critical challenges for successful implementation of 3D neuromorphic computation for high performance application. In this work, we studied the design challenges of the 3D integration technology for neuromorphic computing systems, and possible ways to overcome the limitation of well-connected synaptic system.
Keywords Neuromorphic Computing, Three Dimensional Integrated Circuit, CMOS, Modeling, and Simulations.
1. Introduction Neuromorphic computing system is the electronic implementation of neural system, in which a class of electronic devices mimic and implement the relative characteristics of biological neural networks in their physical circuit layout [1-3]. It’s a rapidly growing field of research that describes the deep understanding between the morphology of neurons, electrical circuit model, and overall architectures of biological nervous system that requires a very precise and intelligence computation. The basic biological neuron consists of soma, dendrite, synapses, and axon which can be integrated into a VLSI model of neuron [4]. Using the dominant complementary metal oxide semiconductor (CMOS) integrated circuit (IC) 978-1-5090-1213-8/16/$31.00 ©2016 IEEE
24
17th Int'l Symposium on Quality Electronic Design
2. Neuromorphic Circuit Design using 3D IC Technology Human brain is the most extraordinary computing machine which can beat the most powerful supercomputers on the planet in many specific tasks such as image and pattern recognition, speech recognition, and so on. And even more, human brain accomplishes all these tasks at extremely fast speed with very low power consumption. There is an increased needs for computer scientists to achieve human brain functionalities by mimicking its structure with 1011 and 1012 neurons, which are connected to form an extremely complex network in three dimensions. To rebuild the functionalities of human brain, two fundamental components of neural systems, neurons and synapses, are needed to be modeled and designed. Several neuron circuits have already been designed with various applications in telecommunications, fuzzy control, and pattern recognition. In biology field, the synaptic weight between two neurons can be modified by the neurotransmitter and this function is widely believed highly related with learning capability. According to the discoveries on functionality of synapse in biology field, a new two-terminal device memristor, which conductance can be incrementally modified by precisely controlling charges or flux through it, has been adopted in synapse design. The memristor crossbar synapse network can potentially offer connectivity and function density comparable to those of biological systems [14] [15]. However, the massive parallelism among neurons is hampered by traditional 2D planar circuit, and this limitation has become the bottleneck to achieve the complexed neuromorphic hardware systems. One possible solution to achieve the complexity of a very large neuromorphic hardware systems is to combine the neuromorphic circuit design with an emerging technology named “3D IC”. 3D IC stacking is a promising technology with numerous advantages: 1) reducing latency and power consumption due to shorter wires, 2) improving bandwidth between stacked layers by offering multiple connections using TSVs, 3) enabling the integration of heterogeneous layers. One of the main drawbacks of 3D IC technology is the increased power density and thermal issue, which are highly related to the chip operational frequency. When we observe and comprehend the advantages and disadvantages of neuron system hardware implementation with 3D IC technology, we found that neural networks would benefit from 3D stacking and furthermore avoid the issues of 3D IC on its traditional integrated circuit field application which ICs generally are operating at very high frequency. If the neural network layers are implemented on 3D stacking structure, the numerous 3D connections formed by TSVs, silicon interposer or micro-bumps between hardware layers can offer the high-density connections required between two neural network layers. Moreover, compared to traditional high clock frequency ICs, hardware neural networks can easy operate at a low power density and reduce the risks of thermal hot spots thanks to both the distribution of computations among neurons, and the
capability of high-speed parallel signal processing which enables a low operating clock frequency. Though, the neuromorphic technology and artificial neural network computation has been very popular during last couple of decades but the hardware implementation of 3D neuromorphic system is a very recent one [16]. Reviewing the literatures, it has been found that there are very few works has been done in neuromorphic computing using 3D integration technology. To the best of our knowledge, there is no thorough investigation exists to explore all the design issues and critical challenges for successful implementation of 3D neuromorphic computation for high performance application. In [8], an analog leaky integrate-and-fire neuron is designed using the TSV and capacitive functionality of spiking neurons in neuromorphic architecture is discussed. In [17], high density 3D neuromorphic hybrid network for efficient hardware platform is developed. In [18], an architecture of a 3D stacked neuromorphic accelerator is designed and implemented for scaling up the efficiency of hardware neural network. In [9], the gain of the neural network clique using 3D technology is explored. All of these aforementioned paper didn’t taken into account the parallelism issues of 3D neuromorphic system in their work. We have worked with the massive parallelism issue to get a significant contribution from it. Without making the appropriate parallelism of 3D interconnect of neuromorphic chip by suitable placement, we cannot get benefited more from this potential technology. The subsequent section presents modeling the optimal TSV array and analysis of crosstalk.
3. MODELING OF OPTIMAL TSV ARRAY Exploiting the physics of silicon technology using VLSI circuits, neuromorphic 3D chips can be fabricated for the production of biophysical process. Being the wire dominated system, hardware implementation of neural network contains large number of parasitics. Also, the neural system maintains numerous effective channels for excellent communication. Therefore, the transmission line theory can be applied for exploring the electronic model of 3D neuromorphic system that uses TSV for signal transmission. The transmission line parameters are needed that built the RLGC model for TSV array. An analytical model of a single ended rough surface TSV is established using two wire transmission line RLGC parameter [19]. Using the force directed optimization algorithm, an optimal TSV array is obtained [20] and now, the analytical modeling of the TSV array is proposed. For the modeling purpose and simplicity of the circuit, a particular portion of the optimized TSV array has been selected from the large 4×11 optimized TSV array. Figure 1 represents the particular section where 4 pairs of differential signal TSV is surrounded by 4 ground TSV and it maintains the same differential pair sequences that is found from the optimized structure by using the force directed optimization algorithm. In this model, the modified RLGC parameters of
transmission line is used and applied for the four differential signal pairs of the optimized TSV arrays.
where is the mutual inductance and L is the selfinductance of TSV. The mutual capacitance used for two TSV pair is represented by the equation, = (2) where represents the permittivity of the vacuum, is the relative permittivity of the substrate material, is the pitch between two TSV, and is the radius of the TSV. Using SiO2 as a dielectric between the TSV conductor and silicon substrate, a capacitance of coaxial form is obtained, = (3) _ (
Figure 1. Optimized differential signal TSV assignment for modeling From the physical configuration of the differential signal TSV array, the equivalent circuit model in Figure 2 is proposed which is composed of different electrical parameters of TSV.
)
is the permittivity of and is the radius of where . Two wire transmission line formulas are applied here for the modeling of our TSV array [19]. The modified RLGC elements of the equivalent circuit are given by, =
1−(2 / )2
=
(4)
( /2 ) + ( /2 ) − 1 + (
= =
1
0
( /
)
( /
)
( /
)
( /
)
)
(5)
(6) (7)
is the permeability of the free space, is the where and are the conductivity of the TSV conductor, conductivity and permittivity of the substrate material, respectively. All the parameters are expressed in per unit length. This analytical model of differential TSV includes the parasitic elements that represents loss and coupling.
4. ANALYSIS OF RESULTS Figure 2. Equivalent circuit of optimized differential signal TSV The inductance and resistance of the TSV is characterized by L and R respectively, C_SiO2 represents the capacitance of the dielectric layer between the conductor of TSV and the substrate. The parallel conductance and capacitance of the silicon substrate is denoted by G and C respectively where G represents the lossy characteristics of the semiconductor substrate. Each of the port of the differential signal TSV represents the pair of input and output separately. Assuming a homogenous medium, the mutual inductance between the two adjacent differential signal pair TSV is calculated by the coupling coefficient k, = (1)
This section represents the frequency domain and time domain simulation results for analysis of crosstalk of optimized TSV array. The proposed model of the optimized differential signal TSV is validated by comparing the frequency domain simulation performed by using High Frequency Structural Simulation (HFSS) [21]. Time domain simulation is being performed to compare the crosstalk of optimized and non-optimized TSV array.
Frequency domain analysis To perform the crosstalk analysis, two adjacent differential signal TSVs are considered in the optimized TSV array. The modeling and simulation results are demonstrated in frequency domain by means of near and far end crosstalk. Due to the coupled electromagnetic field, the strong mutual capacitance is more important of closely spaced TSVs for the selected frequency range of the 3D neuromorphic structure. Among different factors for coupling, we have considered the geometric arrangement which one is the most important factor especially for large
number of TSVs in neuromorphic chip. Because it produce a larger capacitance and hence an increased capacitive coupling that leads to higher mutual capacitance and coupling noise that results a larger crosstalk. 0
Time domain analysis For the performance comparison between the optimized and non-optimized differential signal array, step response simulation has been performed. The step response of nonoptimized and optimized TSV array is plotted in Figure 5 and Figure 6 respectively. From the obtained results, the transient noise for both the cases of TSV arrays can be found. m2 Time = 39.06 nsec V_NEXT = 0.003 Max
Simulation Model
-40
-60
-80
-100
m1 Time = 5.115 nsec V_NEXT = - 0.001 Min
V_NEXT (Volts)
NEXT (dB)
-20
0
100
200
300
400
500
Time (µs)
Frequency (MHz)
Figure 3. Analytical model and simulation of Near-end crosstalk for optimized TSV array (mag)
Figure 5. Step response simulation in near end crosstalk for non-optimized TSV pattern
FEXT (dB)
-20
Simulation Model
-40
V_NEXT (Volts)
0
m2 Time = 7.015 nsec V_NEXT = 0.002 Max m1 Time = 86.17 nsec V_NEXT = - 0.000 Min
-60
-80
Time (µs) -100
0
100
200
300
400
500
Frequency (MHz)
Figure 4. Analytical model and simulation of Far-end crosstalk for optimized TSV array (mag) The equidistance signal ground-signal is considered in both the model and simulation. The magnitude for near end and far end crosstalk are plotted in Figure 3 and Figure 4 for two adjacent differential signal pairs. It can be seen from these plots that there is a decent correlation and nice agreement between the proposed circuit model and the simulation results. Though there is a little bit difference in the model and simulation results but it’s not more than 6% which is quite acceptable. Far end crosstalk is reduced compared to the near end crosstalk because of the capacitive coupling that is constructive at near end and destructive at far end. Far end crosstalk from the circuit model is reduced by 5dB compared to near end crosstalk and the far end cross crosstalk from simulation is reduced by 2dB at 500 MHz.
Figure 6. Step response simulation in near end crosstalk for optimized TSV pattern Through our time domain analysis, the peaks of the transient noise voltages of non-optimized TSV array are 0.003 V max and -0.001 V min, where the peak to peak noise voltage of non-optimized TSV array is 4 mV. In contrast, the peak transient voltages of optimized TSV array are 0.002 V max and 0.000 v min, so peak to peak noise voltage of optimized TSV array is 2 mV. Therefore, the transient analysis verified the optimized and non-optimized differential signal TSV structure performance of neuromorphic 3D systems.
5. CONCLUSION Three dimensional integration technology has inherent potentiality that can be incorporated with neuromorphic system to develop energy efficient next generation technology. In this paper, we worked on the significant reduction of crosstalk noise that appears due to the huge parallelism between the neural hardware layers. An optimum
differential S/G TSV array is obtained by using force directed optimization algorithm that could minimize the crosstalk noise. An electrical model of optimal TSV structure is proposed and the investigation of crosstalk is carried out in frequency domain. The analytical model of proposed differential TSV is verified with the simulation results.
REFERENCES [1] Mead, C. 1989. Analog VLSI and neural systems.
[11] Takahashi, K., and Sekiguchi, M. 2006. Through
[12]
[13]
Addison-Wesley, Boston, MA, USA. [2] Renaud, S., Tomas, J., Lewis, N., Bornat, Y., Daouzli,
[3]
[4]
[5]
[6] [7]
[8]
[9]
[10]
A., Rudolph, M., Destexhe, A., and Saïghi, S. 2010. PAX: A mixed hardware/software simulation platform for spiking neural networks. Neural Networks 23, 7(Sep. 2010) 905–916. Koickal, T.J., Hamilton, A., Tan S. L., Covington, J.A., Gardner, J.W., Pearce, T.C. 2007. Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip. IEEE Trans. Circuits Syst. 54, 1(Jan. 2007), 60-73. Hasler, J., and Marr H. B. 2013. Finding a roadmap to achieve large neuromorphic hardware systems. Front. Neurosci. 7, 118(Sep 2013). Brink, S., Nease, S., Hasler, P., Ramakrishnan, S., Wunderlich, R., Basu, A., and Degnan, B. 2013. A learning-enabled neuron array IC based upon transistor channel models of biological phenomena. IEEE Trans. Biomed. Circuits Syst. 7, 1 (Feb. 2013), 71-81 Indiveri, et al. (2011) Neuromorphic silicon neuron circuits. Front. Neurosci. 5,73 (May 2011) Schölkopf, B., Platt, J., and Hofmann, T. 2006. A selective attention multi-chip system with dynamic synapses and spiking neurons. In Proc. Adv. Neural Info. Process. Syst. Conf., 2006, 111-119. Joubert, A., Duranton, M., Belhadj, B., Temam, O., and Heliot, R. 2012. Capacitance of TSVs in 3D stacked chips a problem? Not for neuromorphic systems. In Proc. DAC’12. (Sanfrancisco, CA, USA, Jun 3-7, 2012), pp. 1260–1261. Boguslawski, B., Sarhan, H., Heitzmann, F., Seguin, F., Thuries, S., Billoint, O., Clermidy, F. 2015. Compact interconnect approach for networks of neural cliques using 3D technology. In proc. IEEE Int. Conf. VLSI (5-7 Oct. 2015). Knickerbocker, J. U., Andry, P. S., Dang, B., and Horton, R. R. 2008. Three dimensional silicon integration. IBM Journal of Research and Development, 2008.
[14]
[15]
silicon via and 3-D wafer/chip stacking technology. Digest of Technical Papers, 2006. Xie, B., Swaminathan, M., Han, K. J., and Xie, J. 2011. Coupling analysis of through-silicon via (TSV) arrays in silicon interposers for 3D systems. In proc IEEE Int. Sym. Electromag. Compat.,(14-19 Aug, 2011). Qian, L., Xia, Y., Liang, G. 2015. Study on crosstalk characteristic of carbon nanotube through silicon vias for three dimensional integration. Microelectronics Journal, 46, 7, (July 2015), 572–580. M. Hu, H. Li, Y. Chen, Q. Wu, G. Rose, and W. Linderman, “Memristor Crossbar Based Neuromorphic Computing System: A Case Study,” IEEE Transactions on Neural Network and Learning System (TNNLS), vol. 25, no 10, pp. 1864-1878, (Oct. 2014). M. Hu, H. Li, Y. Chen, X. Wang, and R. E. Pino, “Geometry Variations Analysis of TiO2-based and Spintronic Memristors,” the 16th Asia and South Pacific Design Automation Conference (ASPDAC), (Jan. 2011), pp. 25-30.
[16] Indiveri, G., Barranco, B. L., Legenstein, R.,
Deligeorgis, G., Prodromakis, T. 2013. Integration of nanoscale memristor synapses in neuromorphic computing architectures. Nanotechnology, (2013), 24, 38. [17] Ryan, k., Tanachutiwat, s., and Wang, w., 2009. 3D CMOL Crossnet for Neuromorphic Network Applications. Nano-Net, Springer Berlin Heidelberg, 3, (2009), 1-5. [18] Belhadj, B., Valentian, A., Vivet, P., Duranton, M., He, L., Temam, O. 2014. The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators. In proc. Int. Conf. on Compilers, Architec. Synth for Embedded Syst. (12-17 Oct. 2014), 1-9. [19] Ehsan, M. A., Zhou, Z., and Yi, Y., 2015. An Analytical Through Silicon Via (TSV) Surface Roughness Model Applied to a Millimeter Wave 3-D IC. IEEE Transactions on Electromagnetic Capability. 57, 4, (Aug. 2015), 815-826. [20] Yi, Y., Liu, Y., Zhou, Y., Becker, W.D. 2009. Minimizing crosstalk in high-speed differential buses by optimizing power/ground and signal assignment. In proc. of 18th IEEE Elect. Perform. Electron. Packag. Sys. (19-21 Oct. 2009). [21] Ansoft HFSS. [Online]. Available: www.ansys.com.
