EAM Cascode Push-Pull CML ... - IEEE Xplore

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2017.2699328, IEEE Transactions on Circuits and Systems II: Express Briefs

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS Jeongho Hwang, Student Member, IEEE, Gyu-Seob Jeong, Student Member, IEEE, Woorham Bae, Member, IEEE, Jun-Eun Park, Member, IEEE, Chang Soo Yoon, Jung Min Yoon, Student Member, IEEE, Jiho Joo, Gyungock Kim, and Deog-Kyoon Jeong, Fellow, IEEE

Abstract—This paper presents a 32 Gb/s driver for a Mach-Zehnder modulator (MZM) and an electro-absorption modulator (EAM). A push-pull current-mode logic (CML) driver is chosen to achieve a better power efficiency and a large voltage swing. A double cascode with thin oxide transistors is employed to mitigate the over-voltage stress associated with a large output voltage swing. At the same time, shunt-peaking inductors are incorporated in a compact way to extend the bandwidth and to have a flat group delay. The proposed driver has been fabricated using 65 nm CMOS technology with an active area of 0.086 mm2. The electrical measurement result shows that the driver exhibits a differential output swing of 4 V pp at 10 Gb/s. The measured extinction ratios (ER) of the driver using the MZM and EAM are 4.53 dB and 4.17 dB, respectively, at 32 Gb/s. The power consumption is 201 mW at 32 Gb/s, which corresponds to an energy efficiency of 6.28 mW/Gb/s. Index Terms—Silicon photonics, push-pull driver, low-voltage differential signaling (LVDS), Mach-Zehnder modulator (MZM), Electro-absorption modulator (EAM), current-mode logic (CML) driver, CMOS.

A

I. INTRODUCTION S data rates required for digital communication continue to

rise, silicon photonics has become one of the most promising candidates for the next generation of high-speed link technology. Recently, various types of modulators for silicon photonics have been developed, i.e., a Mach-Zehnder modulator (MZM) and an electro-absorption modulator (EAM). The MZM introduces interference between two optical paths using electro-optic effects [1]. The EAM absorbs different amounts of the light depending on the reverse bias voltage [2]. Both modulators require a large input swing in order to achieve This paragraph of the first footnote will contain the date on which you submitted your paper for review. It will also contain support information, including sponsor and financial support acknowledgment. J. Hwang. G.-S. Jeong, J.-E. Park, C. S. Yoon, J. M. Yoon, and D.-K. Jeong are with the Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: [email protected], [email protected]). W. Bae is with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA. J. Joo and G. Kim are with the Electronics and Telecommunications Research Institute, Daejeon 341129, South Korea. Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier

VDD Vbiasp

Mp5

Mp1 inph

Mp2

Mp3

Mp4

Vb outn

Rmain Lmain Lmain Rmain

Mn3 Deep N-Well Vb

Vb

innl

inpl Vbiasn

houtn

Vb

Mn2

Mn1

2.7V 1.7V

MZM or EAM

outp Mn4

Vcm

innh

Deep N-Well

houtp

1.5V 0.5V

Mn5

Fig. 1. The proposed cascode push-pull main driver with shunt-peaking.

a sufficient extinction ratio (ER) [1], [2]. To generate the large swing, a digitally controlled distributed amplifier [3], [4], multi-stage driver [5], and pull-down only drivers [6]−[8] have been proposed. However, the abovementioned drivers consume high power, typically larger than 10 mW/Gb/s. Among the various types of drivers, we analyze and compare the power and swing of pull-down only current-mode logic (CML) driver and the push-pull CML driver in this paper. The push-pull CML driver is proposed as the most efficient candidate and optimized for MZM/EAM applications to improve the power efficiency and 32 Gb/s operation, which is shown in Fig. 1. The cascode structure is added in the proposed driver in order to alleviate the over-voltage stress while achieving a sufficiently large voltage swing of 4 V ppd [1], [8]−[10]. In addition, shunt-peaking inductors are placed in series with the load resistors for the pre-driver and the main driver to extend the bandwidth and to achieve a flat group delay response simultaneously [11]. This brief is organized as follows. Section II details the architecture of the proposed cascode push-pull CML driver with shunt peaking. Section III shows the results of measurement, and Section IV concludes this brief. II. PROPOSED MODULATION DRIVER ARCHITECTURE A. Power-efficient push-pull CML architecture Two types of current-mode signaling schemes, pull-down

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RL

I1

outp

3Vov

GND Z0

outn

Vb

I0

inn IPD

houtn RS=Z0

houtp RS=Z0

innh Vb outp Vb innl

RL

3Vov

Vcm

IPP

276

200

GND

Z0

65.2%

96

100 0

0.5

I0

inpl

houtn RS=Z0

1.5 Swing [V]

2

2.5

3

Pull-down only Push-pull

400 300

65.2%

200 100 0

50

outn Vb

1

(a)

500

0

inph Vb RL

Vcm

Power [mW]

VDD

∆(Swing)

I1

300

600

3Vov

IPP

400

700

(a)

VDD

500

0

Vb inp

Pull-down only Push-pull

600

Power [mW]

RL

VDD-RLIPD/2

∆(Swing)

VDD

700

VDD

RL ∆ 2RS

RL [Ω]

100

150

(b)

houtp RS=Z0

(b)

Fig. 2. Driver comparison of pull-down only driver and push-pull driver. (a) Pull-down only driver: data ‘1’ and (b) push-pull driver: data ‘1’.

only driver and push-pull driver, are shown in Fig. 2. Both schemes drive the modulator, terminated with R S matched to the transmission line impedance Z 0 . Drivers include load resistors R L and cascode transistors biased with the bias voltage V b to reduce the voltage stress. Further, DC block capacitors are used to decouple the bias condition of the modulator from that of the driver. The following analyses assume that the DC block capacitors are settled to their final DC values. The focus of the analyses is the difference between the source currents and the required supply voltages to achieve the same single-ended peak-to-peak output swing (∆). As shown in Fig. 2(a), the common-mode DC voltage at the output of the pull-down only driver is V DD −RLIPD/2 and the single-ended peak-to-peak output swing ∆ is expressed as IPD(RLRS)/(RL+RS). Assuming that the input and current source transistors have the same overdrive voltage Vov and operate at the edge of the saturation region, the minimum required supply voltage is (RL/(2RS)+1)∆+3Vov. The load resistors RL in the pull-down only driver carry current only in one direction; however, bipolar current flow is possible for the push-pull driver as shown in Fig. 2(b). When the data ‘1’ is driven at the node outp, the current I1 flows from the load resistor RL on the left to the load resistor on the right. On the contrary, the current I0 representing data ‘0’ flows in the opposite direction. Using the same assumption used in the pull-down only driver, the minimum supply voltage is ∆+6Vov. Fig. 3 compares the power consumption of the pull-down

Fig. 3. Comparison of the estimated power consumption between the pull-down only logic and push-pull logic: (a) RL=100 Ω and (b) varying RL.

only driver and the push-pull driver analytically. Compared with the pull-down only driver, the push-pull driver requires only half the current to achieve the same output swing. When all overdrive voltages of the transistors are assumed as Vov for comparison, the power consumption for the pull-down only driver (PowerPD) and the push-pull driver (PowerPP) with the minimum power supply can be calculated as  1 RL R L+ R S  (1) = + 1)∆  ∆ Power PD  3V ov + ( 2 RLRS  RS  ∆ R L+ R S  (2)  3V ov + 2  ∆ . RLRS   From equations (1) and (2), it can be determined that the push-pull driver is more power-efficient than the pull-down only driver. Power consumption versus the load resistance is also shown in Fig. 3(b) with a 2-V single-ended peak-to-peak swing. The graph shows that the large load resistance makes the driver more power-efficient. However, the larger resistance than the impedance of the transmission line degrades the signal integrity and sacrifices speed performance due to under termination at the source. The value of the load resistor RL is chosen as 100 Ω as a trade-off achieving a good power efficiency while satisfying the bandwidth requirement as [12], whereas 50 Ω resistors are used in previous works, [1], [4], [7], [8]. In addition, difference between pull-up current and pull-down current makes the rise and fall times asymmetric. The common mode voltage is supplied to solve these issues. = Power PP

B. Cascode architecture For a large output voltage swing, a cascode structure with thin-oxide transistors is used to protect the transistors from the over-voltage stress while achieving both high bandwidth and large swing. In addition, deep n-well NMOS transistors (Mn3,


1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0

Mp1 Mn1

20

Mp3 Mn3

Magnitude [dB]

1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0

0

1

2

Time [ns] (a)

3

4

Mp1 Mn1

5

0 -20 BW-3dB =7GHz

-40 w/o L w/ opt. L

-60 -80

1

BW-3dB =17GHz

10

100

Frequency [GHz] (a)

Mp3 Mn3

60 50

195

196

197

198

Time [ns] (b)

199

200

Fig. 4. Post-layout simulations: voltage stress, Vds, on output transistors (a)before settlement of the ac coupling capacitor (0~5 ns) and (b) after settlement (195~200 ns).

Group delay [ps]

Vds [V]

Vds [V]


7ps

40

20ps

30 20 w/o L w/ opt. L

10 0

1

10

100

Frequency [GHz] (b)

Fig. 6. Simulated frequency response of the overall transmitter: magnitude and group delay in the case of without inductors and with optimized inductors. TABLE I.

OPTIMIZED INDUCTANCE AND RESISTANCE L [pH]

R [Ω]

1 CML buffer (L1, R1)

510

65

2nd CML buffer (L2, R2)

330

30

Level converter (L3, R3)

330

30

Main driver (Lmain, Rmain)

510

100

st

Fig. 5. Overall architecture of the transmitter.

Mn4) have their body nodes connected to their source, mitigating the voltage stress further and eliminating the body effect [1], [8]. The body nodes of the PMOS transistors (Mp1−Mp4) are also connected to their sources for the same reason. As a result, the drain-source voltage stress of the cascode transistors are less than 1.2 V during the transient and steady state as shown in Fig. 4. Since the required voltage range is different between the pair of NMOS (Mn1−Mn2) and PMOS (Mp1−Mp2) transistors for the main driver, high-speed sub-blocks such as the pre-driver and the level converter are designed for the optimum pre-driver swing. Fig. 5 shows the overall architecture of the transmitter. Pre-drivers and a level converter are implemented with a

pull-down only driver configuration, since they do not require a large output swing. A differential input of 1-V swing is applied to the first buffer. The output of the second buffer is applied to the level converter to generate a high common-level input for the proposed push-pull CML driver. The level converter uses an on-chip AC-coupling capacitor Cb of 1.8 pF and an on-chip DC-bias resistor Rb of 10.2 kΩ. It achieves a cut-off frequency of 8.7 MHz, which is sufficiently low to transmit a 32 Gb/s PRBS7 data pattern. The pre-drivers and the level converter utilize shunt-peaking inductors for the bandwidth extension. Shunt-peaking inductors, using only a metal-8 (M8) layer, are optimized using an EM simulation tool for the compact area and the proper frequency response for transmitting high-speed signals. C. Area-efficient shunt peaking inductors As shown in Fig. 5, it is essential to consider the interface parasitics of the chip such as the pad capacitance and bond wire inductance since they become critical when a high-speed signal is transmitted. The pad capacitance is 80 fF and bond wire inductance is 500 pH. In order to verify the optimal operation of



330 µm Level Converter

inp

Main Driver

outp 260 µm

CML Buffer

Diff. Input

Bias

Level Converter

inm

~2Vpp

Diff. Output

50ps/div

outm

Fig. 7. Die photomicrograph.

-0.5

-20

-1.0

-30

-1.5

-40

-2.0

-50

-2.5

-60

-3.0

0

10 Frequency [GHz]

20

Fig. 8. Measured S-parameters: S11 and S21.

BER

S11 [dB]

-10

Fig. 10. Measured electrical single-ended eye diagram at 10 Gb/s.

0.0

S11 S21

S21 [dB]

0

10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -0.4

28 Gb/s 32 Gb/s 0.52 UI 0.24 UI

-0.3

-0.2

-0.1

0.0 0.1 Time [UI]

0.2

0.3

0.4

Fig. 11. Measured electrical bathtub curve using 28 Gb/s and 32 Gb/s PRBS7.

tr1

Jpp1

tf1

tr2

Jpp2

tf2

ER: 5.08 dB, Pavg=611.8uW


(b)

(a) Rise time (10% to 90%)

Fall time (90% to 10%)

Jitter (Peak-to-peak)

(a) CM OFF

tr1 = 56 ps

tf1 = 52 ps

Jpp1 = 12.67 ps

(b) CM ON

tr2 = 50.65 ps

tf2 = 50.65 ps

Jpp2 = 9.34 ps

Fig. 9. Measured rise/fall time and peak-to-peak jitter comparison at 10 Gb/s. (a) CM Off and (b) CM On.

shunt-peaking inductors for transmitting high-speed signals, the magnitude response and group delay response of the overall transmitter are simulated. As shown in Fig. 6, the transmitter offers the bandwidth of 17 GHz and exhibits a peak-to-peak group delay variation of 7 ps over the range of 1−17 GHz, which is sufficiently low for the target bandwidth. Shared shunt-peaking inductors for both pull-up and pull-down paths are used instead of using separate inductors, which make the driver area-efficent. The optimized values of the inductors and resistors used for the entire transmitter are described in Table I. III. MEASUREMENT RESULTS Fig. 7 shows the die photomicrograph of the prototype chip fabricated using the 65 nm CMOS process. The active area of the driver is only 0.086 mm2. Since the proposed driver uses a partially terminated load, a reflection characteristic of the electrical channel is important. Therefore, the test board with its traces designed in microstrip is verified by the EM simulation tool to keep the reflection loss S11 and the transmission gain S21 within an acceptable level. Measured results show S11 below -15 dB and S21 above -3 dB at 20 GHz for a differential input/output trace as shown in Fig. 8. The electrical eye diagram of the proposed driver is measured by an Agilent

10ps/div

(a)

10ps/div

(b)



10ps/div

(c)

10ps/div

(d)

Fig. 12. Measured optical eye diagrams. (a) 28 Gb/s MZM, (b) 32 Gb/s MZM, (c) 28 Gb/s EAM, and (d) 32 Gb/s EAM.

86100D DCA-X wide-bandwidth oscilloscope. Rise/fall times and peak-to-peak jitter are compared in Fig. 9. Rise/fall time mismatch and peak-to-peak jitter becomes larger with the common mode node floating. The measured single-ended output swing is 2 Vpp at 10 Gb/s, as shown in Fig. 10. Fig. 11 shows that the proposed driver has timing margins of 0.52 UI and 0.24 UI at the bit error rate (BER) of 10-12 for 28 Gb/s and 32 Gb/s, respectively. The bathtub curve is measured by an Anritsu MP1800A signal quality analyzer. The prototype driver is connected to a 40 Gb/s LiNbO3 MZM with a polarization controller and a 1:1 splitter via the DC block module. It is later connected to a 43 Gb/s Oki EAM laser module, which includes both EAM and the distributed feedback laser (DFB) in the same module. The optical eye diagrams for the MZM and EAM are measured by the same oscilloscope used for the electrical eye



TABLE II. PERFORMANCE COMPARISON

Technology Main topology

TVLSI'16 [1]

ISSCC'13 [3]

OFC'15 [4]

ISSCC'15 [5]

TVLSI'14 [6]

ASSCC'15 [7]

65 nm CMOS

180 nm BiCMOS

65 nm CMOS

65 nm CMOS

130 nm CMOS

65 nm CMOS

Pull-down Distributed Distributed amplifier only VML amplifier

Multistage

Pull-down only CML

Pull-down only CML

Letter'15 [13]

This Work

65 nm CMOS

130 nm CMOS

65 nm CMOS

Pull-down only CML

Push-Pull VML

Push-Pull CML

TCAS'16 [8]**

Supply voltage [V]

1.0/2.0/3.0

-5.2/5

4.5

1.25/2.5

1.2/4.0

1.2/3.3

Type 1 1.5/2.3/2.6

Type 2 1.5/3.9

1.6/3.3

1.5/2.7/3.3

Data rate [Gb/s]

10

10

25

25

20

25

20

25

20

32

Power [mW]

98

2130

520

275

900

480

534

348

312

201

Output swing [Vpp,diff]

4.4

6

6.4

5

7

3.3

5

3.8

3.4

4(@10Gb/s)

Single-ended ER[dB]

N/A

N/A

1.07*

3.1*

9.78 (@10Gb/s)

N/A

N/A

N/A

5.01

4.53(MZM) 4.17(EAM)

Active area [mm2]

0.04

0.95

N/A

0.6

0.72

0.029

0.068

0.038

N/A

0.086

Bias-T

X

X

X

X

O

O

O

X

X

X

F.O.M [mW/Gb/s]

9.8

213

20.8

11

45

19.2

26.7

13.9

15.6

6.28

*Calculated from differential ER **Driver type1 & type2

diagram. The optical eye diagrams are shown in Fig. 12. PRBS7 data pattern is passed directly to the driver for both MZM and EAM without any bias-T. ERs of 5.08 dB at 28 Gb/s and 4.53 dB at 32.4 Gb/s are measured in MZM while ERs of 4.59 dB at 27.8 Gb/s and 4.17 dB at 32.4 Gb/s in EAM. With the differential configuration of the MZM and EAM, ER can be improved by 3 dB as in [4]. The pre-driver composed of first and second CML buffers consumes 49 mW utilizing a 1.5 V supply. The level converter carries the drive voltage to the upper voltage range while dissipating 49 mW with a 2.7 V supply. The core block, the main driver, consumes 103 mW with a 3.3 V supply as estimated in Section II. The entire transmitter consumes 201 mW. Compared with the state-of-the-art works shown in Table II, the proposed transmitter achieves the highest power efficiency of 7.18 mW/Gb/s at 28 Gb/s and 6.28 mW/Gb/s at 32 Gb/s for both modulators. IV. CONCLUSIONS A power-efficient 32 Gb/s MZM/EAM driver incorporating the push-pull CML driver configuration is designed and fabricated using the 65 nm CMOS process. Analysis shows that the push-pull driver is able to offer the same voltage swing with less power consumption compared with the pull-down only driver. Power efficiency can be improved further as a larger voltage swing is required. To alleviate the over-voltage stress, cascode transistors are used. Furthermore, shunt-peaking inductors are used to extend the bandwidth and to achieve the flat group delay response in an area-efficient way. As a result, power consumption is reduced to only 201 mW with a 32 Gb/s PRBS7 data stream for driving the MZM and EAM.

[2] [3] [4] [5]

[6] [7] [8] [9] [10] [11] [12] [13]

ACKNOWLEDGMENT This work was supported by the Electronics Telecommunications Research Institute (ETRI).

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and

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