IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 7, JULY 2012
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Effect of Annealing Temperature on TiO2-Based Thin-Film-Transistor Performance Ni Zhong, Jun Jun Cao, Hisashi Shima, and Hiro Akinaga
Index Terms—Annealing, semiconductor–insulator interfaces, thin-film transistors (TFTs), titanium oxide (TiO2 ).
To prepare high-performance TiOx TFTs, a well understanding of how the bulk crystallinity and the interface structure affect the TFT performance is required. In this letter, the bottom-gate top-contact TFTs were prepared with sputtered TiOx as the channel and SiO2 prepared by plasma-assisted chemical vapor deposition (PCVD) as the gate insulator layer. By the postannealing process at various temperatures, the crystallinity of the TiOx and TiOx /SiO2 interface structure was modified, which were probed by X-ray diffraction (XRD) and Fourier transform infrared (FTIR) spectra. The corresponding change of the TFT performance on the annealing temperature was studied. The mechanism of the performance variation on the annealing temperature is discussed.
I. I NTRODUCTION
II. E XPERIMENTS
ITANIUM oxide (TiOx ) exhibits promising application in areas ranging from photovoltaic and photocatalysis to photo-/electrochromics and sensors [1]. Enormous efforts have been devoted to the research on TiOx for the application of nanoscale electronic devices, such as resistive random access memory and memristive devices [2]–[6]. Moreover, TiOx is promising to use in transparent electronics due to the transparency [7], [8]. Therefore, considerable interest has been also attracted on applying TiOx as the semiconductor channel layer in the thin-film transistors (TFTs). The n-type transistor characteristics have been observed in the devices with rutile single crystal, anatase film, or amorphous TiOx thin film as channel [7]–[12]. Some reports suggested the characteristics of the bulk TiOx layer such as high crystallinity and multiplicity of the Ti oxidation states of TiOx as the origin for the high performance of the TFTs [7], [8], [10], [12]. Aside from bulk characteristics of channel materials, the channel/gate dielectric interface has been reported to play a role on the TFTs characteristic. Therefore, not only the TiOx crystallinity but also the TiOx /gate dielectric interface should be considered.
A doped n-type single crystal silicon wafer covered with a 400-nm-thick thermally grown silicon dioxide (SiO2 ) was used as the substrate. A conventional photolithography process was used to fabricate TFTs. Gate electrode Al was first prepared by thermal vacuum evaporation. After the gate insulator of 150-nm-thick SiO2 was deposited at 250 ◦ C by PCVD, the TiOx channel layer with a thickness of 20 nm was deposited by radio-frequency magnetron sputtering deposition. The target was TiO2 with a purity of 99.99%. The sputtering was performed under a mixture of argon (Ar) and oxygen (O2 ) atmosphere at a ratio of 9.5:0.5 sccm, and the working pressure was kept at about 0.5 Pa. Finally, Al source and drain electrodes were prepared by thermal vacuum evaporation. Al was selected because an ohmic contact can be obtained between Al and TiOx [13]. The channel length L and width W of the TFTs were 10 and 100 μm. The fabricated devices were postannealed in vacuum at various temperatures from 100 ◦ C to 500 ◦ C for 30 min with the heating rate of 1 K/s. Transistor characteristics were evaluated at room temperature in air using an Agilent 4156C semiconductor parameter analyzer. To examine the TiOx /SiO2 interface state, the infrared absorption spectra were recorded at room temperature (Thermo Scientific, Nicolet 6700). The crystal structure was evaluated by XRD (Rigaku, Ultima X) employing Cu Kα radiation. The chemical state of Ti ions close to the TiOx /SiO2 interface was also investigated by the electron energy loss spectroscope (EELS) analysis.
Abstract—TiOx thin-film transistors (TFTs) are fabricated using SiO2 as gate dielectrics. The enhancement of the electric characteristics is observed after a postannealing processing including the reduction of the threshold voltage Vth , the increase in mobility μ, and the on/off ratio. The effect of the postannealing temperature on both the TiOx /SiO2 interfacial bonding structure and the TiOx crystallinity is investigated. We suggest that the interfacial modification at the TiOx /SiO2 interface contributes to the significant reduction of Vth due to the breaking of Si–O–Ti bonding. The improvement of the TiOx crystallinity and interfacial structure leads to the increase in μ and in the on/off ratio. The low-temperature annealing treatment at 200 ◦ C is very effective to improve the TiOx /SiO2 interface structure.
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Manuscript received March 15, 2012; revised March 30, 2012; accepted March 31, 2012. Date of publication May 14, 2012; date of current version June 22, 2012. The review of this letter was arranged by Editor Z. Chen. N. Zhong is with the National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki 305-8568, Japan, with CREST, Japan Science and Technology Agency, Tokyo 100075, Japan, and also with the Laboratory of Polar Materials and Devices, East China Normal University, Shanghai 200241, China (e-mail:
[email protected]). J. J. Cao, H. Shima, and H. Akinaga are with the National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki 305-8568, Japan, and also with CREST, Japan Science and Technology Agency, Tokyo 100075, Japan. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2012.2193658
III. R ESULTS AND D ISCUSSION The transfer characteristics of all the TFTs are shown in Fig. 1(a). The as-prepared TFTs exhibit a poor transfer characteristic with a low on/off current ratio and a high threshold voltage Vth . On the contrast, the TFTs annealed at 300 ◦ C,
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Fig. 1. (a) Transfer characteristics (Id –Vg ) of TFTs annealed at various temperatures. (b) Output characteristics (Id –Vd ) and (c) Id0.5 –−Vg curves of the 300 ◦ C annealed TFTs.
IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 7, JULY 2012
Fig. 3. (a) XRD patterns of the TiOx films. Deconvolution of the FTIR spectra (650 ∼ 1000 cm−1 ) of (b) as-prepared and (c) 300 ◦ C annealed TiOx /SiO2 thin films.
Fig. 2. Dependence of (a) Vth , (b) μ, and (c) on/off ratio on the annealing temperature. (Vth , μ, and on/off ratio are extracted at Vd = 20 V, for asprepared and 100 ◦ C and 200 ◦ C annealed TFTs, and Vd = 10 V for 300 ◦ C, 400 ◦ C, and 500 ◦ C annealed ones.).
400 ◦ C, and 500 ◦ C show low Vth and a high on/off current ratio. Fig. 1(b) and (c) shows the typical drain current Id versus drain-to-source voltage Vd (Id –Vd ) output characteristics and the Id0.5 –Vg curve of the 300 ◦ C annealed TFTs. Electron mobility μwas extracted from the transfer curves using the equation μ = L/(Ci W Vd ) · ∂Id /∂Vg , where Ci is the geometrical capacitance of the SiO2 layer and L and W are the length and the width of the TFT channel, respectively. The dependences of Vth , μ, and on/off ratio on the annealing temperatures are summarized in Fig. 2. The as-prepared and 100 ◦ C annealing TFTs exhibit high Vth values of 65.4 and 64.8 V, indicating the little effect of 100 ◦ C annealing. Vth markedly decreases to 28.85 V after 200 ◦ C annealing, whereas the effect of annealing temperature on Vth becomes little when the annealing temperature is higher than 300 ◦ C. Moreover, it can be seen that both μ and the on/off current ratio first increase with the annealing temperature when it is not higher than 300 ◦ C and then decrease with a further increase in the annealing temperature, as shown in Fig. 2(b) and (c). The maximum μ value and on/off ratio were found in the TFTs annealed at 300 ◦ C, which are 4.02 × 10−2 cm2 V−1 s−1 and 4.08 × 104 at Vd = 10 V and Vg − Vth ≈ 25 V. The results are comparable with the previous works [7]–[12]. The annealing temperature is much lower than that in the previous work in which annealed Ti/TiO2 layer was used as the channel [7]. The crystallinity of all the TiOx layer was investigated by XRD, as shown in Fig. 3(a). No obvious diffraction peak is observed for the as-prepared and 200 ◦ C annealed TiOx thin films, indicating an amorphous nature. Diffraction peaks
Fig. 4. Evolution of the [Si–O–Ti]/[Si–O–Si] peak area ratio with the annealing temperature.
corresponding to the (101) orientation of the anatase phase (JCPDS, No. 21-1272) appear at 300 ◦ C. The peak intensity increases with annealing temperature, indicating an increase in the crystalline nature of the TiOx films above 300 ◦ C. FTIR absorption spectra of the TiOx (20 nm)/SiO2 (150 nm) films were measured. Typical deconvolution of the FTIR spectra (650 ∼ 1000 cm−1 ) for as-prepared and 300 ◦ C annealed samples are shown in Fig. 3(b) and (c). In the as-prepared sample, a band at 910 cm−1 is clearly observed, which is widely accepted as the characteristic vibration due to the formation of Si–O–Ti bonds [14]–[16]. Three bands were deconvolved into Gaussian curves, and the assignments of the vibration are as follows: 1) ∼820 cm−1 for symmetric Si–O–Si stretching vibration [14], [16], [17]; (2) ∼ 860 cm−1 for the vibration of the associated Ti–O–Ti bond [18]; (3) ∼ 910 cm−1 for Si–O–Ti vibration. The influence of the annealing temperature on the Si–O–Ti density was quantized using the peak area ratio [Si–O–Ti]/[Si–O–Si], as shown in Fig. 4. It is clear that Si–O–Ti bonding density quickly decreases after 200 ◦ C annealing, and it changes little with a further increase in the annealing temperature. A few works reported the breaking of the Si–O–Ti bonding after the thermal heating process. In the investigation on Si-TiO2 powders by X-ray photoelectron spectroscopy, the suppression of the Si–O–Ti component in the O1s spectra was demonstrated after thermal treatment [19]. By EELS analysis at the interface of TiOx /SiO2 , the splitting of the Ti 2p spectra is found, which is signed by arrows in
ZHONG et al.: EFFECT OF ANNEALING TEMPERATURE ON TiO2 -BASED TFT PERFORMANCE
Fig. 5. Ti L3,2 EELS profile of the as-prepared and 300 ◦ C annealed TFTs at the TiOx /SiO2 interface. (Inset) Corresponding transmission electron micrographs.
Fig. 5, demonstrating the oxidation of TiOx close to SiO2 . Those results agree well with the decrease in the Si–O–Ti bonding density after annealing (see Fig. 4) and suggest that the reduction of the Si–O–Ti density is attributed to the breaking of the Si–O–Ti bonds. The suppression of the Si–O–Ti bonding contributes to the reduction to the Vth after annealing, since Vth corresponds to the interface trap density. The variation of Vth and Si–O–Ti bonding density on the annealing temperature is quite similar, as shown in Figs. 2(a) and 4. Therefore, the poor transistor characteristics of the as-prepared TFTs is attributed to the extensive high density of the Si–O–Ti bonding at the TiOx /SiO2 interface and the high density of the point defect in the as-prepared amorphous TiOx layer, which may act as deep-level traps [20]. The significant improvement of the interfacial structure after 200 ◦ C annealing contributed to the marked reduction of Vth . It suggests that low-temperature annealing is very effective for suppression Vth in our TFTs. The μ value and the on/off ratio first increase with the increasing of the annealing temperature (≤ 300 ◦ C), and the most obvious increase is seen after 300 ◦ C annealing. With a further increase in the annealing temperature (≥ 300 ◦ C), the μ value and the on/off ratio decrease a little. An increase in μ with increasing annealing temperature is always observed, which is attributed to the improved crystallinity due to the large domain and the fewer grain boundary [12], [21]. The phase transition from amorphous to anatase and the further improvement of TiOx /SiO2 interface contribute to the high TFT performance after 300 ◦ C annealing [12], [21]–[23]. The small degradation of the μ value and the on/off ratio after 400 ◦ C and 500 ◦ C annealing may be attributed to the oxidation of source and drain electrodes, the formation of the oxygen vacancy (VO ) in TiOx acted as trap site for electrons [24], and the increase in the grain boundaries with double Schottky barrier for electrons [24], [25]. R EFERENCES [1] M. Grätzel, “Photoelectrochemical cells,” Nature, vol. 414, no. 6861, pp. 338–344, Nov. 2001. [2] H. Akinaga and H. Shima, “Resistive random access memory (ReRAM) based on metal oxides,” Proc. IEEE, vol. 98, no. 12, pp. 2237–2251, Dec. 2010. [3] N. Zhong, H. Shima, and H. Akinaga, “Switchable Pt/TiO(2−x) /Pt Schottky diodes,” Jpn. J. Appl. Phys., vol. 48, no. 5, pp. 05DF03-1– 05DF03-4, May 2009.
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