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Non-isolated Single Stage PFC Rectifier for Wide-Input Large Step-Down Voltage Applications Abbas A. Fardoun
Esam H. Ismail
Senior Member, IEEE Electrical Engineering Department University of United Arab Emirates P.O. Box 17555, Al-Ain, UAE
[email protected]
Senior Member, IEEE Electrical Engineering Department College of Technological Studies P.O. Box 35007, AL-Shaa’b, Kuwait, 36051
[email protected]
Abstract -- This paper proposes a non-isolated single-stage high power factor rectifier suitable for applications requiring low-voltage and high-current output. The proposed converter integrates two buck-boost converters with a buck converter. As a result, the proposed converter can operate over a wide range of input voltage with extended low output voltage capability, making it suitable for universal input applications. The proposed topology utilizes two synchronized non-floating power switches with low current stress. Additional features are gained when the converter operates in discontinuous conduction mode (DCM). These features include low semiconductors voltage stress, zero-current switch at turn-on, and simple control with a fast well-regulated output voltage and near unity input power factor. Closed form equations of the design constraints for the proposed topology are presented. Simulation and preliminary experimental results are presented to demonstrate the feasibility of the proposed technique. Index Terms—ac-dc converter, fast output regulation, low harmonic distortion, power factor correction, single-stage.
I.
INTRODUCTION
Power supplies with active power factor correction (PFC) techniques are becoming necessary for many types of electronic equipment to meet harmonic regulations and standards, such as the IEC 61000-3-2. While many PFC solution exists, single-stage power factor correction (PFC) integrated topologies have proven to be a good solution as a cost-effective approach for achieving both the function of high PFC and fast output voltage regulation by using one (or one set of synchronized) active switch(es) under a single control loop. Newly emerging power-electronics applications such as computer power supplies, battery chargers, and LED lightening, require extremely step-down voltage conversion ratios. Conventional PFC topologies having step-down conversion capability such as buck–boost, flyback, SEPIC, and Cuk converters suffer from providing low output voltage over a large range of input voltages since it requires an extremely low duty-cycle operation. On the other hand, low duty-cycle operation degrades the power efficiency and influences the performance of both steady and transient states. Extreme duty-cycles cause severe diode reverse-recovery current which will increase the electromagnetic interference (EMI) levels. Moreover, an extreme duty cycle is not desirable since no room is left for control to compensate changes in load or line. This work was supported in part by the United Arab University, Research affairs, under grant contract # 03-04-7-11/09).
Fig. 1. Proposed large step-down DC-DC converter.
In order to overcome the aforementioned and related drawbacks, several single-stage step-down PFC converters have been proposed lately [1-4]. However, these converters are not suitable for very low voltage step-down applications without utilizing a high step-down transformer. In order to extend the duty cycle margin of operation, two non-isolated schemes based on integrating buck-boost PFC cell with a dc-dc buck converter have been proposed in [5-6]. These converters have relatively high step-down voltage ratio and exhibit high power factor with low THD in the line current. Also, they address the problem of high voltage at the energy storage capacitor presented in [7-9]. In this paper, a new non-isolated dc-dc converter with extreme step-down voltage gain is proposed. The proposed converter, shown in Fig. 1, is derived by integrating two buck-boost switching cells with a conventional buck cell. The front end buck-boost cell was selected due to its high power factor capability when operating in discontinuous conduction mode. As a result, the proposed converter can operate over a wide range of input voltage with extended low output voltage capability, making it suitable for universal input applications. Moreover, the proposed converter has two distinct advantages over the one presented in [5-6], namely it provides extended duty-cycle margin of operation and a non-inverted output voltage polarity. It shall also be mentioned that the capacitor voltage is well below the input voltage. The gating signal of both switches is the same and can be non-floating signal. The principle of operation and comparisons with the topologies presented in [5-6] will be addressed. Simulation and experimental results are also presented in order to demonstrate the effectiveness of the proposed scheme. Parameters design constraints which guarantee unity power factor and zero turn-on switching with minimum switching
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PEDS2009 and capacitor stresses are also presented. II.
PROPOSED LARGE STEP-DOWN DC-DC CONVERTER
Please use automatic hyphenation and check your spelling. Additionally, be sure your sentences are complete and that there is continuity within your paragraphs. Check the numbering of your graphics (figures and tables) and make sure that all appropriate references are included. Fig. 1 shows the proposed large step-down DC-DC converter. The converter consists of two buck-boost cells cascaded with a buck cell to achieve wide input-output voltage ranges. The proposed converter of Fig. 1 utilizes two non-floating active switches Q1 and Q2; however, the two switches can be driven with the same PWM signal, which significantly simplifies the implementation of the control circuit. Note that the switch Q2 can be implemented by either the choice of NMOS or PMOS which allows using a low side driver. To facilitate the explanation of the circuit operation, consider the DC-DC converter of Fig. 1 is operating in the continuous conduction mode (CCM). In this case, the circuit operation during one switching period Ts can be divided into two operating stages which are briefly described in the following. Stage 1 [0 t DTs]: from Fig. 1, when Q1 and Q2 are turned-on simultaneously, D2 becomes forward biased by the inductor current iL2. Accordingly, diodes D1, D3, and D4 are reversed biased by the voltages Vg+VC1, VC1+VC2, and VC2, respectively. This interval ends when the switches Q1 and Q2 are turned-off initiating the next subinterval. Stage 2 [DTs t Ts]: In this stage, diodes D1, D3, and D4 are forward biased providing a path for the three inductor currents iL1, iL2 and iL3. Diode D2 is reversed biased by input voltage Vg. In this stage, capacitors C1 and C2 are effectively in series with L1 and L2, respectively. Hence, they are being charged by the energy stored in L1 and L2. Based on the volt-second balance of the three inductors, the voltage conversion ratio M of the proposed converter is given by M
Vo D3 V m ( 1 D ) 2
analyzed for DCM operation. Assuming the input ac voltage is ideal source, converter components are ideal (nolosses), switching frequency is well higher than the line frequency, capacitors C1, C2, and C3 are storage capacitors (large), inductors L1, L2, and L3 operate in DCM mode and the phase shift introduced by the input filter is negligible. By allowing the three switching cells to operate in the DCM, inherent PFC and fast well-regulated output voltage can be achieved simultaneously using a single-loop voltage feedback controller. In this case, the circuit operation during one switching period TS can be divided into four operating stages which are briefly described below. Stage 1 [D1TS] (Fig. 4(a)): At the start of this stage, it is assumed the currents in inductors L1, L2, and L3 are at zero level. At the beginning of this stage, switches Q1 and Q2 are turned on causing D2 to turn on. Hence, inductors L1, L2, and L3 are charged linearly. Since switches Q1 and Q2 are turned on with inductors currents at zero level, zero-current turn-on switching is achieved. Stage 1 is ended by turning off Q1 and Q2. Stage 2 [D2TS] (Fig. 4(b)): Turning off Q1 and Q2 causes diodes D1, D3, and D4 are forward biased providing a path for the three inductor currents iL1, iL2 and iL3, respectively. Diode D2 is reversed biased by input voltage vi = |vac|. In this stage, capacitors C1 and C2 are effectively in series with L1 and L2, respectively. Hence, they are being charged by the energy stored in L1 and L2. This stage ends when inductor L1 is completely discharged and current goes to zero. Hence, diode D1 is reversed-biased. The diode DL prevents the current iL1 from becoming negative. Stage 3 [D3TS] (Fig. 4(c)): In this stage, the two inductor currents iL2 and iL3 discharges through diode D3 and D4, respectively. This interval ends when iL2 reaches zero which forces diode D3 to be reverse-biased.
(1)
where D is the switch duty-cycle. For the sake of comparison, Fig. 2 illustrates the relationship between M and D of the proposed converter as well as for other previously proposed large step-down non-isolated topologies. It is evident from Fig. 2 that the proposed converter operate at a higher duty ratio compared to other large step-down converters provided that M is the same for both converters. Accordingly, the range of the duty-cycle will be also extended when the converter operates in the discontinuous conduction mode (DCM).
Fig. 2. Ideal voltage conversion ratio M as a function of duty-cycle D.
III. PROPOSED SINGLE-STAGE PFC CONVERTER: PRINCIPLE OF OPERATION (DCM MODE) Fig. 3 illustrates the configuration of the proposed converter when operating from an ac source. The front-end buck-boost cell has good inherent PFC capability when operating in DCM. Hence, the converter in Fig. 3 will be
295
Fig. 3. Proposed single-stage PFC rectifier.
PEDS2009 DCM in the sequence shown in Fig. 5, then iL1, iL2, and iL3 are discharged to zero before turning-on the switches. The inductors DCM sequence (L1 followed by L2 and finally L3) shown in Fig. 5 is required to minimize rms current in Co & for simpler control. Note that the additional diode DL in Fig.3 prevents the inductor current iL1 from going negative during switch off-time; hence, the rectified input current iin will naturally follow the rectified input voltage. Fig. 5 shows typical waveforms of the proposed rectifier for DCM operation. A.
Conditions for DCM Since PFC is possible when L1 converter is operating in DCM, conditions for this mode are analyzed. Duty cycles in the off-time, namely, D2, D3, and D4 will be expressed as function of on-time duty cycle D1 and other converter parameters. This analysis is derived by applying voltagesecond to inductors L1, L2, and L3. The following equations are obtained:
Fig. 4. Topological stages for the converter of Fig. 3 in DCM.
D 2 D1
vi VC1
D 2 D 3 D1
(2) VC1 VC 2
(3)
D 2 D 3 D 4 D1
V C 2 V o Vo
(4)
For PFC, only L1 must be in DCM mode. However, inductors L2 and L3 must be in DCM mode to ensure zerocurrent turn-on switching on switches Q1 and Q2; thus the following equations must be satisfied. (5) D 2 1 D1 D 2 D 3 1 D1
(6)
D 2 D 3 D 4 1 D1
(7)
From (2)-(7), the following boundaries can be deduced, v i ( 1 D1 ) 2 Vo D13 VC 2
Fig. 5. Typical DCM waveforms of the proposed rectifier of Fig. 3.
Stage 4 [D4TS] (Fig. 4(d)): In this stage, inductor current iL3 continues to discharge through D4 until it becomes zero forcing diode D4 to be reversed biased. Besides zero-current switch turn-on and reduced diode reverse recovery problems, DCM operation of the three inductors tends to reduce the voltage stress on the energy storage capacitors C1 and C2; hence, on the active switches Q1 and Q2 which is independent of the load current variations. This is a very desirable feature especially for universal input voltage applications. IV. STEADY STATE ANALYSIS Referring to Fig. 3, when the three inductors operate in
(8)
Vo D1
(9)
Note that for step-down conversion, (8) can always be satisfied over the entire ac line input voltage. To have L3 operating in boundary conduction mode (BCM), then, D1+D2+D3+D4 = 1, hence; Vo = D1VC2. DC Capacitor Voltages VC1 & VC2 In this section, the capacitor voltages VC1 and Vc2 are addressed because they determine the stresses for Q1, Q2, and diodes D1 through D4. The voltages across C1 and C2 are determined by applying charge balance on C1 and C2 across half line cycle (TL/2). The average capacitor current over TL/2 can be expressed as,
B.
i Cn ( t )
TL / 2
2 TL
TL / 2
0
i Cn ( t )
TS
dt , n 1, 2
(10)
The averaged capacitor currents over a switching cycle can be expressed as follows,
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PEDS2009
iC 2 ( t )
1 ( D1 I L 2 _ pk D 2 i L 1 _ pk ( t )) 2
TS
TS
1 (( D 2 D 3 ) I L 2 _ pk D1 I L 3 _ pk ) 2
(11)
250
Capacitor voltages [Volt]
i C 1( t )
(12)
At steady-state, (10) must equal zero. Evaluating (10) for both (11) and (12) based on capacitor charge balance, and using (2), one can solve for VC1 as shown below, V C 1 V m
VC 2
L2 2 L1
(13)
2L3 Vo 1 1 2 M 2 L1
(14)
where M=Vo/Vm and Vm is the peak line voltage. Note that the dependence of VC1 on L2 and L1 already has been discussed in previous publications [9-11] and the above results are in line with what has been published. However, it shall be noted that even though the proposed converter consists of three cascaded cells; VC1 is only dependent on L1 and L2 while it is independent of L3. On the other hand, (14) shows that the voltage across VC2 is not a function of L2. Fig. 6 shows the variation of VC1 and VC2 as a function of the line voltage vac, with the ratio L1/L2 and L1/L3 as a parameter. As can be seen from (13) and (14) the voltage stresses can be reduced by increasing the value of L1. However, L1 must stay within limits to stay in DCM. The upper boundary for the inductors ratio limit can be derived from (2)-(7) and (13)-(14) as follows, L3 2 L1 L 2
M
(15)
Equation (15) allows the designer to obtain the upper limit of the gain as function of the inductors of the converter to stay in DCM mode. Moreover, when L3 operates at BCM, one can solve for the duty cycle D1 using (9) and (14) as follows, D1
Vo VC 2
2 L3 M L1 1 1 2 L3 M L1 2
Voltage Conversion Ratio The voltage conversion ratio M can be obtained by applying power balance principle. The input power can be expressed as, TL / 2
2 TL
TL / 2
0
v in i in ( t ) dt TS
(17)
The average input current over one switching cycle can be approximated from Fig. 5. By applying input-output power balance, the conversion ratio M can be obtained as
VC2
100 50 0
120 150 180 210 240 270 300
vac [Vrms] Fig. 6. Energy-storage capacitor voltages as function of input voltage for an output voltage Vo of 12V.
M
Vo Vm
D1 2K
(18)
where the dimensionless parameter K is defined by, K
2 L1 RL TS
(19)
D.
Inductances L1, L2, and L3 To ensure that the power stages of the proposed converter are operated in DCM, the inductor currents iL1, iL2, and iL3 must be fully discharged to zero in every switching period. The critical value of K (Kcrit) required for L1 to be in DCM is found by rearranging (8) and (18) which gives, K crit
4
1 1 D 2 D
(20)
For values of K ≤ Kcrit, then L1 is operating in DCM; otherwise, L1 will enter the CCM region. The critical value of L1 (L1,crit) required for DCM operation occurs at maximum output power (RL,min) and at the peak of the lowline voltage (Vm,min). Using (18), (19), and (20) gives L1,crit as: L1 ,crit
R T s 1 B 1 / 3 1/ 3 1/ 3 L ,min K 0 1 1 K 0 4 3 2
2
(21)
where K0
C.
Pin ( t )
VC1
150
90
(16)
Equation 14 is independent of load current; however, it is still function of gain M which means that either D1 or the switching frequency must change as load varies. Note that if switching frequency is kept constant, variation of D1 is limited by the boundary conditions discussed earlier.
L1/L2 = 1.4, L1/L3 = 5 L1/L2 = 1.8, L1/L3 = 10
200
B
1
6 M max 4 A3 , A 27 B 3 M max
2 2 M max 18 M max 27 , and 2 27 M max
(22) M max
Vo V m ,min
For values of L1>L1,crit, the converter enters the CCM region where (18) is no longer valid. In CCM, there are only two operating stages per switching cycle, Fig. 4(a) and 4(b). The voltage conversion ratio in CCM can be expressed by M = 2D3/[(1-D)2], which can be derived by equating the average of C1 and C2 currents during a halfcycle to zero and applying the power balance between the input-output ports. However, operating L1 in CCM region results in a more distorted input line current and a lower input power factor than in DCM region. The best choice for the value of L1 is to be close to L1,crit since this will reduce the ripple value of the input current, iin. The DCM
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L3 ,crit
1 R L ,min T s 1 M max 2
2K
2
equations for parameter selections as well as design constraints to ensure PFC and low component stresses for the converter topology have been presented. The converter topology has been verified via simulation and experimental results. 0.4
Voltage conversion ratio, M
characteristic is plotted in Fig. 7 for several values of K. Note that the CCM/DCM boundary line in Fig. 7 is valid for t = /2, i.e. when vi = Vm which gives the minimum required value of Kcrit. Similarly, the condition for the inductor L3 to operate in DCM occurs when the average output current Ts IL3,pk/2, Fig. 5. Thus, the minimum value of L3 (L3,crit) can be found as, (23)
Once the value of inductors L1 and L3 are properly selected, then the value of inductor L2 must be appropriately selected such that iL2 falls to zero after iL1 and before iL3, Fig 5. One can show, from (2)-(4), (13), and (14) that the allowable range of L2 is:
L1 M 1 1
2 L3 L1 M 2
L32 L2 2 L1 M 2
DCM
CCM
0.3 K=1 0.2
K=2 K=6
0.1
CCM/DCM boundary at t=/2
0 0
(24)
0.1
0.2
0.3 0.4 Duty cycle, D
0.5
0.6
Fig. 7. Conversion ratio M as function of duty cycle D1 for several values of K. TABLE I: SEMICONDUCTORS VOLTAGE STRESS.
E.
Semiconductor stresses Table I shows the voltage stresses across the semiconductor devices in terms of peak line voltage Vm and capacitor voltages VC1 and VC2. The semiconductor rms current stresses are shown in Fig. 8. These curves are plotted for Pout = 75 W, Vo = 12 V, fs = 50 kHz, L1 = L1crit, L2 = L2crit, and L3 = L3crit. It is clear from Fig. 8 that the current stress in the semiconductor devices (except for the output diode D4) tends to decrease as the input ac-line voltage increases.
A single-stage high step-down non-isolated PFC converter topology is proposed. The proposed topology has a non-inverted high step down capability which makes it suitable for many applications such as LED and computer applications. The proposed topology requires single nonfloating gating signal to control the output voltage. Design
298
VC1+Vm
Q2 and D4
VC2
D2
Vm
D3
VC1+VC2
rms currents [Arms]
6 IQ2rms
4 IQ1rms
2
ID3rms ID1rmsID2rms
0 90
120 150 180 210 240 270 300 330 vac [Vrms]
Fig. 8. Semiconductors rms current stresses. 2.0
15
0
[Ampere]
vac/100
1.0
iac
-1.0
[Volt]
[Volt]
-2.0 955 960 965 970 975 980 time [msec] (a)
[Volt]
VI. CONCLUSION
Q1 and D1
ID4rms
SIMULATION & MEASUREMENTS
To verify the operation of the proposed converter, the circuit of Fig. 3 has been simulated for the following input and output data specifications: vac = 110 Vrms, Vo = 12 V, Pout = 75 W, and fs = 50 kHz. The simulated waveforms are shown in Fig. 9, which correctly demonstrates the DCM operating mode. Moreover, it is clear from Fig. 9(c) that the output voltage Vo has insignificant low frequency ripple which can be further reduced by simply regulating the output voltage. A low-power (30-W) laboratory prototype is constructed and implemented for 50Vrms/12Vdc. The operating switching frequency is set to 50 kHz. The experimental waveforms at full load are depicted in Fig. 10. It is evident from Fig. 10(a) that the input line current (iac) follows the input line voltage (vac). The waveforms of the output voltage and the voltages on the energy storage capacitors VC1 and VC2 are shown in Fig. 10(b). It can be observed form Fig. 10(b) that the output voltage is almost pure DC with extremely low frequency (twice the line frequency) voltage ripples.
Voltage Stress
8
[Volt], [Ampere]
V.
Component
985
(c)
iL2
5
iL1
0 -5 963 (b)
86 84 82 41 40.7 12.5 12 11.5 955
iL3
10
963.02 963.04 time [msec]
963.06
VC1 VC2 Vo 960
965 970 975 time [msec]
980
985
Fig. 9. Simulated waveforms for the proposed rectifier of Fig. 3. (L1 = 150 H, L2 = 80 H, and L3 = 13.3 H)
PEDS2009
(a)
(b) Fig. 10. Experimental waveforms for the proposed converter of Fig. 2. (L1 = L2 = 120 H, and L3 = 30 H)
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