Regulated Switched-Capacitor Doubler With ... - IEEE Xplore

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation Feng Su, Student Member, IEEE, Wing-Hung Ki, Member, IEEE, and Chi-Ying Tsui, Member, IEEE

Abstract—A dual-branch 1.8 V to 3.3 V regulated switched-capacitor voltage doubler with an embedded low dropout regulator is presented. For the power stage, the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions. For the regulator, the two branches operate in an interleaving fashion to achieve continuous output regulation with small output ripple voltage. Dual-loop feedback capacitor multiplier is adopted for loop compensation and a P-switch super source follower with high current sinking capability is inserted to drive switching capacitive load, and push the pole at the gate of the output power transistor to high frequency for better stability. The regulated doubler has been fabricated in a 0.35 m CMOS process. It operates at a switching frequency of 500 kHz with an output capacitor of 2 F, and the maximum output voltage ripple is only 10 mV for a load current that ranges from 10 mA to 180 mA. The load regulation is 0.0043%/mA, and the load transient is 7.5 s for a load change of 160 mA to 10 mA, and 25 s for a load change of 10 mA to 160 mA. Index Terms—Charge pump, interleaving, low dropout regulator, reversion current, short-circuit current, switched-capacitor DC-DC converter.

I. INTRODUCTION HE market of personal consumer electronics keeps on expanding for the foreseeable future. The batteries for these applications such as NiMH batteries, fuel cells and button batteries usually give a low supply voltage of 1.8 V or even lower. However, many analog and mixed-signal ICs with high precision and high dynamic range still require a higher and regulated supply voltage of around 3 V. For step-up conversion, switchedcapacitor (SC) power converters, or charge pumps, are attractive candidates as they do not need bulky inductors; and if the capacitor voltages of the charging phase and the pumping (discharging) phase are kept small, they would cause less EMI problems compared to switch mode power converters. For voltage regulation, a regulated switched-capacitor voltage doubler that could deliver a few hundred mA is needed, and examples include [1]–[4]. A regulated SC power converter consists of two major functional blocks (Fig. 1). The first is the switched-capacitor power

T

Manuscript received September 03, 2008; revised November 12, 2008. Current version published March 25, 2009. This work was supported in part by the Hong Kong Research Grants Council under CERG HKUST 614506. The authors are with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong SAR (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/JSSC.2009.2014727

Fig. 1. Generic architecture of switched-capacitor voltage regulator.

stage, consisting of power switches and flying capacitors that boost the input supply voltage to a higher voltage. A good power stage should provide a high-efficiency DC-DC conversion and at the same time eliminate short-circuit and reversion current and minimize switching noise. The second is the feedback controller and the reference that compares the scaled output voltage , and generates a control signal to control the voltage on-resistance of power transistors or the switching frequency of the SC power stage to adjust the output voltage . A good feedback controller should have good line and load regulation and have fast response for line and load transient. In this research, we explore high performance design techniques for regulated charge pumps with low switching noise and output voltage ripple [4]. Section II analyzes problems of the conventional 2-phase cross-coupled doubler and proposes a phase-delayed gate drive scheme to eliminate both short-circuit and reversion currents during phase transitions. A 4-phase interleaving scheme is also proposed to achieve continuous output regulation and reduce the output voltage ripple. Section III discusses prior regulated doublers and proposes a switching low dropout regulator with a P-switch super source follower for driving the pMOS pass transistors. Section IV discusses the design details of the proposed SC regulated doubler. Section V presents experimental results and compares the design performance with prior works. A brief conclusion is drawn in Section IV.

0018-9200/$25.00 © 2009 IEEE

SU et al.: REGULATED SWITCHED-CAPACITOR DOUBLER WITH INTERLEAVING CONTROL FOR CONTINUOUS OUTPUT REGULATION

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Fig. 2. Conventional dual-branch SC voltage doubler.

II. SWITCHING NOISE AND LEAKAGE AND THEIR REDUCTION A. Switching Noise and Leakage Fig. 2(a) shows a dual-branch voltage doubler. With the same total capacitance, the dual-branch doubler charges the output capacitor in both phases, achieving a lower output ripple voltage than the single-branch doubler and is thus more efficient [5]. The doubler consists of two symmetrical branches that operate in complementary phases driven by a pair of non-overlapping phases and [Fig. 2(b)]. When , is charged to , and (previously charged to ) steps on top of and transfers charge to the output capacitor , and the output is then approximately . When , the opvoltage and interchanges. Switching noises are due eration of to transient currents rushing in and out of the nodes, causing voltage ripple and ringing. Current transients of the supply input current and the output charging current are the most inimportant among other current transients. Transients of troduces noise to other blocks sharing the same power line, and transients of introduces ripples and glitches at the output filtering capacitor, injecting noise to all loading blocks. The transients are due to charge redistribution current, short-circuit current and reversion current. They are discussed below. Charge Redistribution Current: Charge redistribution occurs when two or more capacitors are connected together. If the switches are ideal, the charge redistribution currents are delta functions, giving instantaneous changes in voltage levels. In practice, finite switch resistances limit the peak of the currents

Fig. 3. Cross-coupled voltage doubler.

and the currents assume RC exponential charging and discharging waveforms. If the duration for charge transfer period [“on” period of and in Fig. 2(b)] is much longer than the RC time constants of the capacitors and switch resistances, the charge redistribution current goes to zero at the end of and the charge transfer is complete. However, if is too short, the charge redistribution current shows up as residual conduction current at the end of , and the charge transfer is incomplete. In such a case, besides charge redistribution loss, conduction loss has to be considered as well. Fig. 2(b) shows and of the doubler operating in typical waveforms of the steady state. During the dead-time periods, all 8 power

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Fig. 4. Charging current to the load of (a) cross-coupled doubler; (b) doubler with phase-delayed control; and (c) 4-phase interleaving doubler with phase-delayed control.

transistors are turned off, and and are zero. At the rising instants of and , both and have large jumps, reaching their respective peak currents, and the larger the load, the larger the voltage differences between the capacitor voltages, and the larger the jump amplitudes. Switching noise due to charge redistribution cannot be avoided but can be reduced by slowing down the gate-drives of the power transistors [6], thus achieving larger initial switch resistances to slow down the and , especially at their rising edges. current transients of Short-Circuit and Reversion Currents: The 2-phase doubler of Fig. 2 is usually implemented by cross-driving the gates of with and the pair with , the pair as shown in Fig. 3 [7]. We labeled it the cross-coupled doubler (XC-doubler). The major problems are short-circuit and reversion currents. Let us consider when is increasing from to and is decreasing from to , such that and are initially on, and and are initially off. Four cases can be identified [8], [9]. (1) If there is time duration when both and are higher than , then both and are turned on, resulting and back to through in reversion current from and respectively. This case is denoted as OV_H (overlap and are high). (2) If there is time duration when both lower than , then both and are turned on, resulting in reversion current from back and through and respectively. This case is to , denoted as OV_L (overlap low). (3) If then both OV_H and OV_L occur in the same transition, and in addition to the above reversion currents, there is also short-circuit (shoot-through) current from back to , and the case , then neiis denoted as OV_HL. (4) If ther OV_H nor OV_L could occur, and the case is referred as OV_NHL. However, is larger than , and we is increasing very fast, with medium could further consider if . If increases very fast, speed, and very slow relative to then is turned on fast and is turned off fast. However, remains on, and hence there will be reversion currents from and back to . In fact, we could verify that there both are reversion currents for the other two cases. Hence, reversion currents are unavoidable for cross-coupled doubler. The ampli-

and tude of these transient currents could even be larger than , compromising the power conversion efficiency of the douof the XC-doubler with bler. Fig. 4(a) shows the simulated a load current of 100 mA, and the reversion current glitches are as high as 600 mA. To reduce both short-circuit and reversion and has to be short, or currents, the transition duration of the gate-drives of the power transistors should be fast, which is contrary to reducing glitches arose from charge redistribution. B. Phase Delay Control To eliminate all the switching leakage currents, the break-before-make mechanism should be fulfilled, which could be summarized in three conditions. 1) For each of the inverter pair , , and , the on-period of power transistors should be non-overlapping to avoid short-circuit current. is cross-coupled, and 2) If the nMOS pair should be OV_L. If the pMOS pair is crossand should be OV_H. coupled, should not be turned on before falls 3) , and should not be turned on before below rises above . To observe all conditions, careful check on each power transistor during every transition is necessary, which is quite a tedious job. To eliminate all switching leakage currents, we observe that the switches should obey two rules. (1) Each power switch should be triggered by its phase signal, where phase signals and are non-overlapping. (2) Each flying capacitor has a charging phase and a pumping phase [Fig. 5(a)]. To avoid leakage current during ’s charging (pumping) transient, the turning-on of should be delayed after the turning-on . As shown in Fig. 5, ’s ( ’s) phase signal is of instead of . The control scheme is denoted as denoted as Phase Delay Control (PDC). Table I summarizes the relationship between each switch and its MOS implementation, and the boldfaced options are used in our proposed voltage doubler. Note that to implement the same switch, the phase of using pMOS is complementary to that of using NMOS. Moreover, the “phase” column in Table I only indicates when the gate should


Fig. 5. Short-circuit and reversion currents elimination: (a) schematic; (b) clock phases.

TABLE I IMPLEMENTATION OF CMOS SWITCHES OF DOUBLER

be high. The actual high voltage is in the “swing” column that could completely turn on and off the MOS transistor under of the doubler discussion. Fig. 4(b) shows the simulated with PDC, and the reversion current is almost eliminated. The remaining glitches are due to current injection from switching to through parasitical capacitive paths. nodes

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are added to slow down the gate-drives of the power transistors. However, the reversion current that flows from the output capacitor back to the flying capacitors during the switching and are not eliminated, causing switching instants of of [6] is between that in Fig. 4(a) glitches. The waveform of and Fig. 4(b). A multi-branch architecture with interleaving is an effective way to reduce switching glitches [10], [11]. In [11], a doubler with two dual-branches that operate with 90 phase shift forming a 4-branch interleaving voltage doubler is suggested. However, the number of off-chip flying capacitors is doubled that increases the production cost. Here, we propose a 4-phase clock that drives two identical branches in an interleaving fashion, using only two flying capacitors, as shown in Fig. 6(a). The 8 power switches are controlled by a 4-phase , where and are clock the two principal non-overlapping phases for Branch A and and of Branch B, respectively, serving the function of Fig. 2. For Branch A, and are also non-overlapping phases designed to prevent short-circuit and reversion currents, and for Branch B. However, and and so do overlap for a short interleaving duration of . As such, one clock period is divided into 8 time sessions [Fig. 6(c)]. In and , and State 1, charges up while charges up . In State 2, and is disconnected from . In State 3, such that is in parallel with , and . This is one of the two interleaving sesboth charges up and , sions. In State 4, is disconnected from . For State 5 to State 8, the and roles of and are interchanged. Clearly, in any of the sessions, at least one flying capacitor is delivering current to the output. With this interleaving control scheme, both the and output charging current will not reinput current turn to zero (at heavy loads) and their ripples are accordingly reduced compared to the conventional cross-coupled doubler with a 2-phase clock. Fig. 4(c) shows the simulated of the 4-phase interleaving voltage doubler with PDC gate drives. assumes very small current ripples all the time and Clearly, the switching glitches at the output due to is greatly reduced.

C. 4-Phase Interleaving Voltage Doubler With the proposed phase delay control, the doubler operates with no short-circuit and reversion currents. The output charging is then quite close to the ideal one shown in Fig. 2(b). current However, in examining Fig. 2(a) in details, we notice that one clock period is divided into 4 time sessions as shown in Fig. 2(c). During the dead-times , all 8 power transistors are turned off, returns to zero. At the rising edges of and , and jumps to the peak current level limited by the switch resistance, and the larger the load current, the larger the amplitude. Moreover, the transient of , , introduces voltage glitches [6]. Ringing may occur due to parasitic inductors of the bond wires and/or the routing copper of the PCB. Especially for heavy loads, the switching noise due to dominates. Methods are suggested to suppress the switching noise at . In [6], two passive poly resistors the output due to

III. REGULATED VOLTAGE DOUBLER A switched-capacitor power converter has high efficiency when the output voltage is restricted to N or N/K times of the input voltage (at no load), where N and K are integers. For the and . To regulate the output, voltage doubler, and refer to Fig. 2(a). The switch pairs are usually nMOS transistors, while and are pMOS transistors. PWM (duty ratio) control was suggested to instead of in [12] to charge during its charging phase such that . In is used and and are [12], the switch pair referred as quasi-switches. Clearly, the pair could be controlled instead. Both schemes are charging phase regulation indirectly. In [1], pumping phase regulation that control

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Fig. 6. Dual-branch SC voltage doubler with 4-phase interleaving driving scheme.

was suggested using the pair , and the regulated doubler was referred as switching low dropout regulator (SLDR). , serves as the During the pumping phase of directly pass transistor of the LDR, and the LDR regulates was used and and instantaneously. In [2], the pair the scheme was labeled pseudo-continuous output regulation. However, for both [1] and [2], all the power transistors are turned off during dead-time sessions. Both and return to zero and the regulated doubler loses regulation. The output capacitor is then solely drained by the load, and the larger the load, the larger the voltage drop, and thus the larger the output ripple voltage. Moreover, the error amplifier of the controller drives the gates of the pass transistors alternately, and this switched-capacitive load behaves capacitive at low frequency and resistive at high frequency, causing problem in modeling the related pole location. In order to ease the design of the compensator, a high performance buffer (source follower) is needed in cascade to the error amplifier, and put the pole to high frequency that will not affect loop stability. Our design is based on the switching LDR control as shown in Fig. 7. To realize continuous output regulation, the power stage is driven by the 4-phase interleaving scheme as discussed

Fig. 7. Architecture of proposed regulated SC doubler.


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Fig. 8. 4-phase interleaving clock generator: (a) schematic; (b) clock phases.

in Section II-C. Dual-loop feedback with capacitor multiplier is adopted for loop compensation [13] and a new P-switch super source follower with excellent current sinking capability is inserted into the loop to drive the switched capacitive load. Design details are addressed in the following section. IV. IMPLEMENTATION OF REGULATED DOUBLER WITH INTERLEAVING CONTROL A. Architecture of Interleaving Regulated SC Doubler The interleaving scheme makes continuous output regulation and act as pass transistors, straightforward. In Fig. 7, while other power transistors act as switches. Each power tran, for example) is driven by an individual gate driver sistor ( (gate driver A1, or GD A1 in Fig. 7, corresponds to in Fig. 6) which synchronizes with the proper “on” and “off” status of the power transistor. Proper voltage swings of the gate drives are oband tained by using level-shifters. Two pMOS transistors are used to charge a small on-chip capacitor to . The size of and is quite small as the power consumption of the controller is around 140 W. The feedback with the refcontroller compares the scaled output voltage erence voltage , generating the control voltage to drive and . It operates as follow: when power transistors , power transistors and are turned on, placing the flying capacitor on top of to deliver current to the output. is fully turned on, is controlled by and the output but the gate of is regulated to . voltage B. Four-Phase Clock Generator Fig. 8(a) and (b) shows the schematic and timing diagram of the 4-phase clock generator, respectively. The clock generator

Fig. 9. CMOS implementation of (a) gate driver A1; (b) gate driver A2.

is formed by three non-overlapping clock generation blocks. with non-overlapping period . Block A generates The phases and are fed into Block B and Block C, respecand tively, to generate the other two pairs with non-overlapping period . The interleaving period between and is . C. Gate Driver A1 (B1) and A2 (B2) The CMOS implementation of gate drivers A1 and A2 are shown in Fig. 9. In gate driver A1, falling edge delay (FED) and rising edge delay (RED) with relative sizes of transistors as drawn are used to generate a short non-overlapping period beand , eliminating the short-circuit current in the tween and . This non-overlapgate buffer composed of and ping period is much shorter than the one between in the doubler. The level-shifter is used to boost the swing to in the gate buffer. The level shifter completely turn off , taking advantage of the is powered by the switching node interleaving scheme. Gate driver A2 is similar to A1. Due to the large swing of , complementary switches are inserted beand and accordingly one more level-shifter is tween needed to turn on and off the switches. Gate drivers B1 and B2 can be constructed in a similar fashion. D. Feedback Controller Fig. 10 shows the implementation of the feedback controller. The regulation loop uses dual-loop feedback compensation with capacitor multiplier [13]. With

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Fig. 10. Dual-loop feedback controller with super source follower.

( apply KCL to

, and

, ) and , the loop gain is given by

,

(1) is the dc loop gain, where is the feedback factor, is the LHP zero, and the two LHP poles are and . Note that is the output resistance , and this notation applies to other output resislooking into tance discussed below. To achieve 60 degree phase margin, we set and get (2) The pMOS power transistors are driven by a buffer that has a high current sinking capability. High current sourcing capability as discussed in [1] and [3] is not needed, because when is off, its gate terminal is pulled to the high output . In the next phase when it is to be turned on, the voltage is connected to that tends to pull gate of up through charge sharing. The buffer then sinks large current to drive to the steady state value. The worst case for the buffer is when the doubler is supplying full load curto correct rent. The buffer should have low output impedance for pushing the pole at the gate of the regulation power transistor to high frequency. The buffer would be too slow if it is a pMOS source follower. To enhance the buffer down-slew rate and attenuate the buffer output impendence, a super source follower with shunt-shunt feedback can be used [14]. Our proposed P-switch super source follower employing shunt-shunt feedback is shown in Fig. 10. is assisted by the source follower The source follower to achieve even lower output impedance at . The swing of the gate of is large. The current mirror formed by and can be used to adjust the loop gain, which is given by (3) where the output resistance at dominant pole is located at

, and is

is . The .

Fig. 11. Micrograph of regulated SC doubler with interleaving control.

The

non-dominant

pole is located at , and is , where is the parasitic capacitor . To ensure stability, we should have , at . and the condition leads to Meanwhile, to guarantee that the pole locating at to have little effect on the stability of the regulator loop, we should , which leads to . have V. EXPERIMENTAL RESULTS

The proposed regulated doubler was fabricated in a 0.35 m CMOS process with an area of 1.15 mm including the pads. The chip micrograph is shown in Fig. 11. Fig. 12 shows the and switching nodes and in the steady output voltage state. The output ripple voltage is 5 mV and 10 mV for a load current of 10 mA and 180 mA, respectively. The interleaving time between and is approximately 10 ns. Fig. 13 shows the load transient response with a load step of 150 mA. The load transient is 7.5 s for a load change of 160 mA to 10 mA, and 25 s for a load change of 10 mA to 160 mA. Load regulation is measured to be 0.0043%/mA, and line regulation is 0.32%/V. The efficiency at 180 mA is 91.5%, and is quite close . to the theoretically maximum limit of 91.667%


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TABLE II PERFORMANCE SUMMARY OF EXPERIMENTAL RESULTS

Fig. 12.

V ,V

and V in the steady state.

REFERENCES

Fig. 13. Load transient response.

Table II summarizes the performance of the interleaving regulated doubler. VI. CONCLUSION In this research, we demonstrated a switched-capacitor regulated doubler with a dual-branch interleaving scheme for continuous output regulation. Phase-delayed control applicable to all switched-capacitor power converters is proposed to eliminate both short-circuit and reversion currents for high efficiency. Furthermore, the two branches operate in an interleaving fashion using a 4-phase driving scheme to achieve small switching glitches, which is crucial in realizing authentic continuous output regulation. The compensation technique of dual-loop feedback with capacitor multiplier makes the system stable for a wide loading range with small compensation capacitors. The proposed P-switch super source follower attains lower output impedance compared to conventional designs. All proposed ideas were implemented in an integrated circuit prototype, and verified by experimental results.

[1] W. Chen, W. H. Ki, P. Mok, and M. S. Chan, “Switched-capacitor power converters with integrated low dropout regulators,” in Proc. IEEE ISCAS, Sydney, Australia, May 2001, pp. III-293–III-296. [2] H. Lee and P. Mok, “An SC voltage doubler with pseudo-continuous output regulation using a three-stage switchable opamp,” IEEE J. SolidState Circuits, vol. 42, no. 6, pp. 1216–1229, Jun. 2007. [3] Y. H. Lam, W. H. Ki, and C. Y. Tsui, “An integrated 1.8 V to 3.3 V regulated voltage doubler using active diodes and dual-loop voltage follower for switch-capacitive load,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2006, pp. 85–86. [4] F. Su, W. H. Ki, and C. Y. Tsui, “A switched-capacitor regulated doubler with novel area-efficient continuous output regulation using a dualbranch interleaving control scheme,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2008, pp. 136–137. [5] W. H. Ki, F. Su, and C. Y. Tsui, “Charge redistribution loss consideration in optimal charge pump design,” in Proc. IEEE ISCAS, Kobe, Japan, May 2005, pp. 1895–1898. [6] H. Lee and P. Mok, “Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1136–1146, May 2005. [7] P. Favrat, P. Deval, and M. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. of Solid-State Circuits, vol. 33, no. 3, pp. 410–416, Mar. 1998. [8] C. Falconi, G. Savone, and A. D’Amico, “High light-load efficiency charge pumps,” in Proc. IEEE ISCAS, Kobe, Japan, May 2005, pp. 1887–1890. [9] F. Su, W. H. Ki, and C. Y. Tsui, “High efficiency cross-coupled doubler with no reversion loss,” in Proc. IEEE ISCAS, Koa, Greece, May 2006, pp. 2761–2764. [10] C. Yoo and K.-L. Lee, “A low-ripple poly-Si TFT charge pump for driver-integrated LCD panel,” IEEE Trans. Consumer Elec., pp. 606–610, May 2005. [11] D. Ma, “Robust multiple-phase switched-capacitor DC-DC converter with digital interleaving regulation scheme,” in IEEE/ACM Int. Symp. Low Power Electronics, 2006, pp. 400–405. [12] H. Chung, “Design and analysis of quasi-switched-capacitor step-up DC/DC converter,” in Proc. IEEE ISCAS, 1998, pp. IV-438–IV-441. [13] W. Chen, W. H. Ki, P. Mok, and M. S. Chan, “Dual-loop feedback for fast low dropout regulators,” in IEEE Power Elec. Specialists Conf., Vancouver, Canada, Jun. 2001, pp. 1265–1269. [14] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001.

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Feng Su (S’03) received the B.Sc. degree in automations from the Shanghai Jiao Tong University (SJTU), Shanghai, China, in 2003, and the Ph.D. degree from the Hong Kong University of Science and Technology, Hong Kong, China, in 2008. In Feb. 2009, he joined Broadcom Corporation, San Jose, CA, as a Staff Design Scientist. His research interests are fully integrated power management units (PMU) for RFID, micro-sensor and biomedical systems, analog and mixed-signal IC design techniques with emphasis on high performance switch mode and switched-capacitor power converters.

Wing-Hung Ki (S’86–M’91) received the B.Sc. degree in 1984 from the University of California at San Diego, the M.Sc. degree in 1985 from the California Institute of Technology, Pasadena, and the Engineer Degree in 1990 and the Ph.D. degree in 1995 from the University of California at Los Angeles, all in electrical engineering. He joined Micro Linear Corporation, San Jose, in 1992 as a Senior Design Engineer in the Department of Power and Battery Management, working on the design of power converter controllers. He then joined the Hong Kong University of Science and Technology in 1995, and is now an


Associate Professor in the Department of Electronic and Computer Engineering. His research interests are switch mode power converters, charge pumps, low dropout regulators, bandgap references, power management for micro-sensor and RFID applications, and analog IC design methodologies. Dr. Ki served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II during 2004–2005. He was the recipient of the Asia Innovator Award in 1998 granted by EDN Asia, and the Outstanding Design Award in 2004 and the Special Feature Award in 2006 of the LSI University Design Contest organized by the Asia and South Pacific Design Automation Conference.

Chi-Ying Tsui (M’95) received the B.S. degree in electrical engineering from the University of Hong Kong and the Ph.D. degree in computer engineering from the University of Southern California, Los Angeles, in 1994. He joined the Hong Kong University of Science and Technology in 1994 and is currently an Associate Professor in the Department of Electronic and Computer Engineering. He is also a cofounder of Perception Digital Ltd., a company which focuses on multimedia and wireless design. His research interests are designing VLSI architectures for low-power multimedia and wireless applications, designing power management circuits and techniques for embedded portable devices, and ultra-low-power system design.