Single-phase Voltage-doubler with Mismatched Capacitors for Balanced Output Voltages and Reduced DC-bus Voltage Ripples Wen-Long Ming, Qing-Chang Zhong Dept. of Automatic Control and Systems Engineering The University of Sheffield Sheffield, United Kingdom w.ming@sheffield.ac.uk,
[email protected]
Abstract— In this paper, a single-phase voltage-doubler with mismatched capacitors that converts a single-phase AC voltage to two balanced DC output voltages is proposed. It is based on a half-bridge rectifier and consists of two legs: one rectification leg to convert the AC voltage to DC output voltage and one neutral leg to split the DC output voltage into two balanced DC output voltages. Moreover, under the case with mismatched capacitors, the DC-bus voltage ripples can be significantly reduced compared to the ripples of the common singlephase half-bridge rectifier. The two legs can be independently controlled and the resulting high performance of the system is then achieved. Simulation results are provided to illustrate the excellent performance of the system.
I. I NTRODUCTION With the penetration of renewable energy systems, more and more converters are adopted to provide the interface between AC power grids and AC/DC renewable sources to regulate the frequency, amplitude and phase of the voltage and current. In order to reduce power pollutions caused by the converters, a power factor correction (PFC) circuit is often put at the utility interface to maintain the current drawn from the grid being clean and in phase with the grid voltage. In some circumstances [1]–[4], it is quite normal to have single-phase utility. As a result, many topologies for the switching mode single phase PFC circuits [5]– [9] have been studied in recent years. Among the PFC circuits, rectifiers named voltage-doublers [7], [8], [10]– [12] can provide the double output DC-bus voltage. One of the families, the half-bridge rectifier, features relatively low costs since only two switches are needed. The midpoint of the split DC-bus capacitors is connected to the neutral line of the power source so that half of the DC-bus voltage, that is the voltage across each capacitor, is higher than the peak amplitude of the source voltage. Thus, the output voltage is doubled compared to some normal rectifiers, e.g. full-bridge rectifiers.
978-1-4799-0336-8/13/$31.00 ©2013 IEEE
However, as a result of the mismatched topology, the voltages across the two DC-bus capacitors may be seriously unbalanced especially when dual balanced loads are operated. Essentially, the voltage imbalance results from the unbalanced currents flowing through the capacitors. But it is worth noting that even with same charging and discharging currents, the voltage imbalance still exists if the capacitors are mismatched. In principle, the voltage imbalance stems from the asymmetrical circuit. With this recognization, two main approaches from AC and DC sides have been reported to reduce or compensate voltage imbalance, respectively. One of the approaches is to regulate the source current from the AC side via changing control strategies for the existing halfbridge or via adding an auxiliary circuit to adjust the capacitor charging and discharging currents. In [7], the error of the voltages across the capacitors is fed into a proportional controller and then the output was taken as a DC component added into the existing current controller. This is to add a DC component to the source current to offset the unbalanced current flowing through two capacitors. However, the input power factor becomes worse and the ferroelectric cores for the inductor and the transformer may saturate because of the DC component. In [8], two switches are connected back-toback in series and then put across the AC power source. Also with the half-bridge rectifier, the additional two switches were turned on to slow down the rate of the capacitor discharging current so as to lower the voltage across one of the capacitors. This circuit features the high input power factor without any DC components. But the limited range for the ratio of the two loads to eliminate the voltage imbalance can become a problem when seriously unbalanced dual loads are operated. Either reducing the conversion efficiency or raising the output voltage is helpful to solve this problem. Many other strategies can be found in [11]. Most of them are focused on the AC side to eliminate the voltage imbalance
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and suffer from the mentioned problems more or less. The other approach is to add auxiliary circuits in the DC side to balance the voltages across the capacitors. The circuits are normally put across the DC bus and then connected to the midpoint of the capacitors to eliminate the voltage imbalance via regulating the capacitor charging and discharging currents. One of the circuits, the multilevel half-bridge converter, features reduced voltage across the switches and lower harmonic components in the input current and hence, it is very suitable for high power applications. Both diode and active neutral-point-clamped (DNPC and ANPC) multi-level converters have been studied in recent years. For example, two switches instead of two diodes in the 3L-DNPC are used in the 3L-ANPC to solve the unbalanced distribution of losses on the switches and to balance the voltages across the split capacitors. Although better performance is achieved, the system efficiency and reliability are reduced as a result of the four more switches compared to common half-bridge rectifier. Moreover, a neutral-point-clamped circuit used in the three-phase fourwire inverters has been reported in [13]–[15]. Two active switches are put across the DC bus and the midpoint of the switches is connected to the midpoint of the split DC-bus capacitors after an inductor. The formed neural point is then connected to the neutral line of the grid. The neutral current flowing in and out of the capacitors through the neutral point can be controlled around zero via turning on and off the two switches so that the voltage imbalance can be eliminated. Note that this actually facilitates the independent control of the neutral leg and phase leg, which means the three phases can be controlled independently. With this neutral leg, a parallel PI voltage-H ∞ current controller was proposed in [13] to balance the voltages, that was to control the current not around zero to eliminate the voltage imbalance when mismatched capacitors are operated. This topology can also be easily applied to the multi-level converters to enable the system operation even when unbalanced loads or mismatched capacitors are connected. In this paper, the idea of eliminating the voltage imbalance at the DC side is further explored to realize a double DC output voltage and two balanced output voltages. A topology for a single-phase voltage-doubler consisting of a rectification and a neutral leg is proposed and then the corresponding control strategies are developed. The main functions of the rectification leg are to draw a clean source current that is in phase with the source voltage and to regulate the DC-bus voltage. The neutral leg, taking the topology in [13], is used to split the DC output voltage into two balanced DC output voltages with reduced voltage ripples and to provide a return path for the rectification leg current. As a result, the control of the rectification leg and neutral leg becomes independent, which makes the design of control strategies much more flexible. A carefully-
designed parallel PI-Resonant voltage controller is used to accomplish a high loop gain, especially at the frequency of the voltage ripples, to simultaneously handle the ripple and DC components of the capacitor voltages. Meanwhile, under the case with mismatched capacitors, the DC-bus voltage ripples can be reduced compared to the ripples of the common single-phase half-bridge rectifier. The rest of the paper is organised as follows. In Section II, the topology of the proposed single-phase voltage-doubler is first given. After that, the analysis of how to realize balanced output voltages and reduce the DC-bus voltage ripples is addressed in detail. The associated control strategies are developed in Section III and simulation results are presented in Section IV, with conclusions made in Section V.
Q1
i+
C+
V+
R+
iC+ is ~
CQ2
R
VDC
iC
LLsa
R-
V-
i-
iC-
vs
N
(a) Q1
Q3
C+
i+ V+
iC+ is ~
LLsa
iL
iC
Lr
CQ2
Q4
iC-
R+ R
VDC
V-
Ri-
vs
N
(b) Fig. 1. Single-phase voltage-doublers based on the half-bridge rectifier: (a) with split capacitors; (b) with a neutral leg to split the voltages.
II. T HE P ROPOSED VOLTAGE - DOUBLER A. Topology The topology for the proposed single-phase voltagedoubler is shown in Figure 1(b). It is composed of a rectification leg and a neutral leg. The rectification leg contains two switches Q1 and Q2 and an inductor Ls . The main functions of this leg are to draw a clean current
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from the source that is in phase with the source voltage and to maintain the DC-bus voltage via switching on and off Q1 and Q2 . The neutral leg, taking the topology in [13], is formed by two switches Q3 and Q4 , an inductor and two split capacitors. It is controlled to split the DC output voltage into two balanced DC output voltages and to provide the return path for the rectification leg current. Moreover, according to Kirchhoff’s current law, the sum of the neutral current iC and the capacitor currents iC+ and −iC− is zero. As a result, if iC is regulated to be different values via controlling the switches Q3 and Q4 , currents flowing through the capacitors can be accordingly changed to balance the voltages. B. Elimination of Voltage Imbalance Assume the voltages across the capacitors C+ and C− with respect to the neutral point N and the negative point of DC bus are V+ and V− , respectively. Then the DC-bus voltage is VDC = V+ + V− and the voltage difference between two DC-bus capacitors is v d = V+ − V− . For the proposed system, the instantaneous voltages across the split capacitors can be written as t 1 iC+ (t)dt V+ (t) = V+ (0) − C+ 0 t 1 iC− (t)dt V− (t) = V− (0) − C− 0 in which V+ (0), iC+ and V− (0), iC− are the initial voltages and the passing current of the upper and lower DC bus capacitors, respectively. The voltage difference can be then rewritten as vd
=
V+ − V −
=
V+ (0) − V− (0) t 1 1 − ( iC+ (t) − iC− (t))dt, C C + − 0
(1)
which helps to confirm that, even with single load, the voltage difference can be very large if the initial values and/or the capacitance of the capacitors are different. In order to analyse the effect of the mismatched capacitors, it is assumed that C− = kC+ in which k > 0. Then, (1) can be reformed as vd
=
V+ (0) − V− (0) t 1 1 − (iC+ (t) − iC− (t))dt C+ 0 k
(2)
It can be seen that through regulating the two currents iC+ (t) and iC− (t), the voltages across the two capacitors can be changed accordingly. Suppose V+ (t) and V− (t) reach VDC at t1 , respectivley, then (2) can be rewritten as 2 t 1 1 (iC+ (t) − iC− (t))dt vd = − C + t1 k If vd is instantaneously 0, the following conditions 1 iC− . (3) k must be satisfied. In order to satisfy this condition, another current path must be provided for the current difference iC− −iC+ . This is actually why the neutral leg is connected to the midpoint of the split capacitors in the proposed topology. After introducing the neutral leg, the conditions for maintaining voltage balance become iC+
=
1 )iC− . (4) k It can be seen that another variable iC has been introduced into the relationship between iC− and iC+ , which means iC− can be controlled to be different with iC+ . This helps to balance the voltages through charging or discharging one of the capacitors more even if the initial voltages and/or the capacitance of the capacitors differ considerably. The control of the current iC can be realized through operating the switches Q3 and Q4 and the detailed control method will be given in Section III. It is also worth mentioning that there is no limit on the ratio of the dual loads to eliminate the voltage imbalance so that the proposed system is suitable for the cases with any loads. iC = (1 −
C. Reduction of DC-bus Voltage Ripples For single-phase voltage-doublers, √ if the source current is regulated to be sinusoidal as is√= 2Is sin(ωt) and in phase with the source voltage vs = 2Vs sin(ωt), then the output power can be divided into two parts: a constant power and a ripple power. As a result of the power balance at AC and DC sides, the DC-bus voltage can be expressed as 2 − E sin(2ωt) vdc = VDC C and hence, the DC-bus voltage ripples can be denoted as VDC =
E CVDC
where E = VsωIs is the system ripple power. This means the voltage ripples VDC are inversely proportional to the DC-bus capacitor C. Therefore, mismatched capacitors can lead to higher DC-bus voltage ripples because of smaller equivalent DC-bus capacitor C.
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be applied to track the reference current of is . Because of the excellent harmonic rejection performance, the repetitive controller shown in Figure 2(a) is adopted in this paper. The controller consists of a proportional controller Kr and k VDC VDC CN + (1+k) = E = VDC CN + VDC . an internal model: E = 4 1+k Kr As such, it can be found that , C(s) = ωi 1 − s+ωi e−τd s VDC 4 = where Kr and τd are designed based on the analysis in [20], VDC 2 + k + k1 [21] as of which the ratio between voltage ripples with and without 1 = 0.0199sec, τd = τ − the proposed neutral leg is defined. As k + k1 2 is always ω i V Kr = ω i L r , true for all k > 0, then VDC 1. This is to say the DCDC bus voltage ripple can be reduced to a much lower level in which Lr is the neutral line inductor and ωi = 10000, τ = compared to the ripples of common single-phase half-bridge 0.02sec. rectifier when the capacitors are mismatched. As shown in Figure 2(a), the current is is measured as a feedback to form the current error signal after subtracted III. C ONTROLLER D ESIGN by the reference source current. The output of the repetitive A. Control of the Rectification Leg controller is sent to a PWM generator as the modulation One of the main functions for the rectification leg is to signal compared with a triangle wave signal to generate the regulate the DC-bus voltage. For this purpose, the voltage PWM signal for the switches Q1 and Q2 . should be measured for feedback, which contains two parts: Q1 VDC* a constant component and a ripple one. The constant comPI PWM × Kr Q2 ponent is always hoped to be controlled equal to its reference + value and the ripple one is normally smoothed by DCsin(ωt) ωi is e −τ s bus capacitors. Thus, the constant component should be s + ωi STA H(s) first extracted from the DC-bus voltage for the feedback. Repetitive Controller Otherwise, the second-order harmonic can be introduced to v V s DC the control loop, which should be avoided. Here, the hold filter (a) 1 − e−T s/2 , H(s) = V+ PI T s/2 + where T is the fundamental period of the supply, is used to If with same system parameters, the ripple power with and without the proposed neutral leg is same, which can be expressed as
d
remove the ripple component. Because of the power balance between the AC and DC sides, the output of the PI controller can be set as peak amplitude of the reference source current. Apart from this amplitude information, the phase information of the source voltage is also needed to form the reference source current, which can make sure the current drawn from the source is in phase with the source voltage so that no reactive power is drawn from the source. This can be realized in many ways, e.g. with phase-lock loops [16], [17] or sinusoidal tracking algorithms (STA) [18]. In this paper, the STA proposed in [18] is adopted to extract the phase information of the source voltage. With the amplitude and phase information, the reference source current can be then formed. What is left now is to design a current controller so that the current is tracks the reference source current. Many current controller such as hysteresis controllers [19] that have a variable switching frequency and repetitive controllers [20] that have a fixed switching frequency, can
V-
iC
KR(s)
+
Q3 PWM Q4
PI
(b) Fig. 2. leg.
Control strategy: (a) for the rectification leg; (b) for the neutral
B. Control of the Neutral Leg The neutral leg formed by switches Q3 and Q4 , one inductor Lr and two split capacitors C+ and C− has been the studying target of a few papers [1], [15], [20], [22] on how to provide a neutral line for the three-phase four-wire inverters. After the inductor Lr , the midpoint of two switches is connected to that of the split capacitors. The neutral point N can be then obtained. Apart from the provision of the neutral point, another important function of the neutral leg is to provide the return path for the rectification leg current.
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As a result, the neutral point N is connected with the source neutral line. It is actually a combination of a split DC bus in the half-bridge rectifiers and a neutral leg but this makes the control of the neutral leg become independent with the rectification leg. In this paper, the main task of the neutral leg controller is to maintain the voltage difference vd close to zero via controlling Q3 and Q4 so that the voltage imbalance between the capacitors can be eliminated. At the same time, it should provide a return current path for the rectification leg. As mentioned before, as long as (4) is satisfied, the voltages can be balanced very well. Therefore, the control of the neutral leg is also a current-tracking problem. For this purpose, the neutral current should be measured for feedback. However, because the exact value of k is hard to be measured, which may also be changed after working for some years, it is difficult to directly meet the condition. This means if only currents are taken as the control variable, the voltage imbalance is hard to be completely eliminated. If k = 1, which means the split capacitors are balanced, the condition then becomes iC = 0. This can be realized via a PI current controller as shown in the lower part of Figure 2(b). However, in most cases, k is not euqal zero as discussed above. In order to remove the effect caused by the unbalanced capacitors, a voltage control loop is added after measuring the capacitor voltages V+ and V− . The output of the PI voltage controller is added with the output of the PI current controller to form the final control signal sent to the PWM generator as shown in Figure 2 (b). The function of the current controller is to maintain neutral current iC to be 0, that is to work with the AC component and the PI voltage controller is just to bring the constant voltage deviation of neutral voltage back to 0, that is to work with the DC components. It can be proved that the added voltage controller does not affect the stability of the current loop because the two controllers are decoupled in the frequency domain. As a result, a parallel voltage–current control structure is formed to eliminate the voltage imbalance. Moreover, for conditions with very heavy loads, the DC voltage ripple can become larger. Thus, the effect of the voltage ripple should be carefully considered when designing the controller for the neutral leg. But, as mentioned above, the added PI voltage controller is only designed to work with the DC component. Of course, the gain of the PI controller can be chosen big enough to reduce the secondorder components in the error signal. But this may affect the stability of the system, which should be avoided. In order to remove the effect of the voltage ripple, an additional gain at the second-order frequency is added in parallel with the current and PI voltage controllers via
implementing a resonant controller as described below KR (s) =
s2
2ξωs ×K + 4ξωs + (2w)2
of which the gain at frequency 2w is K with zero phase and ξ = 0.02 is used in simulations later. It is almost zero everywhere apart from the second-order frequency. The coefficient K can be tuned according to the system performance as a gain with a larger value for better performance. As such, the unbalanced voltage that contains DC and second-order components can be both suppressed significantly. After combining the PI current, PI and resonant voltage controllers, the final controller for the neutral leg can be depicted as shown in Figure 2(b). IV. S IMULATION R ESULTS Simulations were carried out in MATLAB/Simulink to verify the proposed voltage-doubler and the solver used was ode23tb with a maximum step size of 1μs. The parameters of the system are given in Table I. The parameters of the PI controller for the DC-bus voltage are KP = 0.05, KI = 2 and the gains of the PI controller for neutral current iC are KP = 10 and KI = 20. In addition, the paramaters of the PI and resonant voltage controllers are set to be KP = 0.5, KI = 10 and K = 20, respectively. The load R− was about two times the load R+ , which can cause large unbalanced current and then leads to large voltage difference between two capacitors. TABLE I PARAMETERS OF THE S YSTEM Parameters Supply voltage (RMS) Line frequency Ls DC-bus capacitance C+ DC-bus capacitanceC− DC-bus voltage VDC DC-bus Load R DC Load R+ DC Load R−
Values 110V 50Hz 2.2mH 1120μF 560μF 400V 1000Ω 470Ω 1000Ω
The proposed controllers for the rectification and neutral legs were started at 0.08 s. Note that the PI-Resonant voltage controller was inactive before 0.24 s so that its effect can be clearly observed. The performance of the rectification leg and the neutral leg is shown in Figure 3 and Figure 4, respectively. The current drawn from the source is in phase with the source voltage as shown in Figure 3(a). Moreover, it can be found from Figure 3(b) that the DCbus voltage was maintained well at its reference value. However, before starting the voltage controller, the voltages of capacitors are seriously unbalanced with different DC and ripple components. After 0.24 s, both V+ and V−
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300 200 100 0 −100 −200 −300
is
0
0.08
0.16 0.24 Time/s
V+/V V−/V
400
VDC/V
100 0
0.08
0.16 0.24 Time/s
0.32
0.4
(a)
0.4
(a) 600 500 400 300 200 100 0
200
vs
0.32
V−
V+
300
0
V+−V−/V
is/(A*5) vs/V
were maintained at 200 V with same ripples as shown in Figure 4(a). The voltage difference became very small after the voltage controller was activated. Note that the DC-bus voltage ripples also became smaller as illustrated in Figure 3(b) and Figure 4(a), which is consistent with the analysis before.
200 150 100 50 0 −50 −100 −150 −200
0
0.08
0.16 0.24 Time/s
0.32
0.4
(b) Fig. 4. Simulation results of the neutral leg: (a) Voltage across the split capacitors V+ and V− ; (b) Voltage difference V+ − V− .
0
0.08
0.16 0.24 Time/s
0.32
R EFERENCES
0.4
(b) Fig. 3. Simulation results of the rectification leg: (a) Source current is and voltage vs ; (b) DC-bus voltage VDC .
V. C ONCLUSIONS A single-phase voltage-doubler has been proposed for providing two balanced output voltages and reduced DC-bus voltage ripples with mismatched capacitors. It consists of one rectification leg and one neutral leg. The main functions of the rectification leg are to draw a clean current that is in phase with the source voltage and to generate a stable DCbus output voltage. Thanks to the neutral leg, the DC-bus voltage can be split into two balanced DC output voltages. In addition, compared to the DC-bus voltage ripple of the common single-phase half-bridge rectifier, the ripple of the proposed voltage-doubler can be reduced when mismatched capacitors are connected. This enables the system to have a high performance over a long period even if the capacitors become mismatched after working for many years. All these functions can be realized in an independent way after the introduction of the neutral leg and the decoupled control strategies are carefully designed for the neutral leg and rectification leg, respectively. Simulation results have demonstrated excellent performance of the proposed system.
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