The 2014 International Power Electronics Conference
Dynamic Voltage Balancing Algorithm for Modular Multilevel Converter with Three-Level Flying Capacitor Submodules Apparao Dekkao, Bin Wuo and Navid R. Zargarit °
Dept. of Electrical and Computer Engineering, Ryerson University, Toronto, ON MSB 2K3, Canada t Medium-Voltage Drive R&D, Rockwell Automation, Cambridge, ON NIR SXl, Canada E-mail:
[email protected]@ee.ryerson.ca and
[email protected]
Abstract-The modular multilevel converter (MMC) has sev eral three-level flying capacitor (3L-FC) submodules in cascade. To balance the submodule capacitors voltage, this paper describes a dynamic voltage balancing algorithm based on the carrier phase shifted pulse width modulation (CPS-PWM) scheme. The submodules are controlled based on the instantaneous value of capacitor voltage and the direction of current. For the selection of the submodules, the maximum and minimum voltage submodule selection logics are designed. These voltage logics are generating an index number for each submodule based on the relative comparison of capacitors voltage. Finally the switching state of the submodules is generated by comparing the submodule index number with the dynamic reference index number. The performance of the proposed voltage balancing algorithm at different operating conditions is evaluated on 6kV/2MVA MMC system with the MATLAB simulation and the corresponding results are presented. In addition, the performance comparison of MMC with 3L-FC and conventional two-level half bridge (2L
lIB)
submodules is presented.
Index Terms-Capacitor voltage balancing, circulating cur
rents, flying capacitor (FC) converter, modular multilevel con
(a)
verter (MMC), pulse width modulation (PWM)
I.
INTRODUCTION
The increase in the production rate and the economy of scale are demands the high power, multilevel converter systems [1]-[3]. In the last few decades, various multilevel converter topologies are investigated and are presented in [1]-[3]. The most popular multilevel converter topologies are (i) neutral point clamped (NPC) converter, (ii) flying capacitor (FC) converter and (iii) cascade H-bridge converter (CHB) [1]-[3]. The application of these converter topologies at high voltage, high power level is restricted by the semiconductor ratings, extra number of devices, assembly of the converter, dc link capacitors and the dc voltage balancing capability etc [1]-[3]. In recent years, the modular multilevel converter has gained more attention for high voltage applications due to its in herent features such as modular structure, common dc bus terminals and the possibility of back-back operation etc [4] [8]. The modular multilevel converter is first introduced in [8]-[lO] for high voltage direct current (HV DC) applications. The research on MMC is continuously growing in the areas of medium voltage motor drives [6], medium voltage static compensator [11], solar photo voltaic application [7] etc.
978-1-4799-2705-0/14/$31.00 ©2014 IEEE
(b) Figure 1. (a) Power circuit of three phase MMC (b) Three level half bridge flying capacitor converter
Various configurations of MMC and their applications are discussed in [4]-[8]. The generalized structure of the modular multilevel converter is shown in Fig. l(a), uses two-level half bridge (2L-HB) converter as submodule. To meet the required operating voltage, these submodules are connected in cascade.
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The 2014 International Power Electronics Conference However it is also possible to use the well established mul tilevel converter technology in MMC. The three-level flying capacitor (3L-FC) submodule is considered as an alternative for two-level half bridge (2L-HB) submodule, which is shown in Fig. l(b). With any submodule technology, the voltage balancing of floating capacitors is necessary. In the literature, various voltage balancing algorithms are discussed for MMC with 2L-HB submodules [7], [12]-[16]. These algorithms are facing the following difficulties such as complexity in the implementation for higher number of submodules, accuracy and the requirement of converter parameters, requirement of huge memory to store the mapping process and the stability issues etc. In this paper a new generalized voltage balancing algorithm is proposed for modular multilevel converter. The proposed algorithm is also applicable to the conventional two-level half bridge (2L-HB) submodules. The balancing algorithm does not require the sorting technique to select the submodules, which will reduce the burden on the controller. Here a simple submodule selection logics are designed based on the relative comparison of normalized submodule capacitors voltage. The final switching state for the submodules is generated by dynamically. With the present approach, the implementation and the extending to higher number of modules is quite easy. In addition, a simple modulation stage based on the carrier phase shifted pulse width modulation (CPS-PWM) scheme is presented for modular multilevel converter. The output of the modulation stage is a normalized reference PWM waveform, which resembles the actual output voltage waveform of the converter. The effectiveness of the proposed algorithm is verified at different operating conditions by means of MATLAB simulation and the results are presented. The main features of the proposed modulation stage and balancing algorithms are: •
•
•
•
It avoids the extra computations such as calculation of required number of on-state cells at every switching instant In addition to the voltage balancing, it can generate the predefined voltage waveform at the output of the converter Implementation and extending to the higher number of modules per arm is easy It does not require the sorting technique for the selection of submodules
In addition to the voltage balancing, the circulating currents is a one of the major issue in modular multilevel converter. The second harmonic current component is a dominant component in the circulating currents and its magnitude is depends on the modulation index (M) , fundamental frequency (F) and power factor (PF) [17]-[21]. These circulating currents have the severe impact on the performance of the modular multilevel converter, especially the harmonic distortion, device power losses and the converter efficiency are deteriorates. The circu lating currents are minimized by using buffer inductors [17]. However, the size of the buffer inductors is small so its impact
Table I
SWITCHING STATES OF 3L-FC SUBMODULE
81
82
81
82
Vpq
ixy > 0
ixy:S; 0
1
1
0
0
Vel
vcl t,vc2 ;::::
Vcl +,Vc2 ;::::
Vcl ;:::::,Vc2 t Vel t,vc2 +
Vcl :::::::,Vc2 + Vel -l-,vc2 t
0
1
1
0
vc2
1
0
0
1
Vel - Vc2
0
0
1
1
0
Vcl ;::::;:,Vc2 ;::::;: Vcl ;'::::;:,Vc2 :=::::
on the circulating currents is limited. The control method using resonant current controller is presented in [18]. In this method, the current controller is designed to eliminate the dominant harmonic component from the circulating currents. The control method based on the synchronous reference frame theory with the simple proportional-integral (PI) controller is discussed in [21]. However, the circulating currents can be minimized by using properly designed multilevel submodules. In this paper, the 3L-FC submodule is proposed to minimize the circulating currents. By selecting the proper capacitance value of the floating capacitors, the voltage ripples and the magnitude of circulating currents are significantly minimized. To study the effectiveness of the 3L-FC submodule, a performance compar ison between the MMC with 3L-FC and 2L-HB submodules is presented. The paper is organized as follows: Section II provides the basic structure and the operation details of the MMC. The sec tion III gives the modulation scheme and the voltage balancing algorithm for MMC. In section IV, the effectiveness of voltage balancing algorithm is presented. In addition, the performance comparison of MMC with 3L-FC and 2L-HB submodules at the different operating power factors is discussed. Finally conclusions are given in section V. II.
MODULAR MULTILEVEL CONVERTER
A. Basic Structure
The generalized three phase structure of the modular mul tilevel converter is shown in Fig. l(a), which is realized by using two three-phase CHB structures connected their output terminals through buffer inductors (Lxy) . Where x represents the phase (x a, b, c) and y represents the arm (y p, n) . The output terminal (x) is divided the each phase into two arms, positive arm (p) and negative arm (n), and each arm consists of N-submodules and a buffer inductor (Lxy) . The structure of the submodule is shown in Fig. l(b), which is a three-level flying capacitor (3L-FC) topology. Each submodule is further divided into two cells, where 81 , S\ and C1 are considered as cell-I, and 82 , 82 and capacitor C2 are considered as cell-2. Each 3L-FC submodule has two floating capacitors C1 and C2 with a voltages of Vel and Vc2 respectively. The outer capacitor voltage (Vc1 ) is twice that of inner capacitor voltage (Vc2 ) ' The charging and discharging of these floating capacitors is depends on the direction of arm current and the corresponding switching states. The Table I shows the output voltage levels
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=
=
The 2014 International Power Electronics Conference From the equivalent circuit shown in Fig. 2, the output phase voltage with respect to the dc bus midpoint is expressed as follows:
� 2
1 d(ixn - ixp) . )] Vxo = 2 [vxn - Vxp + L + R CZxn - Zxp dt
/�'\
l
.,
( \; \..
substitute the equation (4) in (5), then the final output voltage is become as follows
•
: iXZ ••••'
1 dix . ] Vxo = 2" [vxn - Vxp - Ldi - Rzx
•
� 2
.
(5)
(6)
The voltage across the buffer inductor due to the circulating currents is given as
.'
.... _ ....
dixz . 1 LTt + Rzxz = 2" ( Vde - vxp - Vxn)
(7)
Figure 2. Single phase equivalent circuit of MMC
From the equations (6) and (7), the output voltage and the circulating currents are realized by controlling the positive and negative arm voltages. Based on the above analysis, the positive and negative arm voltages are deducted as
and the variation of capacitors voltage in 3L-FC submodule for different switching states.
Vde vxp = 2 - Vx
B. Principle of Operation
Vde Vxn = 2 +vx
Depends on the switching state, the 3L-FC submodule can generate a different voltage levels at the output. So each submodule can be modeled as a controlled voltage source and each arm contains N-controlled voltage sources in cascade. The output arm voltage is equal to the sum of N-controlled voltage sources. For the analysis, the MMC system can be further simplified and the single phase equivalent circuit is shown in Fig. 2. Where Vde and ide are the total dc bus voltage and dc current, Land R are the buffer inductance and their equivalent resistance, Vx and ix are the converter output voltage and output line current. The output voltage of the cascaded submodules in positive and negative arms are represented as a AC voltage source of vxp and Vxn respec tively. The required voltage at the output (vxo) is generated by controlling the voltage sources of positive (vxp) and negative arms (vxn) . From the equivalent circuit shown in Fig.2, the current flowing through the positive and negative arms are given as
ix . . zxp = Zxz + 2
(1)
ix . . Zxn = Zxz - 2
(2)
where ixp and ixn are the current flowing through the positive and negative arms respectively, ixz is the circulating current and ix is the output current flowing through the load. By adding the equation (1) and (2), the circulating current flowing through the phase is given as
. ixp + ixn Zxz = 2
(3)
By subtracting the equation (2) from (1), then the output current is becomes
ix = ixp - ixn
(4)
(8)
Where Vx is the output phase voltage, which is in the following form:
(9) where M is the modulation index (0 � M � 1), ex is the initial output phase angle and Wo is the output angular frequency. The equation (8) shows, each arm in MMC can be controlled independently by using individual modulating signals. Even though, the above analysis and the conclusions are deducted based on the single phase equivalent circuit, but this can be applicable to the MMC system with the any number of phases. III.
MODULATION SCHEME AND VOLTAGE BALANCING AL GORI T HM
A. Modulation Scheme for MMC
The number of voltage levels at the output of the MMC is depends on the phase shift between the triangular carrier signals and the number of submodules. The 3L-FC submodule is considered as an alternative to the 2L-HB submodule. Each 3L-FC submodule can be controlled by using two phase shifted triangular carrier signals [12], so for 2N-submodules per phase requires a 4N-triangular carrier signals. The 4N-triangular carriers are disposed with a phase shift of 3:�o and the carriers which belongs to the same arm are disposed with a phase shift of 3;�o . With the above carrier arrangement, the modular multilevel converter with N-3L-FC submodules per arm can generate a 2N + 1 voltage levels at the output. In addition to the carrier signals, the PWM modulator is requires a reference modulating signal. In modular multilevel converter, each phase can be divided into two arms and each arm can be controlled independently. So it requires a two reference modulating signals, one for the positive arm (v��f) and another
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The 2014 International Power Electronics Conference
PWM
Yes
Minimum Voltage
Maximum Voltage Waveform
2N
Vcxp_k ixp S':P_k i
t
Logic
Logic
Referece PWM
........................
p Sxn_
P sxp_k
i •••••••••••••••••••••••
Dynamic
�
Vcxn_k ixn S':p_k
SXY_k else
!
SXY_k
Index =
2N -Dxy if
0
2N
Figure 3. Single phase based pulse width modulator for MMC
for the negative arm (v�,:!) , where x represents the phase (x a, b, c). The individual reference modulating signals are generated by adding the fixed offset to the reference output phase voltage. The reference modulating signals for each arm is given as
2N
Reference
mCk;:O:
else
SXY_k
�
2N
=
Vdc vre xpf -""2 Vx Vdc vre xnf =- +vx
Figure 4. Flow chart of voltage balancing algorithm for MMC
B. Voltage Balancing Algorithm
_
-
(10)
2
where Vx is the reference output phase voltage, which is given in the equation (9) . The structure of the PWM modulator is shown in Fig. 3, where the reference modulating signal for each arm is generated corresponding to the modulation index (M) and the initial phase angle (ex) . The reference modulation signal of the arm is compared with the each triangular carrier signal of the corresponding arm. The output of each comparator is summed up, which gives the normalized reference PWM waveform (Dxy) , where y represents the arm (y = p, n). The reference PWM waveform (Dxy) represents the normalized voltage levels of 0, 1, 2, ...., 2N, which is also equal to the required number of on-state cells. If Dxy=2N, then the required number of on-state cells is equal to 2N. The output of PWM modulator is a reference PWM waveform, which resembles the actual output voltage waveform of the converter. The normalized PWM waveform is given as the input to the voltage balancing algorithm. The voltage balancing algorithm will select and apply the required switching state to the submodule based on the required number of on-state cells, instantaneous value of submodule capacitors voltage and the direction of arm current.
The balancing of submodule capacitors voltage is achieved either by using external controllers or by using the redundant switching states. The complexity in the designing of the external controllers for voltage balancing is increases with the number of submodules. Also this method is involves the sta bility problems due to the interaction between the controllers [21J. In contrast, the voltage balancing with the redundancy switching states is the easiest method. However, the number of redundant switching states is drastically increases with the number of submodules. The selection of required switching state from such a high redundancy is difficult and requires a sophisticated method. Also this method is involves the huge memory to store the redundancy switching states. To minimize the complexity and the requirement of memory, this paper is describes a generalized voltage balancing algorithm based on the dynamic switching state selection approach. The proposed approach is easily implemented in the digital controllers like DSPIFPGA, computational less complex and easily extendable to the higher number of submodules. The voltage balancing algorithm is mainly involves the following steps:
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• • •
step- l: Calculation of required number of submodules step-2: Selection of submodules step-3: Generation of switching state of submodules
The 2014 International Power Electronics Conference
+
the any type of submodules without any major changes. In submodule selection logic, each normalized capacitor voltage is compared with the other normalized capacitor voltages. The output of the each comparator is added together and the resultant output is the index number of the corresponding cell (mh_k or mU). Similarly, the relative comparison between the other capacitors voltages is executed and the corresponding index numbers are provided by the submodule selection logics. The index number of each cell represents the priority order of that particular cell. The switching state for the each cell is generated by comparing the cell index number with the dynamic reference index number OR). If cell index number (mh_k or mCk) is greater than or equal to the reference index number OR) then the corresponding cell is turned on. The dynamic reference index number is generated based on the equation (11) � = 2N Dxy (11)
mh_l
+
+
mh_2
+
+
mh_2N
+
(a)
