routing, but the algorithm is applicable to a broader class of problems than the grid-based ..... We apply the Max-Flow Min-Cut theorem. In. Cases 1 and 4, it is ...
Ecient Breakout Routing in Printed Circuit Boards (Extended Abstract) John Hershberger? and Subhash Suri??
Abstract. Breakout routing is a single-layer wire-routing problem in which each of a set of pins must be connected to one of a set of vias, but no matching is prespeci ed. We propose a network- ow approach to breakout routing in which the wiring grid is modeled by a more compact graph. Our graph is a factor of (2 ) smaller than the wiring grid, where is the ratio of via spacing to pin spacing, which improves both the space and run time eciency of the ow computation. A ow in the compact graph can be transformed into a wire layout, and vice versa.
1 Introduction Breakout routing is a crucial problem in routing printed circuit boards (PCBs) and multichip modules (MCMs). The problem arises because a typical PCB or MCM has multiple layers available for routing, but electronic components are often connected to only a single layer of the board. Completing the routing requires that these surface-mounted components be connected to other layers by vias. The most ecient way to do this is to place a set of breakout vias near the component, connect each surface-mounted pin to a unique via, and then nish routing the connections from via to via using all the routing layers. Breakout routing is qualitatively di erent from ordinary PCB routing: the connections from pins to breakout vias lie in a single routing layer, whereas ordinary routing may use multiple layers to cross one wire over another. The pairing of pins with breakout vias is not xed: any pin may be connected to any via, because the connections speci ed by the circuit schematic will be routed between pairs of vias. At the highest level of circuit board design, positions of wires, vias, and even components are all exible. The design process removes exibility little by little, while trying to preserve feasibility. The sequential removal of
exibility may lead to a non-optimal solution (because the problem is NP-hard), but reduces the complexity of the solution process to something manageable. Partitioning the breakout routing problem into two phases, via site selection and subsequent routing of pins to vias, is an example of imposing sequentiality where the problem does not require it, in the interest of simplifying the process. Breakout routing is often the hardest part of routing a PCB or MCM|once the ? ??
Mentor Graphics, 1001 Ridder Park Drive, San Jose, CA 94301 Department of Computer Science, Washington University, St. Louis, MO 63130. Research supported in part by NSF Grant CCR-9501494
pins have been connected to all routing layers by breakout vias, nishing the schematic-speci ed connections is straightforward. Proper separation or spacing of breakout vias is important. A via blocks routing on all layers through which it passes. (Depending on the technology, a via may pierce all layers, or just a contiguous subset of layers.) Thus, if breakout vias are placed too close together, they will form an impenetrable barrier to routing on all layers they intersect. In particular, placing breakout vias under the component pins, which usually lie in closely spaced rows, is a bad idea, because it precludes using the area under the components for routing. (N.B. PCB routing is di erent from channel routing of integrated circuits, in which the component area is unavailable for routing.) Likewise, manufacturing technology often dictates that vias may be placed only on a coarse grid. Thus, in practice, breakout vias are often chosen to lie on a grid that is signi cantly coarser than the component pin spacing. While in current systems the ratio of via spacing to pin spacing is still under ten, technology trends (such as MCMs and ball grid arrays) are expected to increase the ratio to \tens." Ball grid arrays (BGAs) also pose problems closely related to breakout routing. When a BGA component is mounted on a PCB, it connects to a coarse rectangular grid of pins on the board surface. Connections from these pins must be routed outward from the component, either on a single layer, or on multiple layers using vias. The outward connections on each layer must be planar, so the problem is similar to breakout routing, with the BGA pins playing the role of the breakout vias and the component boundary playing the role of the pins. A related problem also arises in VLSI processor arrays, in the context of faulttolerant recon guration [5]. The recon guration problem in processor arrays is to match a set of N nodes (faulty processors) in an m n rectangular grid with nodes on the grid boundary using disjoint paths. The fastest known algorithm for this p problem is due to Chan and Chin [1]|their algorithm runs in time O(d nmN), where d is the maximum number of disjoint paths found. More interestingly, they p show that the size of the grid graph can be compressed from O(nm) to O( nmN) for the recon guration problem. While our results are somewhat incomparable, our compressed graph is smaller by a factor of in the extreme case of ?full via grid; in particular, the compressed ? nm graph of Chan and Chin has size O nm , whereas our graph has size O 2 .
1.1 Previous Work Due to the importance of breakout routing in design automation, there has been a lot of work on the problem. Not all techniques necessarily appear in the scienti c literature, and some are even protected by patents. Nevertheless, there seem to be at least ve di erent methods for breakout routing. In computer science terminology, all but the last one can be viewed as \greedy methods." 1. [Pattern routing.] Each pin has a preferred breakout via and wiring pattern, along with a short list of alternates. If none of the patterns is feasible, the pin is not connected to any breakout via. The patterns typically capture
2.
3.
4.
5.
a designer's experience in routing. This method can be ne-tuned for speci c boards, but provides no general guarantees of success. [One at a time connection, without pin assignment] Start routing from a pin, and terminate at the rst available via. Repeat for all pins. Obviously, a wrong route or a bad choice of via can cause this method to fail, even when a feasible routing exists. Nevertheless this method can work well if vias are well-distributed. [One at a time connection, with pin assignment] One rst nds an \assignment" (a matching) of vias to pins, and then uses an ordinary maze router to complete the routing for each pin-via pair. Most of the intelligence in this method is built into the rst phase, which nds the pin assignment. This method has the potential to be better than method 2, but it also is not guaranteed to nd a valid routing. [Pattern routing in a grid.] In the special case in which the vias lie in a rectangular grid and pins are located on its periphery, connect pins to vias with p a regular pattern of wires. This method is guaranteed to nd at least 1= 2 of the maximum possible number of connections [7], but it is limited to the case of a fully populated via grid. [Network ow.] The network ow approach is to solve the routing problem by computing a \ ow" on the grid graph, where pins and vias are taken as sources and sinks, and where the grid spacing is the same as the minimum wire spacing. This method clearly nds a feasible routing if one exists, but it appears to be more popular in theory [2, p. 625] than in practice, perhaps because of the asymptotic complexity of network ow algorithms. One big disadvantage of the \vanilla" network ow method is that the size of the grid graph can be quadratic in the number of pins. Recent work by Yu, Darnauer, and Dai [8] uses network ow on a graph derived from a constrained Delaunay triangulation to solve the breakout problem approximately. The resulting ow may not correspond to a feasible routing, but the algorithm is applicable to a broader class of problems than the grid-based approach.
1.2 Our Contribution Our method can be viewed as combining the best features of the last two methods: pattern routing in a grid and network ow. Like pattern routing in a grid, it exploits the fact that vias lie on a grid, but it allows some sites in the via grid to be inactive. It uses a network ow framework and always nds an optimal number of routes, but it does not explicitly build the entire grid graph. In particular, suppose that n breakout vias lie within a rectangular grid of size p q, and m component pins lie on the boundary of the rectangle, where m n pq. Our algorithm computes network ow in a network of size O(pq), whereas the conventional approach will construct a grid graph of size at least (pq2 ), where + 1 is the ratio of via spacing to pin spacing. (In Figure 1, p = q = 5, m = 6, and = 3.) We believe that the improvement by a factor of 2 in running time
and, more signi cantly, in space can make our approach a viable candidate for breakout routing in practice. Our \coarsened" network ow algorithm can determine the precise assignment between the pins and vias, but computing the actual geometric layout of the wires does require the ner grid graph. Fortunately, the detailed layout phase of our algorithm is highly local, operating at the level of a single \via cell." Thus, the algorithm needs to consider the detailed grid graph only one cell at a time, requiring O(2 ) additional space. Secondly, in an interactive design environment, feasibility tests, which check whether a component placement admits a routing, are far more numerous than detailed layout computation, which is typically carried out only for the nal design. Thus, our algorithm can be valuable for making design software run at interactive speeds. Because this paper works with the coarser, via-grid-level graph, we explore the \combinatorial" structure of the routing problem in far more detail than is necessary at the wire grid level. We develop some general techniques for formulating and solving routing problems at the level of via cells. Our approach involves an interesting interplay of geometry and network ow. We rst develop a network model of the problem that allows us to work at a \combinatorial" level, dealing only with the number of wires entering or leaving a via cell through each edge, rather than their exact positions. Thus the amount of data maintained per via cell is a constant independent of . The second part of our algorithm transforms the combinatorial data at a cell level into an embedding: any feasible
ow inside a cell can be realized as a wire embedding. The cell layout algorithm requires a certain exibility in terminating wires on the boundary of the cell. Without the exibility to choose wire endpoints, many legal ows turn out to be unembeddable. That is, if we require wires to terminate at certain xed positions on the boundary, then some legal ows cannot be geometrically embedded. However, the same ows can be embedded for di erent positions of wires. The algorithm's dilemma is this: complete freedom to place wires anywhere on the boundary ensures that all legal ows can be successfully embedded, but two adjacent cells may place a common wire at mutually inconsistent positions; on the other hand, forcing wire positions on the boundary may not be always feasible. Fortunately, there turns out to be a simple solution to this problem. The idea is to orient each cell (clockwise or counterclockwise), and force wires in each cell to be positioned at the speci ed end of each edge. By alternating cell orientations in a checkerboard fashion, we can ensure that wire positions enforced on an edge by its two adjacent cells are consistent. More importantly, we show that even with this constraint, any legal ow in a cell can be embedded.
2 Preliminaries and the Combinatorial Wire Flow Consider a ( + 1) ( + 1) square, partitioned into ( + 1)2 unit squares by a square grid, for a nonnegative integer . Let us call the big square a via cell , its four corners via sites , the unit grid the wire grid , and vertices of the unit
grid grid points .3 For purposes of breakout routing, a printed circuit board can be modeled as a rectangular tiling of via cells. The parameter , which we call via separation , determines the maximum number of wires that can be routed between two adjacent vias in any row or column. Figure 1 shows an example. via location
A wire element is an edge of a unit square in the wire grid. A wire path is a simple (non-self-intersecting) path made up of wire elements. In this paper, all our wire paths will connect a pin location to a via location, and we assume throughout that these paths are directed from the pin to the via. Each via can either act as a sink node for a wire path, or as a transit node, but not both. If a via can act only as a sink, and not a transit node, then our algorithm and method still apply, with only a minor modi cation in the construction.
via site
wire grid
(a)
pins (b)
Fig. 1. (a) Via cell; = 3. (b) Tiling of cells.
A matching between a set of pins P =
fp1, p2, : : :, pm g and a set of vias V = fv1, v2 , : : :, vn g is a pairing f(p1 ; v1), (p2; v2), : : :,(pk ; vk )g where each pin or via appears at most once. A complete matching is a matching where each pin appears exactly once; that is, k = m. A matching is embeddable if each matched pair can be joined by a wire path in the
wire grid so that all paths are pairwise non-intersecting. In this paper, we will be interested only in embeddable matchings, and so we assume in the following that a matching is always embeddable. As mentioned before, we assume that each wire path is directed from its source pin to its sink via. Finally, we de ne the notion of a wire element entering or leaving a cell. We say that a wire element x enters a cell c if x's head is on the boundary of c but its tail is outside c. Similarly, x exits a cell c if x's tail is on the boundary of c but its head is outside c. Figure 2 illustrates these de nitions.
3
Thus, a via site is also a grid point.
In order to reason about breakout routing at the x1 level of via cells, we rst need to establish some \combinatorial" properties of a matching. Our approach is x6 x2 to keep just the net number of wires entering or leaving through each side of a cell. In order for such an aggreCell c gate approach to work, we need to understand which x3 combinations of these numbers correspond to feasible x5 x4 wirings, and which do not. Obviously, the via separation gives an upper bound on the maximum number Fig. 2. Wire eleof wires that can pass through an edge, but this simments x1 enters c ple condition by itself is not sucient. Let us introduce and x2 leaves c. some more de nitions to facilitate the discussion. Similarly, x3 and In order to discuss the wire layout in a via cell, x5 enter c, while x4 it is convenient to separate the boundary of the cell and x6 leave c. No from its interior. Let us de ne the core of a cell c to be other wire element the subgrid in the center of c. The boundary of shown is entering c is the square de ning c. In Figure 1 (a), the central or leaving c. 3 3 grid is the core of the via cell. Let us discuss the combinatorial properties of a wire layout with respect to the core of a cell. The main property of a core that we need in the following discussion is that a core has no vias, and therefore no wire terminates inside a core. Fix a matching M for the ensuing discussion, and consider the core b of a via cell c. Let ei (b), for 1 i 4, denote the edges of the square b in clockwise order, starting from the left edge. Let fi (b) denote the number of wire elements in M that enter b through ei (b), and let gi (b) denote the number of wire elements in M that leave b through ei (b), where 1 i 4. (We omit b from the notation for fi ; gi whenever the identity of the square is clear from the context.) The following two constraints are easily established: 1. [Capacity Constraint] fP . i (b) + gi (b) P 4 4 2. [Wire Conservation] f (b) ? i i=1 i=1 gi(b) = 0. The capacity constraint follows from the fact that wires in M are disjoint and that each side of b has wire capacity . Wire conservation follows from the fact each wire of M terminates at a via and the core b is via-free. The number of wire elements in M entering or leaving b through each of its four sides describes the combinatorial wire ow in b. The capacity constraint and wire conservation are clearly necessary for a combinatorial wire ow to be embeddable. Unfortunately, they are not at all sucient, as the following example shows: Let f1 = f2 = , f3 = f4 = 0; g1 = g2 = 0; and g3 = g4 = . It can easily be veri ed that this combinatorial ow satis es the capacity constraint and wire conservation, but cannot be embedded. It turns out that the maximum number of wire elements entering b in a legal embedding can vary from to 2 depending on the topology of wires. Our next lemma gives a full characterization of this combinatorial fact.
Let xi = fi ? gi denote the net ow of wires into b through the edge ei . The edge ei is called a surplus edge if xi > 0, a de cit edge if xi < 0, and neutral otherwise. We de ne the type of a square b depending on the number of surplus edges; see Figure 3, where (a), (b), (c) illustrate types I, II, and III.
Type I: b has exactly one surplus edge or exactly one de cit edge. Type II: b has two surplus edges sharing a common vertex. Type III: b has two surplus edges that are opposite (nonadjacent) edges of b.
e2
e2 e3
e1
e1
e2 e3
e3
e1
e4
e4
e4
(a)
(b)
(c)
Fig. 3. Three types of cells: (a) Type I; (b) Type II; (c) Type III. Wire conservation guarantees that not all four edges can be surplus or de cit. The case in which all four edges are neutral will not play any important role in our algorithm, as will become evident soon. The following lemma uses the characterization above to give tight bounds on the maximum in ow into a core. By symmetry, the same bounds also hold for out ow.
Lemma 1. The maximum wire in ow into a square core b satis es the following bounds:
4 X
i=1
max(fi ? gi ; 0)
8
0, a demand node if (u) < 0, and transshipmentPnode otherwise. We assume that total supply equals total demand, that is, u (u) = 0. A ow on G is a real-valued function on vertex pairs satisfying the following: Anti-symmetry: (u; v) = ? (v; u). Capacity Constraint: (u; v) cap(u; v). Flow Conservation: Pv (u; v) ? Pv (v; u) = (u), for all u 2 V . The value of the ow is the sum of (u) over all supply nodes. In some cases, each node u also has a nonnegative capacity cap(u), denoting the maximum ow leaving u. In this case, a ow satis es the following additional constraint: Node Capacity: Pv (u; v) cap(u). It is easy to convert a network with node capacity constraints into one with only edge capacity constraints. Suppose a node u has capacity constraint cap(u). We replace u with two new nodes u and u , add a directed edge (u ; u ) between them, and assign it capacity cap(u ; u ) = cap(u). Finally, we transfer all incoming edges of u to u , and all outgoing edges of u to u . It is easy to see that the new network is equivalent to the old one for the purpose of ows. In order to keep our notation and gures simple, we will retain node capacity constraints in our discussion, but keep in mind how they can be transformed into edge capacity constraints. In fact, for ease of reference, let us call (u ; u ) the node capacity edge of u. A cut in a graph G = (V; E) is a partition of the nodes V into two nonempty sets V1 and V2 . We denote this cut by [V1 ; V2]. Given a cut [V1 ; V2], an edge (u1; u2) 2 E is called a forward edge if u1 2 V1 and u2 2 V2 . Similarly, (u1; u2) is a backward edge if u1 2 V2 and u2 2 V1 . The capacity of a cut [V1 ; V2] equals the total capacity of all forward edges. The following celebrated theorem of network
ow will be used throughout [2, p. 593] Theorem2 (Max-Flow Min-Cut). Let Vs and Vd , respectively, denote the set of supply and demand nodes in a network G = (V; E). Then a ow satisfying the supplies and demands of Vs and Vd exists if and only if the total supply does not exceed the minimum capacity of a cut [V1; V2 ] where Vs V1 and Vd V2 . Let be a ow in N . We say that is canonical if for each pair of nodes (u; v), the ow value (u; v) is integral. The following lemma is well-known in network ow theory; a constructive proof of this fact follows easily from the correctness of the classical Ford-Fulkerson ow augmentation algorithm. Lemma 3. For every integer-valued ow , there exists a canonical ow of the 0
00
0
0
00
00
0
00
0
00
same value.
We are now ready to describe the graph structure of our network. All capacities in our network are integers, and therefore we can assume that all integervalued ows are canonical.
3.2 Network Model for the Via Grid In our construction, the following diamond network will play a crucial role; see Figure 5. The four nodes on the outer cycle are labeled a1 ; a2; a3; a4, joined by edges of bidirectional capacity 1 = b=2c; whenever an edge is drawn undirected, it should be interpreted as having the same capacity in both directions. In addition, there is a central node a0 , joined to the four other nodes by edges of bidirectional capacity 2 = ? 2b=2c. The central node a0 also has a node capacity constraint (a0 ) = 1; other nodes have no capacity constraints. Notice that ? 2b=2c = 0 if is even, and so the middle portion of the network exists only for odd values of . In our discussion, a0 always is a transshipment node, while others can be either supply or demand nodes. The following lemma characterizes the admissible ow based on which nodes on the outer cycle a1 ; a2; a3; a4 are supply nodes.
a2 κ1 a1
κ2 κ2
κ1
κ1 a 0 κ2 κ2
a3
κ1
a4
Fig. 5. The diamond
network corresponding to the core of a cell. In the gure, 1 = b=2c and 2 = ? 2b=2c. The central node a0 has node capacity 1.
Lemma 4. The diamond network admits a ow for each of the following cases.
1. Exactly one node on the cycle, say a1 , is a supply node with (a1 ) . 2. Two adjacent nodes on the cycle, say a1 and a2 , are supply nodes with (a1)+ (a2 ) . 3. Two opposite nodes on the cycle, say a1 and a3 , are supply nodes with (a1 )+ (a3 ) 2 ? 2. 4. Three nodes on the cycle, say a1, a2, and a3, are supply nodes with (a1) + (a2 ) + (a3 ) . Proof. For convenience, we use a node capacity of
2 for a0 : the node a0 is reachable only when 2 = 1, so the unit capacity of a0 is functionally equivalent to a capacity of 2 . We apply the Max-Flow Min-Cut theorem. In Cases 1 and 4, it is easily seen that the minimum cut has capacity at most . In particular, in Case 1, the cut [fa1g; V ? fa1g] has capacity 21 + 2 = 2b=2c + ? 2b=2c = . Similarly, in Case 4, the cut [V ? fa4 g; fa4g] also has capacity . In Case 2, a minimumcapacity cut is [fa1; a2; a0g; fa3; a4; a0 g], with capacity 21 + 2 = 2b=2c + ? 2b=2c = . (Recall that (a0; a0 ) is the node capacity edge corresponding to a0.) Finally,in Case 3, a minimumcut is [fa1; a3; a0g; fa2; a4; a0 g]. The cut capacity is 41 +2 = 4b=2c + ? 2b=2c, which is 2 when is even, and 2 ? 1 when is odd. This completes the proof. 0
00
0
0
00
00
A via cell is modeled using the network shown in Figure 6. We call this a
network element . The nodes v1 ; v2; v3; v4 represent the four via sites; the central
diamond represents the core b of the cell; and the nodes u1 ; u2; u3; u4 act as connections between the core and the cell boundary. For ease of reference, we will often use the term connection nodes for the ui nodes, connection edges for the edges (ui ; ai), and boundary edges for the edges (vi ; uj ). The via nodes vi and the middle diamond node a0 have node capacity 1; the connection nodes ui have capacity each; all other nodes have no capacity constraint. Let N denote the network corresponding to the entire via grid. (See Figure 7.) We complete the network by adding two arti cial nodes s and d, called supply and demand nodes. We join each via location to d with a unit-capacity edge. We join s to each node on the boundary of the via grid. The capacity of the edge joining s to u is the number of \pins" on the portion of the boundary corresponding to u: if u is a via site, then the capacity is at most 1; otherwise, the capacity is the number of pins lying between the via site neighbors of u. Finally, we set (s) = jP j and (d) = ?jP j. (For example, in Figure 1, there are 9 nodes on the bottom row, of which ve are via sites. The capacities of the edges between these nodes and s are, in left to right order, 0; 0; 0; 3;1; 2; 0;0;0.) 1
v1
u2
v2
1
κ a2
1
u1
κ
1
κ
a0 a1
1
a3 a4
u3
1
κ v4
1
u4
1
v3
Fig. 6. Network corresponding to a via cell. Connection nodes ui have capacity ; via nodes vi have capacity one; the middle diamond node a0 has capacity one; all other nodes have no capacity constraint.
Informally, it is not hard to see that N correctly models the PCB: Each via site has four wire elements incident to it, which are modeled by the four (bidirectional) edges incident to its corresponding node in N ; unit node capacity ensures that at most one wire path runs through or sinks in a via. The core of a cell is represented by the diamond network, which can admit at most wires from any one side. Formally, Lemma 5 below proves that every matching M Let corresponds a ow inofNthe . pins and vias, and let be a ow in N . We M be a tomatching say that is consistent with M at a via node vi if there is a unit ow along an edge incident to vi if and only if there is a wire path in M incident to vi along that edge. We also say that is consistent with a cell c if (ui; ai) = fi , and (ai; ui) = gi, where fi and gi , for 1 i 4, are the number of wire elements entering and leaving the core of c through the edge ei . Finally, we say that is consistent with M if it is consistent with each cell and each via.
Fig. 7. Illustration for the network N . The unit capacity network in the middle of each diamond has been left out for clarity of the gure. The arrowhead in each diamond denotes the cyclic orientation of the cell associated with that network element. The reason for cell orientation is explained in Section 4. Lemma 5. Given a matching M, there is always a ow in N consistent with M. Proof. Given a matching M, we show how to set up a ow in N that is consistent with M. De ning a ow consistent with via nodes is easy: since at most one
wire enters and leaves vi , we assign ow value 1 to the associated edge in the network. To make consistent with cells, let us consider a cell c and its core b. Set (ui; ai) = fi ; for 1 i 4 (ai; ui) = gi ; for 1 i 4 P P Note that, by wire conservation, we have fi = gi . Except for the diamond nodes ai , all other nodes satisfy ow conservation, and all edges satisfy capacity constraints. In order to turn this partial ow into a valid ow in N , we now augment the ow in the diamond graph of each cell. Lemma 1 gives bounds on the total imbalance at the nodes ai , depending on the type of the cell. Lemma 4 shows that in each case, a ow can be set up within the diamond graph so that all the nodes are ow-conserving. The resulting ow is consistent with M at every via and in every cell. Finally, to show that the connection nodes also respect their capacity constraints, let us consider the total outbound ow on one such node, say, u1 . Let c and c denote the two adjacent cells sharing the side (v1 ; v4). Let f1 and f1 denote the number of wires entering the cores b and b , respectively, through the side (v1 ; v4). Thus, the total outbound ow at u1 equals f1 + f1 + j (u1; v1)j + j (u1; v4)j: 0
0
0
0
Now, observe that the side (v1 ; v4) of c has interior grid points (these are the grid points through which a wire must pass to enter the core on either side). Each wire corresponding to f1 or f1 consumes at least one of these grid points. 0
Further, the wires corresponding to (u1; v1) and (u1; v4 ) run along (v1 ; v4) and consume at least one of these grid points each. Thus, we have the following inequality: f1 + f1 + j (u1; v1)j + j (u1; v4 )j ; 0
which completes the proof.
4 Converting a Flow into a Wire Layout The preceding section has shown that, given a matching M, we can de ne a ow consistent with it. We now describe the converse step: to construct a matching consistent with a given ow in N . It turns out that we need to modify the ow values locally, while maintaining the total ow, in order to realize the layout. We call the modi ed ow tail-ordered , and explain it below. The tail-ordered
ow depends on a cyclic ordering of each cell, and so we begin by describing a method for orienting each cell so that the directions are consistent at common cell boundaries.
4.1 Cell Orientation Our method for converting a ow into a matching is a local method: it computes the embedding on a cell-by-cell basis. In order to ensure that the embeddings in di erent cells are globally compatible in that the wires on common cell boundaries line up properly, we adopt a cyclic ordering for the layout in each cell. Speci cally, we orient each cell c either clockwise or counterclockwise, which enforces a direction on each boundary edge of c. If an edge (a; b) is oriented from a to b, then our wiring layout pushes all wires on (a; b) to the b end. See Figure 8 for illustration. (Because pin positions are xed, we may need to introduce a small bu er zone between the pins and the boundary of the via rectangle to get the desired wire positions at the boundary.)
In order to orient the cells consistently, so that the direction enforced on an edge by its two neighboring cells is the same, we assign the orientations in a checkerboard fashion, alternating between clockwise and counterclockwise. The arrows in Figure 7 illustrate this ordering.
e2
e2 e3
e1
e1
e3
e4
e4
(a)
(b)
Fig. 8. (a) CW oriented cell. (b) CCW oriented cell.
4.2 Tail-Ordered Flow
Let us start with a brief and informal motivation for introducing the tail-ordered ow. Our layout algorithm will attempt to place wires at cell boundaries consistent with the direction of each boundary edge. Thus, for instance, if a cell c is clockwise oriented, then all wires entering or leaving e1 are pushed near the top of e1 . Now suppose ` of these wires leave the core b of c, and one of them heads towards the via v1 , while others enter the core of the neighboring cell c . In keeping with the placement rule determined by the cell orientation, the wire heading to v1 occupies the topmost two grid points|it emerges from the core b at the second grid point of e1 and then enters v1 . The remaining ` ? 1 wires use the third through (` + 1)st grid points to exit c and enter c . Unfortunately, c \expects" all the wires coming in from e1 to enter its core using the topmost ` ? 1 wires, and the one-unit shift causes problems for the layout algorithm. Roughly speaking, the trouble is caused by the wire that goes to the via site v1 at the head of e1 . On the other hand, if the last wire (at the bottom of e1 ) had gone to the via site v4 , then the remaining wires would match up properly along e1 . This motivates us to modify the ow so that ow along a boundary edge of a cell occurs only at the tail end of the edge. We are now ready to formalize this idea. Consider the network element associated with a via cell c, and assume that c is clockwise oriented. We say that c has a tail violation at the connection node u1 if either (v1; u1) and (u1; a1) are both positive, or (a1; u1) and (u1; v1) are both positive. (Symmetrically, if c is counterclockwise oriented, then a tail violation occurs if either (v4; u1) and (u1 ; a1) are both positive, or (a1; u1) and (u1; v4) are both positive.) We say that is tail-ordered in c if there is no violation at any of its connection nodes. If all cells are tail-ordered, then is tail-ordered in N . Figure 9 shows an example; the cell is clockwise oriented and there is a tail violation at u1; we update the ow values at bold edges, by an amount equal to the numbers shown next to edges, to correct the tail violation (cf. Lemma 6). The following lemma shows that it is always possible to convert a ow into a tail-ordered ow of the same value. 0
0
0
Lemma 6. Given an integer-valued canonical ow in N , one can always construct an equal-valued ow that is tail-ordered. 0
Proof. We argue that among all tail violations, there is always at least one that can be removed by a local ow modi cation. Suppose a tail violation occurs in a cell c. Without loss of generality, assume that c is clockwise oriented, and the connection node in violation is u1 . There are two cases, depending on the direction of ow along (v1 ; u1). Figure 9 shows both cases; the proof is quite symmetric for the two cases, so we consider only the rst. Therefore, let us assume that (v1 ; u1) = 1 and (u1; a1) > 0. The desired ow modi cation subtracts one unit of ow from (v1 ; u1) and (u1; a1), adds one to (v1 ; u2) and (u2; a2), then recomputes the ow in the diamond graph in the core of c. We show that this is always possible, unless it creates a capacity violation at u2, and in this case there exists another tail violation that can be corrected.
u2
v1
v2
u2
v1
+1
+1 −1
−1
a2
a2 u1
−1
a3
a1
u3
u1
a4
v4
v2
+1
+1
u4
−1
a3
a1
u3
a4
v3
v4
u4
v3
Fig. 9. Illustration for Lemma 6. The two cases depending on the direction of
ow along (v1 ; u1). The bold lines show the edges whose ows are updated; the changes are shown in bold letters next to the edge. The modi cation a ects the ow at four edges outside the central diamond subgraph of c. Since (v1 ; u1) and (u1; a1) are greater than zero, the updates at those edges decrease the ow and hence do not violate their capacity constraints. The unit node capacity at v1 means that (v1 ; u2) 0, so the update leaves (v1; u2) 1. By Lemma 1, we have (u1; a1)+ (u2; a2 ) before the update, which implies (u2; a2) ? 1. The update therefore leaves (u2; a2) , satisfying the edge capacity. The revised ows along the (ui ; ai) edges can be satis ed by a legal ow in the diamond subgraph. If (u2 ; a2) > 0 in the original ow, then we know that (u1; a1) + (u2; a2) . Since we decrease the rst term by one, and increase the second by one, the total remains the same; furthermore, since (u1; a1) > 0
initially, the new value of (u2; a2) is at most , and so a valid ow is possible by Lemma 4. If, on the other hand, (a2 ; u2) > 0, we decrease both the incoming and the outgoing ow for the diamond subgraph by one each, and it is easy to see that a legal ow is possible in the diamond graph. The ow modi cation a ects three nodes with node capacity constraints. The modi cation decreases the ow out of u1, and either leaves the ow out of v1 unchanged or reduces it to zero (depending on whether (u2 ; v1) is 0 or 1 before modi cation). If (u2; a2) < 0 and/or (u2; v1) = 1, then the modi cation does not increase the ow out of u2. However, if (u2; a2) 0 and (u2; v1) = 0 originally, then the modi cation increases the ow out of u2 by one unit. If the
ow out of u2 is already , this would cause a violation of the node's capacity. In the problematic situation, (u2; a2) = ? 1, (u2; v1) = 0, and either (u2 ; v2) = 1 or the ow from u2 to the diamond node above it (call it a ) is 1. In the former case ( (u2 ; v2) = 1), we have (a ; u2) = , and the cell above c (call it c ) has a tail violation at u2; in the latter case (u2; a ) = 1, and so we must have = 1 and (v2; u2) = 1, which also creates a tail violation at u2 in c. If the tail violation at u2 in c cannot be removed by local ow modi cation, the same argument shows that there is a tail violation in the cell to the right of c at its u1 node. That is, the node in the northeast neighbor cell of c whose position corresponds to u1 has a tail violation. Because the cell con guration is nite, we can repeat the argument in this cell, proceeding diagonally up and to the right until we nd a tail violation that can be removed. Eliminating a tail violation does not create any new tail violations. Thus we can eliminate all tail violations one at a time by repeated local modi cations. 0
0
0
0
0
0
0
The following lemma shows that a tail-ordered ow eliminates ow along boundary edges at the head of an edge (as directed under cell orientation) unless there is no \cross ow."
Lemma 7. Let be a tail-ordered ow in N , and consider a connection node
u, lying between two via nodes v and v . Assume that the cell orientation directs the side (v ; v) from v to v. Then a nonzero ow between the node pair (u; v) implies that the ow between u and its two diamond graph neighbors is zero. 0
0
0
Proof. Assume, without loss of generality, that (v ; v) is vertical, with v below v; 0
0
the cell on the right is c; the cell on the left is c ; and the connection neighbors of u are a in c and a in c . By hypothesis, maxf (u; v); (v; u)g > 0. First, suppose that (u; v) > 0. Then if either (a; u) > 0 or (a ; u) > 0, we get a tail violation condition at u (in c in the former case and in c in the latter case). Thus, if there is any ow between u and a or u and a , it is directed away from u. But if (u; a) > 0 or (u; a ) > 0, then at least two units of ow are outgoing at u, and at most one incoming (from v ), which contradicts ow conservation at u. A completely symmetric argument works when (v; u) > 0. This completes the proof. 0
0
0
0
0
0
0
0
We are now ready to describe our layout algorithm. We assume in the following that is a tail-ordered canonical maximum ow in N . We will show how to compute a layout of the matching associated with . The most complex part of the layout algorithm is the wiring inside a core. Computing a layout in a core corresponds to solving the problem only for the subgraph spanned by the connection nodes and the diamond graphs, leaving out the vias and boundary edges. Once the core wiring is computed, it will be easy to augment it with the remaining wires.
4.3 Wire Layout in a Core Consider the network element corresponding to a cell c. We are interested in 's restriction to the subgraph spanned by c's diamond and the connection nodes| this subgraph corresponds to the core b of the cell c. We will show how to compute a layout consistent with the ow in this subgraph. First, since is anti-symmetric, each connection edge (ui ; ai) has ow in only one direction. Thus, we can use the direction of ow in (ui ; ai) to label the corresponding core boundary edge. In order to avoid unnecessary new notation, let us use the same symbols for the corresponding edges of b and c. Thus, the boundary of b has e1 ; e2; e3 ; e4 in clockwise order, starting from the left edge. We say that the edge ei is surplus if (ui ; ai) > 0; it is de cit if (ai ; ui) < 0; and neutral otherwise. The core b can now be classi ed as Type I, II, or III, depending on which of its edges are surplus, exactly as in Section 2. (It should be clear now that no wiring needs to be done in b if all edges of b are neutral.) The following three lemmas show how to do the layout in each of these cases, under the further restriction that wiring must be consistent with the cell orientation of c. The core b inherits the orientation of its cell c|each of the boundary edges of b has the same direction as the corresponding edge of c. In the layout of b, all wires along an edge are pushed toward the head of the directed edge. We call such a wiring orientation preserving . Without loss of generality, we assume in the following that the core is clockwise oriented; the construction is completely symmetric for the other case. The three lemmas below describe the construction for Type I, II and III cores. In each case, we will use the following common convention: ` denotes the wire count for a surplus edge; j denotes the wire count for a de cit edge; the subscript on ` and j is the same as the corresponding edge ei . (Thus, if e1 is surplus, then the number of wires entering through e1 is denoted by `1 , and if e1 is de cit, the number of leaving wires is denoted by j1.) Our rst lemmahandles the case of a Type I cell; without loss of generality, we assume that e1 is the surplus edge, and others are neutral or de cit; a symmetric proof works if one edge is de cit and others are surplus. In this extended abstract, we present only a proof sketch of the third case, which is also the most complex. Lemma 8. Let b be the core of a cell, and suppose that `1 wires enter b through e1 and ji leave through ei , for i = 2; 3; 4, where `1 = j2 + j3 + j4 . Then an orientation preserving wiring exists for b.
Proof. In the clockwise embedding, the wires are pushed to the top along e1 ,
and to the right, bottom, and left along e2 ; e3 and e4 , respectively. We connect the topmost j2 wires of e1 to e2 , the next j3 to e3 , and the remaining to e4 . Figure 10 shows this construction. To see that this embedding is always possible, we consider the rectangular areas of b claimed by each of three wire groups. Connections between e1 and e2 all lie within a rectangular block of size j2 ,
ush with the top edge of b. The connections between e1 and e3 occupy an Lshaped block that is the union of a rectangular block of size j3 on the top and a rectangular block of size ( ? j2 ? j3 ) j3 on the right. This leaves out a rectangular block of size at least ( ? j2 ? j3) ( ? j3 ), anchored at the bottom-left corner of b. Since j4 ? j2 ? j3 , this block is suciently large to accommodate j4 wires between e1 and e4 . This completes the proof.
j
j
2
2
l1
l1
j
j
3
j
3
j
4
4
(a)
(b)
Fig. 10. Layout in a Type I core. (a) shows the wiring, (b) shows the rectangles used in the proof. Lemma 9. Let b be the core of a cell, and suppose that `1 and `2 wires enter b through e1 and e2 , respectively, and j3 and j4 wires leave through e3 and e4 , respectively, where `1 +`2 = j3 +j4 . Then an orientation preserving wiring exists for b.
Proof. First suppose that `1 j4 . We match the `1 wires from e1 with the
leftmost `1 wires on e4 . Match the remaining wires on e4 with the leftmost wires on e2 . The leftover `1 +`2 ? j4 (= j3 ) wires of e2 are matched with the wires on e3 . Figure 11 (a) illustrates this construction. To see why this embedding is always feasible, note that the connections between e1 and e4 lie within a rectangular box of size `1 , ush with e1 . The connections between e2 and e3 lie within a
rectangular box of size j3 , ush with e3 . This leaves out a rectangular block of size at least ( ? j3 ? `1 ) in the middle. Now, since ? j3 ? `1 j4 ? `1 , the middle block is sucient for routing j4 ? `1 wires from e2 to e4 . Figure 11 (b) shows these rectangular regions. A similar construction works for the case when `1 > j4 , and is shown in Figure 11 (c). We match the bottom j4 wires of e1 with those on e4 , the top `2 wires of e3 with e2 , and nally the leftover `1 ? j4 wires from e1 with the ones on e3 . The proof is similar to the rst case, and we skip the details.
l2
l2
l1
l2 l1
l1
j
4
3
3
3
j
j
j
j
j
4
(a)
4
(b)
(c)
Fig. 11. Layout in Type II. Fig. (a) shows the wiring for the case when `1 j4, and Fig. (b) shows the rectangles used in the proof. Fig. (c) shows the construction of the case when `1 > j4 . Finally, we consider a Type III core.
Lemma 10. Let b be the core of a cell, and suppose that `1 and `3 wires enter
b through e1 and e3 , respectively, and j2 and j4 wires leave through e2 and e4 , respectively, where `1 +`3 = j2 +j4 , and `1 +`3 is at most 2 when is even and at most 2 ? 1 otherwise. Then an orientation preserving wiring exists for b. Proof. Let a column denote a vertical grid line in the wire grid. For a column
y in b, let ny denote the number of wires exiting through e2 and e4 left of (and inclusive of) y. Consider the leftmost column y such that ny `1 . Let j21 and j41 denote the number of wires exiting through e2 and e4 , respectively, to the left of y. Let j22 = j2 ? j21 and j42 = j4 ? j41. If ny = `1 , then we match the bottommost j41 wires of e1 to the leftmost j41 wires on e4 , and the topmost j21 wires of e1 to the leftmost j21 wires on e2 . A
similar layout is done for the wires to the right of y. Since `1 = ny = j21 + j41, it is easy to see that this layout is always possible. If ny > `1 , then we must have ny = `1 + 1; this follows from the fact that the wire count can change by at most two per column. In this case, we match the bottommost j41 ? 1 wires of e1 to the leftmost j41 ? 1 wires on e4 , and the topmost j21 ? 1 wires of e1 to the leftmost j21 ? 1 wires on e2 . A similar layout is done for the wires to the right of y. Now, we are left with at most one wire each on e1 and e3 , and they need to be joined to the wires exiting e2 and e4 along the column y. Let us denote these wires on e1 and e3 by w1 and w3. We join w1 to the leftmost j21 th wire on e2 , and w3 to the j41th wire on e4 . The only nontrivial step in this construction is to show that the wire paths for w1 and w3 do not intersect, since they both use a common column y. We will show that w1 runs along a higher row than w3, and so they remain disjoint on y. See Figure 12 for illustration. Due to the clockwise orientation of the cell, we have j41 j21, and similarly, j22 j42. Since j41 ? 1 wires from e1 are joined to e4 , while j21 ? 1 wires are top joined to e2 , it follows that the row index of w1 is at most `21 , where the ` 3 + 1, row of b has index 1. Similarly, the row index of w is at least ? 3 2 which follows because at least `23 topmost wires of e3 are joined to e2 . Thus, to ensure that w1 is above w3, we need to show that
`1 < ? `3 + 1 ; 2 2
or equivalently,
`1 + `3 : 2 2
(1)
When is even, Inequality 1 follows from the fact that `1; `3 . When is odd, we have the additional constraint that `1 + `3 2 ? 1, and the left-hand side is upper-bounded by
+ ? 1 = l m + j k = ; 2 2 2 2
l m
which completes the proof.
4.4 Wiring a Cell
Armed with the results of the preceding two subsections, completing the wiring for each cell now becomes easy. Once the core wiring is complete, the only remaining wires are the ones that correspond to ow along boundary edges of a network element. It suces to consider a side of a cell, and show how the wires from its two neighboring cores can be augmented with the boundary wires. Figure 13 shows an illustrative example. Let us consider two neighboring cells c and c that share the vertical side (v1; v4 ), and the connection node u1 . Consider rst the case in which the only ow through u1 comes from/goes to v1 and v4 . No wires enter the cores of c and c from e1 and, if the ow through u1 is nonzero, a single wire connects v1 to v4 along e1 . 0
0
v1
a3
u1
j
2
w1 l1 l3 w3 j
Fig. 12.
4
Layout in Type III. The column y is highlighted with a dotted line. In this example, `1 = 19, `3 = 11, j21 = 6, j22 = 8, j41 = 14, j42 = 2. y
v1
a1
c
c
v4
v4
Fig. 13. Extending the core wiring to cells. The gure on the left shows the
network picture; the gure on the right shows the geometric picture. In this gure, we have x1 = 4, x2 = 3, and (u1; v4) = 1.
In the second case, at least one of (u1; a1) and (u1; a3) is nonzero, where a1 and a3 are the connection neighbors of u1 in c and c , respectively. Without loss of generality, assume that c is oriented clockwise, and thus e1 is directed from v4 to v1 ; clearly, c is counterclockwise oriented. Figure 13 illustrates the construction. We can also assume that x1 = (a1; u1) 0; the other case is symmetric up to a re ection across the line determined by e1 . By Lemma 7, there is no ow between u1 and v1, meaning j (u1; v1)j = 0. Thus, we have the equality x1 = x2 + (u1 ; v4), where x2 = (u1; a3). By anti-symmetry, (u1 ; v4) = ? (v4 ; u1). By the results 0
0
0
0
0
of Section 4.3, we may assume that the cores of c and c have been wired in an orientation preserving manner. Hence there are x1 wires leaving along the topmost x1 wire elements of the core of c, and x2 wires entering along the topmost x2 wire elements of the core of c . If x1 = x2 +1, then the topmost x2 wires from c's core enter c and the last one is joined to v4 along e1 . (This case is shown in Figure 13.) If x1 = x2 ? 1, then all the wires from c enter c , and the last wire joins v4 to the bottommost wire entering c through e1 . If x1 = x2 , then the wires are joined in the obvious way. This completes our description of how a tail-ordered ow can be realized as a wiring. Since the sources and sinks in the
ow correspond to pins and vias, the resulting wiring is a matching of P and V . 0
0
0
0
0
5 Algorithm and Complexity Analysis All the pieces of our breakout routing algorithm are in place now, and the algorithm can be described as follows at a high level of modularity:
Algorithm 1. Construct the network N corresponding to the via grid, with each via location represented by a sink node, and each pin location represented by a source node. Make each sink node a demand node with value one, and make each source node a supply node with value equal to the number of pins it represents. Assign capacities to nodes and edges as described in Section 3.2. 2. Run a ow algorithm to compute a maximum ow between the source and sink nodes [2]. 3. Modify the ow, if necessary, to make it tail-ordered. 4. Use the tail-ordered ow to compute a wire layout consistent with in each cell. 5. Post-process to remove unnecessary bends in the wire layout [4, 3]. Step 5 requires a bit of explanation. The wire layout our algorithm produces may have more bends than necessary. Reducing the number of bends is desirable for manufacturing reasons; to do this we treat our wire layout as a rubber-band sketch |a speci cation of the routing homotopy|and apply the algorithms of Maley [4] or Dai, Kong, and Sato [3] to the sketch to nish the routing with fewer bends. The time complexity of our method is dominated by the network ow algorithm in Step 2. Our network structure means that even simple, classical network
ow algorithms are likely to perform well in practice. Each node in N has constant degree, so the number of edges is asymptotically the same as the number of nodes. The maximum ow is m, the number of pins, and so even the FordFulkerson algorithm runs in O(mjNj) time [2, p. 587]. The network size is likely to be closely related to n, the number of vias, and so Ford-Fulkerson runs in O(mn) time.
In practice, if pins are not located on all sides of the rectangle of via sites, they are located preferentially on the long sides. This means that the average wire length in the solution tends to be short, on the order of the via rectangle width. Dinic's algorithm [6, p. 102], which operates in phases and nds many paths in parallel in each phase, is a good candidate for use on N . A simple implementation p runs in time proportional to the total length of all paths, or roughly O(m n) in our network. More sophisticated algorithms may perform even better.
6 Future Directions We are presently implementing our algorithm to evaluate its performance in practice. The initial implementation will use Ford-Fulkerson to solve the network
ow problem, but we will experiment with other ow algorithms once the rest of the implementation is stable. We would like to incorporate variable-width wires into our framework. Power and ground wires are often wider than signal wires; likewise, certain applications require two or more wires to be routed together as if they were a single wire. Our network model assumes that all wires are the same width. Overcoming this limitation would extend the applicability of our method. The most interesting and important extension to our technique involves improving the modeling of routing capacity. Our diamond network models a square of unobstructed routing area by a constant-size graph. Similar modeling is central to global routing, a subproblem of PCB routing in which the approximate layout of all wires is planned simultaneously. However, in global routing the routing cells may be partially obstructed, and they need not be square. Relaxing the squareness restriction appears to be a relatively minor step, but modeling partial blockage in our graph structure remains very dicult. Still, such an extension would be very useful in practice, and so it is worth pursuing.
References 1. W.-T. Chan and F. Y. L. Chin. Ecient algorithms for nding disjoint paths in grids. In Proceedings of ACM-SIAM Symposium on Discrete Algorithms, pages 454{463, 1997. 2. T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. The MIT Press, Cambridge, Mass., 1990. 3. W. W.-M. Dai, R. Kong, and M. Sato. Routability of a rubber-band sketch. In Proceedings of 28th IEEE/ACM Design Automation Conf., pages 45{48, 1991. 4. F. M. Maley. Single-Layer Wire Routing and Compaction. The MIT Press, Cambridge, Mass., 1990. 5. V. P. Roychowdhury, J. Bruck, and T. Kailath. Ecient algorithms for recon guration in VLSI/WSI arrays. IEEE Transactions on Computers, pages 480{489, 1990.
6. R. E. Tarjan. Data Structures and Network Algorithms, volume 44 of CBMS-NSF Regional Conference Series in Applied Mathematics. Society for Industrial Applied Mathematics, 1983. 7. M.-F. Yu and W. W.-M. Dai. Single-layer fanout routing and routability analysis for ball grid arrays. In Proceedings of IEEE/ACM International Conf. on CAD, pages 581{586, 1995. 8. M.-F. Yu, J. Darnauer, and W. W.-M. Dai. Interchangeable pin routing with application to package layout. In Proceedings of IEEE/ACM International Conf. on CAD, pages 668{673, 1996.
This article was processed using the LATEX macro package with LLNCS style
