Effect of Annealing on the Structural and Electrical ...

Electrochemical and Solid-State Letters, 11 共12兲 G62-G65 共2008兲

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1099-0062/2008/11共12兲/G62/4/$23.00 © The Electrochemical Society

Effect of Annealing on the Structural and Electrical Properties of High-k Sm2O3 Dielectrics Tung-Ming Pan,*,z Chun-Chin Huang, Shi-Xian You, and Chih-Cheng Yeh Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan In this paper, the authors report a high-k samarium oxide 共Sm2O3兲 dielectric grown on the silicon substrate by reactive sputtering. We find that the Sm2O3 gate dielectric after annealing at 700°C exhibits excellent electrical properties such as small equivalent oxide thickness, gate leakage current, frequency dispersion, and stress-induced leakage current. This indicates that annealing at 700°C treatment can prevent the interfacial layer formation, improve the surface roughness, and passivate a large amount of trapped charge at defect sites. © 2008 The Electrochemical Society. 关DOI: 10.1149/1.2990226兴 All rights reserved. Manuscript submitted August 19, 2008; revised manuscript received September 8, 2008. Published October 2, 2008.

* Electrochemical Society Active Member. z

E-mail: [email protected]

LCR meter. The electrical properties of MOS capacitors were measured by using the HP 4156C semiconductor parameter analyzer. In order to explore the morphology of the as-deposited film and its thermal stability during annealing for Sm2O3 film, hightemperature XRD measurements were conducted as shown in Fig. 1. The as-deposited films show featureless patterns, indicating poor crystallinity, whereas the films after RTA at different temperatures exhibit sharp peaks and are polycrystalline. Films annealed at 600°C show a weak 共400兲 reflection, whereas those deposited at 800°C exhibit a strong 共444兲 reflection. Apart from the strong 共444兲, 共622兲, 共400兲, and 共433兲 peaks, minor ones are present in the films. Thus, our study shows that the texture of the Sm2O3 film on silicon is strongly dependent on the RTA condition. PDA causes the crystallization of amorphous films, but annealing does not alter the texture of the films that are amorphous as deposited. XRD further reveals that PDA leads to the removal of the less-intense peaks in textured films and in increased grain size. Figure 2 shows the AFM image of Sm2O3 films after RTA at different temperatures. The surface roughness of the Sm2O3 film clearly decreases with increasing PDA temperature, except for 800°C. This may be attributed to the consolidation of the grains due to the infusion of mobility to the constituents of the film through the annealing process. The sample annealed at 800°C has a slightly

Sm2O3 (622) Sm2O3 (433)

o

800 C

Intensity (a.u.)

High-k dielectric materials are proposed to replace SiO2 as insulator films in complementary metal-oxide-semiconductor 共CMOS兲 devices.1 For this purpose, besides a high-k value, a large conduction band offset 共CBO兲 and thermodynamic stability on Si are needed. Hf-based oxide is one of the most promising high-k dielectrics due to their high permittivity and large CBO.2 Unfortunately, the low-k interface between the silicon and the high-k dielectric has limited its utility in future CMOS technology.3 Rare-earth oxides and silicates are high-k materials that generally satisfy these requirements.4,5 Samarium oxide 共Sm2O3兲 is an attractive substitute for SiO2 in CMOS devices because it possesses a high dielectric constant, predictable thermodynamic stability on Si, and has a proper CBO with Si.6-8 Dakhel explored the optical and dielectric properties of amorphous monoclinic phase Sm2O3 thin films.9 In addition, good insulating properties and k of around 30 were reported for Sm2O3 films grown by pulsed laser deposition10 and by plasma-assisted molecular beam epitaxy.11 Rapid thermal annealing 共RTA兲 has been explored for ultrashallow junction formation and is used in silicide formation for contact metallization in nanoscale devices.12 RTA has also been used for postdeposition annealing 共PDA兲 in high-k materials with the purpose of improving the deposited film properties in order to achieve better electrical characteristics.13 The effect of annealing on high-k Sm2O3 dielectric properties is still not known. In this work, we report the effect of RTA annealing on the structural and electrical properties of high-k Sm2O3 dielectrics. A TiN/Sm2O3 /Si/Al capacitor structure was fabricated and measured. Structural, morphological, and chemical modifications upon annealing were investigated combining X-ray diffraction 共XRD兲, atomic force microscopy 共AFM兲 and X-ray photoelectron spectroscopy 共XPS兲. In addition, the effects of annealing on the electrical properties are discussed. Metal-oxide-semiconductor 共MOS兲 capacitors were fabricated on p-type 共100兲-oriented silicon wafers with a resistivity of 1–10 ⍀ cm. The samples were cleaned by a standard RCA method and dipped in dilute HF for 1 min to remove the native oxide from the surface prior to the dielectric film deposition. An ⬃7 nm Sm2O3 film was deposited on Si substrate by reactive sputtering from a Sm target at a power of 150 W with a base pressure of 1 ⫻ 10−6 Torr. The PDA was done in N2 ambient for 30 s at different annealing temperatures by RTA. After the deposition of a 500 Å TiN film, MOS devices having gate areas of 3.14 ⫻ 10−4 cm2 were defined using photolithography and wet etching. Finally, a 4000 Å thickness Al film was deposited on the back-side contact of the Si wafer. XRD was carried out to investigate the composition of this metal oxide. AFM was used to analyze the surface roughness of the Sm2O3 films. XPS was performed to identify the electronic and bonding structures of Sm2O3 dielectric films. The equivalent oxide thickness 共CET兲 of Sm2O3 films was determined by a Hewlett-Packard 共HP兲 4284A

Sm2O3 (400)

Sm2O3 (444)

o

700 C

o

600 C

As-dep

20

30

40

2θ (degree)

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Figure 1. XRD of Sm2O3 film after RTA at various temperatures in N2 ambient for 30 s.

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Figure 2. 共Color online兲 AFM morphology of Sm2O3 dielectrics annealed at various temperatures.

Sm2O3 reference position 共1084.3 eV兲,14 which indicates the large formation of Sm silicate. The O 1s signals in Fig. 3b further help in realizing layered structures. In three sets of spectra, each fitting peak is assumed to follow the general shape of the Gaussian function. The low-energy state, peak located at 530.4 eV, is assigned to O in Sm2O3.14 The intermediate-energy state, peak located at 531.8 eV, is attributed to interfacial O atoms in nonstoichiometric silicate 共SmSixOy兲. The high-energy state, peak located at 533 eV, is assigned to O in SiO2.15 The as-deposited sample appears to be composed mainly of Sm2O3, Sm-silicate, and SiO2. The Sm-silicate and SiO2 are due to intermixing of the Sm2O3 film and Si substrate. The intensity of the O 1s peak at 533 eV 共corresponding to SiO2兲 increased with increasing RTA temperature, whereas the intensity of the O 1s peak at 530.4 eV 共corresponding to Sm2O3兲 decreased with

larger surface roughness than that annealed at 700°C. This may be due to the formation of silicate and the SiO2 layer containing Sm and O at the growth surface of the metal oxide. The structural and compositional changes of the Sm2O3 film according to the annealing temperature were investigated using XPS. The XPS results showing the variations in the Sm2O3 films as a function of annealing temperature are discussed. Figures 3a-c show the variations in XPS peak intensity and positions of the Sm 3d, O 1s, and Si 2p for Sm2O3 film as a function of the RTA temperature, respectively. Figure 3a shows the variation in the Sm 3d peak as a function of the annealing temperature. The Sm 3d peak position showed almost no shift toward higher binding energy at annealing temperatures up to 700°C, and there was a sudden increase in the shift after annealing at 800°C. The Sm 3d peak for PDA at 800°C is shifted to higher binding energy by ⬃1.2 eV compared with the

Sm2O3

(b)

Sm 3d5/2 o

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600 C

Sm-silicate o

700 C

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600 C

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Binding energy (eV)

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800 C

800 C

Intensity (a. u.)

Intensity (a. u.)

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Si-sub Si 2p

SiO2

o

800 C

700 C

(c)

O 1s

Sm2O3

SiO2

Sm-silicate

Intensity (a. u.)

(a)

o

700 C

Figure 3. XPS results of 共a兲 Sm 3d, 共b兲 O 1s, and 共c兲 Si 2p in Sm2O3 film after annealing at various temperatures. o

600 C

As-dep

As-dep 534

532

530

528

Binding energy (eV)

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98

96

Binding energy (eV)



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100 kHz 500 kHz 1 MHz

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increasing RTA temperature. The SiO2 layer grew monotonically at the film/substrate interface due to the oxygen diffusion toward the interface from the crystal defect and nonstoichiometry structure with the annealing temperature. After annealing at 800°C, the Si 2p corelevel XPS spectra were composed of 3 different component peaks at binding energies of 99.3, 101.9, and 103.1 eV, as shown in Fig. 3c. The Si 2p peak position at 99.3 eV was assigned to the Si substrate, whereas the Si 2p peak located at 103.1 eV mainly corresponds to the SiO2.15 The Si 2p peak position at 101.9 eV is attributed to Sm-silicate. In addition, the single strong peak at 103.1 eV after annealing at 800°C is observed, indicating the formation of amorphous silica. It is obvious that the Si 2p peak at 103.1 eV remains at a smaller value after annealing at 700°C. As a result, there is almost no silicon oxide formed at the interface with the silicon substrate. Figure 4 shows the capacitance vs gate voltage curves measured at frequency of 100 kHz for Sm2O3 gate dielectrics annealed at different temperatures. The CETs of the as-deposited film and samples annealed at 600, 700, and 800°C are 4.86, 3.18, 2.75, and 3.22 nm, respectively. The dielectric constant values are 5.62, 8.58, 9.93, and 8.48 for the as-deposited film and samples annealed at 600, 700, and 800°C, respectively. The MOS capacitor after RTA at 800°C results in a reduction of the capacitance at the accumulation regime, suggesting the growth of a lower-k interfacial layer and Sm-silicate film. These results suggest that thermodynamically it is more favorable for the growth of silica compared to Sm2O3 at this temperature. Sm2O3 dielectric deposited on Si substrate after PDA at 700°C exhibits a higher capacitance value and a lower flatband voltage 共VFB兲 than other RTA temperatures. The decrease in the amorphous silica and silicate layer at the Sm2O3 /Si interface may be due to the suppression of oxygen diffusion at elevated temperatures in vacuum environments. The VFB shift is attributed to a significant number of positive charges into the oxide. In addition, the interface state of film annealed at 700°C is calculated to be as low as 1.68 ⫻ 1011 cm−2 eV−1 by using Terman’s method.16 The capacitance– voltage 共C-V兲 characteristics of Sm2O3 dielectrics after RTA at 700°C measured at different frequencies are illustrated in the inset of Fig. 4. The small frequency dispersion in accumulation of Sm2O3 dielectric might be due to the effect of series resistance,17 which mostly affects the high frequency of 1 MHz curves lowering the accumulation capacitance. Figure 5 displays the gate leakage current as a function of gate voltage across the Sm2O3 dielectric after PDA at various temperatures. It is evident that the sample annealed at 800°C exhibits a

-5

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-3

-2

-1

0

Gate voltage (V) Figure 5. Gate current density as a function of gate voltage for Sm2O3 gate dielectrics after RTA at various temperatures.

smaller leakage current density in the low-voltage than other annealing temperatures. This phenomenon is due to the increase in CET, which is consistent with the results of C-V curves. The reason for the increase in CET is the increase of the interfacial layer between Sm2O3 film and Si substrate after a high RTA treatment. At a gate voltage of −1 V, the leakage current density of the Sm2O3 gate dielectric after RTA at 700°C is only 64.3 nA/cm2. Figure 6 shows the stress-induced leakage current 共SILC兲 on ⌬J/J共t = 0兲关where ⌬J = J共t兲 − J共t = 0兲兴 curves as a function of stress time for Sm2O3 gate dielectrics after RTA at various temperatures. It has been reported that SILC arises from trap-assisted tunneling through bulk neutral defects generated in the gate dielectric layer during electrical stress.18 The charge-trapping properties were measured under a constant voltage stress of −5 V in accumulation mode. It is found that the Sm2O3 dielectric annealed at 700°C exhibit the best SILC characteristics, indicating negligible charge trapping in the Sm2O3 gate film.

150

As-dep o 600 C o 700 C o 800 C

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SILC (%)

Figure 4. C-V curves of Sm2O3 gate dielectrics annealed at various temperatures. The inset shows the C-V frequency dependence of Sm2O3 gate dielectrics annealed at 700°C.

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VG=-5 V

60 30 0

-30 0

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Figure 6. SILC characteristics as a function of gate voltage for Sm2O3 gate dielectrics after RTA at various temperatures.


Electrochemical and Solid-State Letters, 11 共12兲 G62-G65 共2008兲 In conclusion, we reported a high-k Sm2O3 gate dielectric fabricated by reactive sputtering. The MOS capacitor with Sm2O3 gate dielectric annealed at 700°C and performed under N2 ambient shows a thinner CET, a lower leakage current, a smaller frequency dispersion, and better SILC characteristics, indicating the absence of the amorphous interfacial layer formation, low surface roughness, passivation of trapped charges at defect sites, and the reduction of interface traps. Acknowledgment This work was supported by the National Science Council 共NSC兲 of China under contract no. NSC-96-2221-E-182-045. Chang Gung University assisted in meeting the publication costs of this article.

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