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IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 6, JUNE 2002
Effects of High- Gate Dielectric Materials on Metal and Silicon Gate Workfunctions Yee-Chia Yeo, Student Member, IEEE, Pushkar Ranade, Student Member, IEEE, Tsu-Jae King, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE
Abstract—The dependence of metal and polysilicon gate workfunctions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high- dielectrics differ appreciably from their values on SiO2 or in a vacuum. We also show the first application of the interface dipole theory on the metal–dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO2 , Si3 N4 , ZrO2 , and HfO2 are extracted. In addition, we also explain the weaker dependence of n and p polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high- gate dielectrics.
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Index Terms—CMOSFETs, highfaces, metal gate, workfunction.
dielectric materials, inter-
I. INTRODUCTION
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ONSIDERABLE challenges are encountered when bulk CMOS devices are scaled into the sub-100 nm regime for higher integrated circuit (IC) density and performance. The problems of polysilicon (poly-Si) gate depletion, high gate resistance, high gate tunneling leakage current, and boron penetration into the channel region become more severe as the channel length and gate-oxide thickness are aggressively reduced. Therefore, there is immense interest in metal gates and alternative gate dielectrics with high permittivity [1]. Metal gates with workfunctions near the conduction and valence band edges of Si are desired for the N- and P-MOSFETs, respectively. The workfunctions of metals on high- dielectrics have been observed to differ from their values in vacuum [2], [3] with the discrepancy dependent on the gate dielectric used. It is not clear whether a similar effect exists for poly-Si gates. Therefore, an accurate understanding of the top interface of the gate dielectric, i.e., the metal–dielectric or the poly-Si–dielectric interface (Fig. 1) is important to achieving precise control of gate workfunctions and threshold voltages in transistors with high- gate dielectrics. In this paper, we investigate the dependence of metal and poly-Si gate workfunctions on the gate dielectric. We employ the interface dipole theory [4], [10] to explain the experimental observations and extract important Manuscript received February 5, 2002. This work was supported by the SRC/SEMATECH Center for Front-End Processing under Contract 98-BC-616. Y.-C. Yeo was supported by NUS, Singapore, and the 2001 IEEE Electron Devices Society Graduate Student Fellowship Award. The review of this letter was arranged by Editor K. De Meyer. The authors are with the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720 USA (e-mail:
[email protected]). Publisher Item Identifier S 0741-3106(02)05184-4.
Fig. 1. (Left) Energy band diagram and (right) charging character of interface states for the (a) metal–dielectric and (b) silicon–dielectric interfaces. In general, the character of interface states becomes more acceptor (donor)-like toward the conduction (valence) band, as indicated by the solid (dashed) line. Filling an acceptor-like interface state results in a negative charge, while leaving a donor-like interface state empty results in a positive charge. Hence, the shaded area represents the total negative charge on the dielectric side, while the gray region represents the total positive charge on the dielectric side.
material parameters that characterize the gate dielectrics. Implications and challenges for the design of advanced gate stacks are discussed. II. METAL–DIELECTRIC INTERFACE When a metal and a semiconductor or a dielectric form an interface, charge transfer generally occurs across the interface. The Schottky model, where band alignment is determined solely from the workfunction of the metal in vacuum and the
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YEO et al.: EFFECTS OF HIGH- GATE DIELECTRIC MATERIALS
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Fig. 2. (a) Effective workfunction of metals on various dielectrics versus their workfunctions in vacuum showing good agreement between experimental data (symbols) and the interface dipole theory (lines). Data are updated from those reported in [3]. (b) Selection of metals to obtain effective workfunctions of 4.05 V and 5.17 V for five different gate dielectrics. The data points are calculated from our experimentally extracted 8 and S . The trend lines are shown in dashes.
semiconductor electron affinity on an absolute energy scale, is not usually obeyed by experimental data due to the presence of intrinsic interface states. The existence of intrinsic states at the metal–semiconductor or metal–dielectric interface has been established from self-consistent pseudo-potential calculations of the electronic structure of materials interfaces [5]. These , and mostly states are predominantly donor-like close to [Fig. 1(a)]. The energy level in the acceptor-like near band-gap at which the dominant character of the interface states changes from donor-like to acceptor-like is called the charge [4], [10]. Charging of these interface neutrality level states creates a dipole that tends to drive the band lineup toward a position that would give zero dipole charge. Fig. 1(a) is above illustrates the case where the metal Fermi level , creating the charge neutrality level in the dielectric a dipole that is charged negatively on the dielectric side. This goes interface dipole drives the band alignment so that , and the effective metal workfunction toward therefore differs from the vacuum metal workfunction . This workfunction change is proportional to the difference and or equivalently, the difference between and . Thus, between is given by (1) is a slope parameter that accounts for dielectric where screening and depends on the electronic component of the [6]. With larger dielectric screening, dielectric constant the slope parameter becomes smaller, and a higher degree is experienced. Experimental data of pinning to (symbols) in Fig. 2(a) illustrates the varying degrees of pinning of the of metal workfunctions toward the respective
TABLE I COMPARISON OF THEORETICAL AND EXPERIMENTAL SLOPE PARAMETERS AND CHARGE NEUTRALITY LEVELS FOR SEVERAL GATE DIELECTRICS
gate dielectrics considered. A fit of (1) to the experimental data not only reveals the good agreement between the interface dipole theory and measured data, but also yields the first and for dielectrics like ZrO and extraction of HfO . This was not performed in our previous work [3]. The extracted parameters are compared with theoretical values in Table I, and they provide useful guidelines on the choice of gate materials for future CMOS technology. Fig. 2(a) also of 4.05 V (5.17 V) on indicates that in order to obtain a high- dielectric for NMOS (PMOS), a metal with an even has to be used. This is examined more smaller (larger) is plotted as explicitly in Fig. 2(b), where the required for five different dielectrics. For the PMOS a function of gate, inert metals must be used and this makes gate etching particularly challenging. Reactive metals have to be used as the NMOS gate, and this might introduce extrinsic interface states
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IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 6, JUNE 2002
In (2), is the workfunction of n or p poly-Si in vacuum, is the charge-neutrality level in Si. Using (1) and and (2), the theoretical effective workfunctions of n poly-Si V) and a metal with V on different ( high- dielectrics are compared in Fig. 3. It shows that the n poly-Si gate are less vulnerable to Fermi-pinning compared to V) the metal gate. This is also true for p poly-Si ( V. A similar analysis shows and a metal with that poly-silicon–germanium gates behave in the same way as poly-Si gates.
IV. CONCLUSION Fig. 3. Metal Fermi levels tend to be pinned to E of the dielectric. This tendency increases with " . Poly-Si or poly-SiGe gates do not suffer appreciably from this effect.
due to defects arising from an interfacial reaction. Although the thermodynamics of a possible interfacial reaction and creation of defect states is not the intended focus of this work, it should be noted that extrinsic defects states usually have a lower density compared to the intrinsic interface states unless there is significant interfacial reaction. Defect-related extrinsic interface states should be distinguished from intrinsic interface states, and in the context of the interface dipole theory, any large deviation of the measured effective workfunctions from the linear trend in Fig. 2(a) may be attributed to the existence of extrinsic interface states. We have carefully eliminated data which shows evidence of an interfacial reaction. To avoid using an inert or reactive metal gate, a possible solution is to introduce at least a monolayer of SiO at the metal–dielectric interface to achieve a large . III. POLY-SILICON–DIELECTRIC INTERFACE Recently, it has been shown that poly-Si on HfO and SiO have about the same workfunctions [9]. We explain this observation using the interface dipole theory, which has been remarkably successful in explaining the band lineups for metal–metal, metal–semiconductor, as well as semiconductor–semiconductor junctions all within a single unified approach [4], [10]. The important characteristic that differentiates the poly-Si–dielectric interface from the metal–dielectric interface is the absence of interface states at energies where the band-gaps of both materials overlap [Fig. 1(b)]. The band lineup is thus driven by a smaller dipole charge. Mathematically, the effective workfuncis determined by the aligntion of the n or p poly-Si and ment of (2)
To achieve the desired dual-metal gate workfunctions on high- gate dielectrics, candidate metals need to have vacuum workfunctions smaller (larger) than 4.05 V (5.17 V) for the NMOS (PMOS). A monolayer of SiO at the interface could relax this requirement. The effective workfunctions of n and p poly-Si or poly-SiGe gates show less dependence on the gate dielectric material.
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