Efficient Logic Controller Design Grzegorz Borowik and Mariusz Rawski
Grzegorz Łabiak and Arkadiusz Bukowiec
Warsaw University of Technology Institute of Telecommunications Nowowiejska 15/19, 00-665 Warsaw Email:
[email protected] [email protected]
University of Zielona G´ora Institute of Computer Engineering and Electronics Podg´orna 50, 65-246 Zielona G´ora Email:
[email protected] [email protected]
Abstract—Logic controller is a digital device used for automation of electromechanical processes, such as control of machinery on factory assembly line or lighting fixtures. This paper presents the method for designing a logic controller. We implement it using reprogrammable structure equipped with Embedded Memory Blocks, e.g. CPLD or FPGA. We find that specification of the controller with appropriate statechart diagram and further synthesis as equivalent Finite State Machine yields encouraging results: the number of programmable resources has been reduced approximately by 85%. Result of the research is illustrated with synthesis of practical controllers, where hardware resource consumption is presented. It shows the usefulness of the approach.1 Index Terms—logic controller, statechart diagram, finite state machine, decomposition, embedded memory block
I. I NTRODUCTION Logic controller is an electronic digital device implemented as digital circuit. It is used for automation of electromechanical processes, such as control of machinery on factory assembly line, lighting fixtures, traffic control system, or even automation of system whose role is to maintain an ongoing interaction with their environment, i.e. controlling mechanical devices such as a train, a plane, or ongoing processes such as a biochemical reactor. Logic controllers can find their application in different areas of biotechnology either. In [19] a technology of smart hand prosthesis control based on myoelectric signals is presented. The key elements of this design are arithmetic and control units. Bioreactor controller is the focus of the paper [11]. This article provides an overview of current and emerging bioreactor control strategies based on unstructured dynamic models of cell growth and product formation. Nevertheless, process control plays a limited role in the biotechnology industry as compared to the petroleum and chemical industries. This demand for process modeling and control is increasing, however, due to the expiration of pharmaceutical patents and the continuing development of global competition in biochemical manufacturing. The lack of online sensors that allow real-time monitoring of the process state has been an obstruction to biochemical process control. Recent advances in 1 This work was partly supported by the Ministry of Science and Higher Education of Poland – research grant no. N516 418538 for years 2010–2012.
978-1-4244-6952-9/10/$26.00 ©2010 IEEE
Henry Selvaraj University of Nevada, Las Vegas Department of Electrical and Computer Engineering 4505 S. Maryland Parkway Las Vegas, Nevada 89154-4026A Email:
[email protected]
Statechart (mathematical model)
FSM (KISS format)
ROM-based decomposition
Fig. 1.
Behaviour description Synthesis
Architectural decomposition
General idea of FSM-based logic controller design.
biochemical measurement technology, however, have enabled the development of advanced process control systems [11]. In this paper, we propose the method for designing a logic controller in reprogrammable structure. Such a structure offers ability to update the functionality, partial reconfiguration and the low non-recurring engineering costs relative to an ASIC design. The method starts with formal specification of the logic controller behavior. To specify a complex nature of a controller we have chosen a statechart diagram [10]. An important advantage of this specification is the possibility of detecting all reachable deadlocks [13], since any failure in a safety-critical system may cause injury or death to human beings. Having graphically specified behavior, it is subsequently converted into mathematical model [15]. The mathematical model of statechart can be transformed formally into equivalent finite state machine (FSM) [14]. Finally, such a logic controller in FSM form can be implemented in various architectures [1], [3], [6] (Fig. 1). Summarizing, formal description is transformed into Boolean equations in a suitable form for the given technology. II. S TATECHART D IAGRAM S PECIFIES C HEMICAL R EACTOR A statechart diagram is a state-based graphical scheme. It is enhanced with concurrency, hierarchy and broadcasting mechanism. The statechart diagram usually describes a complex system. However, it requires that the system described is composed of a finite number of states [10].
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Fig. 2.
Schematic diagram of chemical reactor.
c) The statechart diagram can certainly specify reactive system behavior. As an example of practical application, the schematic diagram of a chemical reactor and appropriate statechart diagram of its logic controller are presented in Fig. 2 and 3, respectively. The working of the reactor is as follows. Initially, the reacting substances are kept in containers SV1 and SV2 (Fig. 2), and the emptied wagon waits in its initial position on the far right position (Fig. 3, state WaitingForStart). Then, the operator starts the proces with the signal x0. The pump y1 and the pump y2 make that liquid substrates from containers SV1, SV2 are being measured out in scales MV1 and MV2, respectively (state Preparations). During this, the wagon is coming back to its far left position. After the substrates are measured out, the main reaction starts (state Reaction). Next, scales fill main container R with agents (state AgentDispensing) and agitator A starts rotating (state StirringControl). After filling up the main container, the product of the reactor is poured to the wagon (state EmptyingReactor). Then, the wagon goes to empty (states WagonRight and EmptyingWagon). Rounded rectangles in the statechart diagram, called states, correspond to activities in the controlled object (in this case chemical reactor). In general, states can be in sequential relationship (OR state), or in concurrent relationship (AND states). Then, these states make sequential or parallel automaton. States can be simple or compound. The latter state can be nested with other compound or simple. In the diagram (Fig. 3), the AND states are separated with a dashed line. States are connected with transitions with predicates imposed on it. Predicates must be met to transform activity between states connected with an arc. III. L OGIC I NTERPRETATION AND T RANSFORMATION The issue of hardware synthesis of statecharts is not solved ultimately. There are many implementation schemes depended on target technology. First, published in [8], consists transformation of the statechart into the set of hierarchically linked FSMs traditionally implemented. In [9], a special encoding of the statechart configurations targeted at PLA structures is presented. The drawback of this method is that diagram expresses
START
Fig. 4.
i
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Simple diagram (a), its waveform (b) and equivalent FSM (c).
transitions between simple states only. In [17], Drusinsky enhanced the coding scheme by introducing a prefix-encoding. However, the common drawbacks of the presented methods is the lack of support for history attributes and broadcast mechanism. Other implementation methods using HDL and based on ASIP are presented in [12] and [4], respectively. To synthesis statechart-base logic controller it is necessary to precisely define its behavior in terms of logic values. In Fig. 4 a simply diagram and its waveform illustrate the main dynamic features. Logic value 1 means activity of a state or presence of an event, and value 0 means their absence. When transition t1 is fired (T = 350) event t1 is broadcast and becomes available to the system at next instant of discrete time (T = 450). The activity moves from state START to state ACTION, where entry action (keyword entry) and doactivity (ongoing activity, keyword do) are performed (events entr and d are broadcast). Now, transition t2 becomes enabled. Its source state is active and predicate imposed on it (event t1) is met. So, at the instant of time T = 450, the system transforms activity to the state STOP, performs exit action (keyword exit, event ext) and triggers event t2, which do not affect any other transition. The step is finished. Summarizing, dynamic characteristics of hardware implementation are as follows: • system is synchronous, • system reacts to the set of available events through transition executions, • generated events are accessible to the system during next tick of the clock. Noticeably, statechart-based controller can be perceived as a finite state machine of a Moore type. Transformation of statechart diagram into FSM model involves building equivalent Moore-type automaton using statechart elements which
WaitingForStart t1: x0
Process
Substrates WagonReturn
Preparations FillingMV1 do / y1
WagonLeft do / y9
FillingMV2 do / y2
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t7: !x2 t5: x5*x6
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EmptyingReactor do / y5 t14: !x6
t15: !x6
t11 WagonRight do / y8 t12: x8 EmptyingWagon do / y6
Fig. 3.
Statechart diagram of chemical reactor.
for external observer behaves just the way statechart does; members of the sets are explicitly enumerated and functions are given symbolically in tabular form, i.e. KISS format transition table [20]. Classic Moore automatom is defined as a quintuple hX, S, Y, δ, λi, where X is a set of input signals, S is a set of states, Y is a set of output signals, δ is a transition function and λ is an output function dependent only on states. The set of equivalent FSM input signals X is the set of statechart input events, the set of FSM output signals Y is the set of statechart events visible to the environment. The set S of equivalent FSM states is a set of statechart global states which are constructed from local activities: states, actions (entry, do, exit) and events broadcast when transition is fired (e.g. t1 and t2 in diagram from Fig. 4). Transition function δ is a function which maps current global state into next global state depending on the set of currently accessible events, hence transition function δ is a vector of Boolean functions. Each component of the vector is bound up with either a state or action or transition event [15]. The exact algorithm of generating an equivalent FSM in KISS format is presented in [14]. IV. ROM- BASED S YNTHESIS One of the main goals of the synthesis is not only technological implementation of logic controller but also optimization of
hardware resources consumption. It is particularly important when the design is intended for novel programmable structure containing LUT-based cells and embedded memory blocks. The other factor of vital importance is Boolean minimization strategy. Authors’ proposition is to apply the idea of functional decomposition, i.e. a structure with address modifier (Fig. 5b), which is best suited for the FSMs in KISS format from previous section [3], [18]. A limited size of embedded memory blocks available in FPGAs is the main reason behind the application of this structure. The implementation of an FSM shown in Fig. 5b can be seen as a serial decomposition of the memory block included in the structure of Fig. 5a into two blocks: an address modifier and a memory block of smaller capacity than required for the realization of the structure in Fig. 5a. As a result, sequential circuits requiring large-capacity ROM memories (and thus not implementable in the architecture of Fig. 5a) can be implemented using a memory block with a smaller number of inputs and an additional combinational logic block – the address modifier. Then, the size of the required memory [3] is equal M = 2w · (r + p). (1) The address modifier can be synthesized with advanced algorithms of functional decomposition, applied until recently
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