Efficient Symbol Reliability Based Decoding for QCNB-LDPC Codes Leixin Zhou∗, Jin Sha∗, Yun Chen†, Chuan Zhang‡, Zhongfeng Wang§
∗ School
of Electronic Science and Engineering, Nanjing University, Nanjing, China Email:
[email protected];
[email protected] † State Key Lab. of ASIC and System, Fudan University, Shanghai, China Email:
[email protected] ‡ National Mobile Communications Research Laboratory, School of Information Science and Engineering Southeast University, Nanjing, China Email:
[email protected] § Broadcom Corporation, 5300 California Avenue, Irvine, CA 92617, USA Email:
[email protected]
Abstract— As an extension of binary low-density parity-check (LDPC) codes, non-binary LDPC (NB-LDPC) codes show significantly better performance when the code length is moderate or small. Recently, enhanced iterative hard reliability based (EIHRB) decoding algorithm is proposed to reduce the computation complexity. However, the EIHRB algorithm suffers a lot from significant performance degradation when the column weight is small. In this paper, a symbol reliability based (SRB) decoding algorithm, which also performs well when the column weight is low, is proposed for NB-LDPC decoding to improve the decoding performance. With the same maximum iteration number, around 0.38 dB extra coding gain is achieved. Furthermore, the corresponding efficient decoder architecture is proposed. Comparison results have shown that the proposed SRB algorithm can not only achieve good coding gain, but the cost for hardware implementation is reasonable.
weight. Although the algorithm proposed in [7] can improve the performance of reliability based algorithm, its decoding latency suffers a lot from its serial-processing nature and therefore not applicable for real-life applications. In this paper a novel parallel symbol reliability based (SRB) algorithm is proposed, which can carry out the decoding process in a parallel manner. Moreover, the decoding performance is much better than the algorithm proposed in [8]. In addition, the corresponding decoder is also demonstrated. The remainder of this paper is organized as follows. First, the proposed SRB algorithm is demonstrated in Section II. Then the simulation results and the proposed decoder architecture are shown in Section III and section IV, respectively. At last, a conclusion is drawn in Section V.
I. I NTRODUCTION
II. P ROPOSED ALGORITHM
B
INARY low-density parity-check (LDPC) codes, rediscovered by Gallager in 1962 [1], have shown great capabilities in approaching Shannon capacity. Non-binay LDPC (NB-LDPC) codes, which can be treated as an extension of their binary counterparts in finite fields with order higher than 2, were first investigated by Davey and MacKay [2]. Having the capabilities of correcting symbol-wise errors, NBLDPC codes have demonstrated advantages over binary ones in recovering channel impairments [3]. However, the coding gain introduced by NB-LDPC codes comes along with drastic increase of the decoding complexity. The optimal but most complex decoding algorithm is the FFT-based sum-product algorithm (SPA) proposed in [2]. To this end, some alternatives which can achieve better tradeoff between decoding complexity and performance, have been proposed in [4] [5]. Some other algorithms, which are based on symbol-reliability and majority logic [6] [7] [8], have been proposed as well. These algorithms can significantly lower the decoding complexity at the penalty of considerable performance losses, especially for the codes of small column This work was jointly supported by the National Nature Science Foundation of China under Grant No. 61176024 and 61006018, Research Fund for the Doctoral Program of Higher Education of China under Grant No. 20100091120048, the Priority Academic Program Development of Jiangsu Higher Education Institutions and Open Project of State Key Laboratory of ASIC & System (Fudan University) 12KF006.
978-1-4799-3432-4/14/$31.00 ©2014 IEEE
An NB-LDPC code C is defined by an M × N parity-check matrix H, whose elements hi, n are in the Galois field of size 2q , denoted as GF (2q ). The row and column weights of H are denoted by dc and dv , respectively. For quasi-cyclic codes, we can divide the parity check matrix into G groups, each group containing a row of sub-matrix (q−1)×(q−1), which is either a zero matrix or a cyclic-shifted identity matrix and therefore we can make sure that rows in one group have only one nonzero elements in one column. Based on this, we can extend the algorithm in [7] to a partial parallel one. The pseudo-code for the proposed algorithm is shown in Algorithm 1. Each symbol αl (0 ≤ l ≤ q − 2) of the codeword is transmitted as a sequence of q bits tuple (bl, 0 , bl,1 , ... bl, q−1 ) over a binary-input channel with BPSK modulation. The sequence sent is denoted as X. And the received sequence is denoted as Y = (y0 , y1 , ... yN−1 ), where each yn = (yn,0 , yn,1 , ... yn, q−1 ) is noisy sample. The non-binary hard decision based on each received vector yn is denoted by zn . In the proposed algorithm, the channel reliability measure is Ln (αl ) = μ bl, i ln(P(bl, i = 1)/P(bl, i = 0)) (1) , 0≤i
