Electrical Perofrmance of Electronic Packaging, 2004 ... - IEEE Xplore

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Custom circuits used , data recovery methods, signal integrity design and the system verification using buses. register based diagnostics and EYE margin ...
IBM POWER5 bus designs for on and off module connections D. Dreps, . F. Ferraiolo, A. Haridass, R Reese, J. Schiff,B. Tmong IBM Corporation 11400 Burnet Road, Austin, TX 78758 Tel (512) 838-9713, FAX: (512) 838-1717 Email: drepsdm, Rank, anandh, robreesejschitT,[email protected]

Abstract This p a p will overview the interface choices made for the 1: 1 on-module buses and the 2: 1 off-mcdule buses. Custom circuits used , data recovery methods, signal integrity design and the system verification using register based diagnostics and EYE margin mapping.

Introduction Power 5 bus design was targeted IO support at least 2.5Gigahertz processor speeds. The 1:l on-module buses are limited to 4 cm module interconnects that run up to 2.5Gigabit. The 2:1 of module buses nm through up to 4 VHDM connectors and 25 inches of FR4 trace. These buses run up to 1.25Gigabit The buses all use the same source synchronous data recovev methods with ZX finer step sizes on the 1:l busses and tighter wire skew and shielding speciiications. The YO signaling is single ended voltage mode Io “ize per pin bandwidth The 1: 1 buses consist of 15 data bits and 1clk per group. The 2: 1 buses consists of nominally 32 bits and a differential clock pair. Since each system has 10’s of thousands co~ecIions,the methodology of pre-pd simulation will be explained. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping will be explained.

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Driver design consisted of 35 ohm drivers for the on-module that swing rail-&. The modules are Glass Ceramic and are not bandwidth limiting. The receiver is an “aggressive clamp” that clamps the swing at 100-200 mV below the Vdd rail and above gmund respectively. The combination of overdriving into the clamp results in lower IS1 at about 4 ! the power dissipation of conventional split termination. The off-module buses typically use the similar aggressive clamp designs in conjunction with drivers that can be programmed to 20/40 pre-emphasis mode or either 20 or 40 ohm mode via mode registers.(Circuit topology figures of the driver/link/clamp and clamp are shown below) This can allow the same YO cell to be used for short module-module links and long multi connector backplane links. The pre-emphasis mode with the aggressive clamp services links with interconne* losses of up to 4 dB at 750 m e w e m . The docks are run differentally. In order to keep pinaunt low the vrefcan be derived from the differential clock pair and then be windaged to the point where the eye is widest. This feature allows for a somewhat automatic compensation when power supplies are moved and allows vertical eye mapping acmss the bits of the bus The windage adjust is under register control. Figure 1 driver/link/clamp Figure 2 aggressive clamp schematic

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Data recovery methods Most buses are either 4 to 8 Bytes per direction. Each logical bus is made up of gmups of bundles. For both interface types the clock is launched at the Same instant as the data. The edge that is used to launch the data is then shifted to the center of the bit via a state machine controlled delay line. We call this the Interface Alignment procedure. @U')We have chosen to have the clock launch with the data edge to track out local silicon vdd i n d u d skew variation. At power up and at mer defined intervals the bus goes into IAP mode. During this timea special alignment pattern is sent from the driver to the receiver. 1oooOOOO. This aligns the receive FIFO to put the leading one into the proper position across the l o g i d bus structure that requires synchronous operation. The guardbands are continuouSy monitored The minimum threshold value after LAP is written into a history register. This register can be scanned out. The guataband d u e is also compared against a programmed threshold value. If the guardband value equals the threshold valne a flag is set indicating the threshold has been met. The threshold value and error flag are SCOM registers. Guardbands provide real time eye opening small trace anay provides history of eye opening. Figure 3 , Data is sampled 3 times, early, functional and late. Error free d a t a valid w i n d o w

Signal threshold voltage is transferred across the interface via the differential clocks. A programmable threshold o f h t on Rx side is used to stress noise margins. Thus the guardban& can be monitored per bus or per bit with vrefwindage. Also built into the interface design is a Random Data Test mode exists where the interfaw can be fenced and a a high activity pattern can be transmitted across the interface while monitoring the guardbands.5000 data patterns are sent across the interface requires only an operating clock from chips, this allows per bit BER isolation. Figure5 Vref

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Signal Integrity Design Approach The approach taken was to take the minimum and maxi" net oonfigurations draw the schematic models o f nets in the same cadence environment that one designs the driver and recciVa with full cadence. extracled models. This allows for transistor level optimization without abstraction This approach requires a cadence library of package symbols. The result is powerspice model libmy which is linked into cadence so on a single schematic the U 0 &per can iterate with a complete net in graphical form. There are no limitation in the &ce framewotk with respea to aggressors. Below is are typical cadence schematic symbols tbat one can use to assemble a end to end net. An example of a simple endend net is shown below. SpeciGc models can be generated with various tools such as HFSS and ported into powerspice compatible libraries.

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Measured Results Below is an example of the probeless measurement methods that we used to characterize each bit of every bus in a system. The vref is adjusted and the flag2 - flag1 is a measure of the jitter for the alignment pattern. Special scripts are written that extract the bus margins. Below as you can see there is a “bowl effect‘then as you move The vrefstep size. here is 30mV. In addition to this we can extract data bit skew, away from the optimum d. clodr arrival, jitter , eye opening , and isolate open and short bits. After initial characterization derivative server designs we the probeless c h a ’” tion for system characterizationand guardbanding.

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