Electrical Properties of Atomic-Layer-Deposited Thin Gadolinium

Journal of The Electrochemical Society, 154 共10兲 G207-G214 共2007兲

G207

0013-4651/2007/154共10兲/G207/8/$20.00 © The Electrochemical Society

Electrical Properties of Atomic-Layer-Deposited Thin Gadolinium Oxide High-k Gate Dielectrics S. Dueñas,a,z H. Castán,a H. García,a A. Gómez,a L. Bailón,a K. Kukli,b,c T. Hatanpää,c J. Lu,d M. Ritala,c,* and M. Leskeläc a

Departamento de Electricidad y Electrónica, E.T.S.I. Telecomunicación, Universidad de Valladolid, 47011 Valladolid, Spain Institute of Experimental Physics and Technology, University of Tartu, 51010 Tartu, Estonia c Department of Chemistry, University of Helsinki, FIN-00014 Helsinki, Finland d Ångström Microstructure Laboratory, Department of Engineering Sciences, Uppsala University, SE 75121 Uppsala, Sweden b

Amorphous or cubic Gd2O3 thin films were grown from tris共2,3-dimethyl-2-butoxy兲gadolinium共III兲, Gd关OC共CH3兲2CH共CH3兲2兴3, and H2O precursors at 350°C. As-deposited Gd2O3 films grown on etched 共H-terminated兲 Si共100兲 exhibited better leakage current-voltage characteristics as well as lower flatband voltage shift than films grown on SiO2 /Si substrates. Interface trap densities were lower in Al/Gd2O3/hydrofluoric acid 共HF兲-etched Si samples annealed at rather high temperatures. © 2007 The Electrochemical Society. 关DOI: 10.1149/1.2761845兴 All rights reserved. Manuscript submitted February 20, 2007; revised manuscript received May 25, 2007. Available electronically August 2, 2007.

The progressive scaling of integrated-circuit technologies stimulates intense study on very thin dielectric layers on semiconductors, in order to increase the functionality of microelectronic devices. However, in conventional SiO2-based technologies, as the effective gate-oxide thickness scales toward 1 nm there is excessive leakage current due to direct tunnelling. On account of this limitation, SiO2 must be replaced with a suitable high-dielectric-constant 共k兲 material, the higher k allowing a thicker gate dielectric that reduces tunnelling while maintaining the electric fields necessary for controlling the channel current. In the search for proper candidates of alternative dielectrics, the rare-earth 共RE兲 oxides are attractive based on energy considerations, i.e., RE metals are much more reactive with oxygen than other transition metals1 and have a high conduction band offset.2 RE oxides have received considerable attention as alternative gate-oxide materials.3,4 In particular, gadolinium oxide Gd2O3 is an attractive material among the RE oxides because cubic Gd2O3 has one of the closest lattice matches to silicon. Thin films of Gd2O3 have been proposed for gate-dielectric applications5,6 because of its dielectric constant 共near 16兲 as well as its large bandgap 共5.3 eV兲, thermodynamical stability, and chemical stability in contact with silicon. For gate-oxide applications in the complementary metal-oxidesemiconductor 共CMOS兲 devices for the sub-100 nm generation of silicon technology, the dielectrics should form high-quality interfaces with Si with low interfacial state density, Dit, and little interfacial roughness. Studies related to GaAs-based devices have demonstrated7,8 that Gd2O3 epitaxial thin films grown by ultrahigh vacuum vapor deposition forms an excellent insulating barrier with low Dit, and that leads to GaAs-based MOS field-effect transistor 共MOSFET兲 devices. In recent years, studies on electrical properties of Gd2O3 thin films on silicon have gained increasing interest.9-13 Before Gd2O3 can be considered as a viable dielectric material for future electronic devices, much more work must be done in order to understand the leakage conduction mechanisms as well as to control the interfacial structure. Thin films of gadolinium oxide have been synthesized using several techniques such as electron-beam evaporation 共EBE兲,5,6,12 chemical vapor deposition 共CVD兲,14 low-pressure metallorganic chemical vapor deposition 共LP-MOCVD兲,10 reactive radio frequency 共rf兲 sputtering,11 molecular beam epitaxy 共MBE兲,15 and atomic layer deposition 共ALD兲.14,16

* Electrochemical Society Active Member. z

E-mail: [email protected]

In this paper, electrical characterization results of gadolinium oxide films atomic-layer-deposited on n-type silicon from a novel precursor are presented. The techniques used were current-voltage 共I-V兲, capacitance-voltage 共C-V兲, deep-level transient spectroscopy 共DLTS兲, conductance transients 共G-t兲, and constant-capacitance flatband voltage transients 共VFB-t兲. Experimental Gadolinium oxide films were grown in a hot-wall horizontal flow-type ALD reactor F12017 at 350°C from tris共2,3-dimethyl-2butoxy兲gadolinium共III兲, Gd关OC共CH3兲2CH共CH3兲2兴3, and H2O. The gadolinium precursor was evaporated at 195°C. The cycle times were 0.5 s for all pulses and purge periods. The films were grown to different thicknesses by applying 50, 100, 150, or 250 growth cycles. Some samples were directly deposited on hydrofluoric acid 共HF兲-etched 具100典 oriented n-silicon 共14 ⍀ cm兲, and others were fabricated on RCA-cleaned Si with chemically grown 0.9–1.2 nm thick SiO2 film. Some samples were annealed after deposition and before metallization in oxygen 共99.999%兲 atmosphere at 750°C, 1 atm, for 5 min. The thicknesses of the films were evaluated from X-ray reflection patterns measured with a Bruker D8 Advance X-ray diffractometer. The film structure was determined by the same diffractometer in grazing incidence mode 共incidence angle 1°兲. Film composition was determined by time-of-flight elastic recoil detection analysis 共TOF-ERDA兲 on reference films of higher thickness 共⬎50 nm兲, using either 53 MeV 127I10+ 共measured in Helsinki, Finland兲 or 16 MeV 35Cl7+ or 16 MeV 63Cu7+ 共measured in Leuven, Belgium兲 projectile ion beams. Transmission electron microscopy 共TEM兲 was applied for imaging the cross section of four representative samples with gadolinium oxide as-deposited and in annealed states. The high-resolution TEM images were obtained using a field-emission gun Technai F30 ST operating at 300 kV. The electrical measurements were carried out on Al/Gd2O3 /n-Si/Al and Al/Gd2O3 /SiO2 /n-Si/Al capacitors. Aluminum dot electrodes with an area of 0.204 mm2 were E-beam evaporated on top of the dielectric layers through a shadow mask. To form nearly ohmic contacts to silicon substrates, the back sides of the wafers were etched in HF and metallized by evaporating a 100 nm thick Al layer. In order to record the electrical parameters at several temperatures varying between 77 K and room temperature, samples were first cooled in darkness from room temperature to 77 K at 0 bias in an Oxford DM1710 cryostat. An Oxford ITC 502 controller was used to monitor the temperature during the measurements. The I-V curves were measured with a Keithley 6517A programmable electrometer in the stair sweep voltage mode while the voltage step used

G208


was 5 mV. The C-V measurements were carried out with the assistance of a Boonton 72B capacitance meter and a Keithley 617 programmable electrometer. The capacimeter makes measurements of shunt capacitance by applying a 1 MHz and 15 mV-level ac signal test. Voltage bias consists of 50 mV steps. The capacitance measurements are made 10 s after the bias-voltage step is applied in order to prevent transient instabilities in the capacitance values. Interfacial state densities were obtained by saturating pulse DLTS between 77 and 300 K.18,19 The bias voltage was chosen for each sample so that the capacitor was just at the limit between depletion and weak inversion. A 10 ms wide pulse high enough to drive the capacitors into accumulation was applied in order to fill all interface traps. Information on the traps was obtained by analyzing the capacitance transient that results as the traps empty, i.e., return to equilibrium. This technique is adequate to separate the fast contributions of interface states from the slow ones corresponding to defects in the dielectric bulk, because DLTS is time sensitive and allows one to distinguish contributions with different time constants. The interface trap distribution Dit corresponding to the upper half of the forbidden gap 共EC to midgap兲 was deduced from DLTS measurements by means of the expressions reported elsewhere.19 Lowtemperature transients provide information about interface states located near the conduction bandedge, whereas high-temperature transients correspond to the emission of those located very near the midgap. For DLTS measurements we used a 1 MHz Boonton 72B capacitance meter and a HP54501 digital oscilloscope to record the complete capacitance transients. A Keithley 617 programmable electrometer was used together with a HP214B pulse generator to introduce the quiescent bias and the filling pulse, respectively. DLTS technique provides the energetic distribution of interfacial states. However, according to the disorder-induce gap states 共DIGS兲 model proposed by He et al.,20 interface states are distributed not only in energy but also in space. In the spatial dimension, the regions of distorted local bonds extend on both sides of the interface, resulting in disordered regions in the semiconductor and in the insulator. The spatial extension of the disordered semiconductor region is very narrow, typically one or several monolayers, whereas that of the disordered insulator region reaches several tens of angstroms. The shape of the DIGS distribution is exponentially decaying away from the interface into the insulator.21 As from DLTS measurements the interface width cannot be derived, and in order to get a more complete electrical characterization, it becomes suitable to carry out conductance transient measurements.22 From these conductance transients it is possible to obtain the DIGS state density as a function of the spatial distance to the interface and of the energy position.23 The experimental setup of the conductance transient technique consists of an HP 33120A arbitrary wave-form generator to apply the bias pulses, an EG&G 5206 two-phase lock-in analyzer to measure the conductance, and an HP 54501A digital oscilloscope to record the complete conductance transient. Finally, flatband voltage transients at temperatures between 77 and 300 K have been measured by recording the gate voltage while keeping the capacitance constant at the initial flatband condition.24 Samples were kept under no external stress conditions: zero electric field in the substrate, darkness conditions and no external charge injection. Under these conditions, the only mechanism for defect trapping or detrapping is thermal activation by means of phonons. So, this kind of measurement allows us to obtain the energy of soft-optical phonons in the insulator. To obtain the flatband voltage transients, a feedback system that varies the applied gate voltage accordingly to keep the capacitance at its flatband voltage value has been implemented. A Keithley 6517A working as programmable bias source and a 1 MHz Boonton 72B capacitance meter were used.

Figure 1. TEM images of Gd2O3 films with nominal thickness 2.2 nm on HF-etched Si in as-deposited 共upper left panel兲 and annealed 共upper right panel兲 states, and films with thickness 8.1 nm on SiO2 /Si in as-deposited 共lower left panel兲 and annealed 共lower right panel兲 states.

cycles 共growth rate 0.026 nm/cycle兲. The composition profiling revealed that the films contained 37 ± 2 atom % gadolinium and 51 ± 2 atom % oxygen. Thus, the O-to-Gd ratio was close to 1.4 and the films could be considered as oxygen deficient. In addition, the presence of residual hydrogen and carbon was detected. The contents of H and C were 1.0 ± 0.5 and 0.6 ± 0.3 atom %, respectively. TEM studies 共Fig. 1兲 revealed the formation of continuous oxide films without particular grain growth. The interfacial layer was clearly visible, and in the case of SiO2 /Si substrate the thickness of SiO2 was retained. The interfacial SiO2 layer thickness did not increase noticeably upon annealing. At the same time, in the case of films grown onto HF-etched silicon, the interfacial layer thickness increased during annealing, although the exact composition of the interface layers remained open. Crystal growth was not noticeably promoted by the annealing procedure. The Gd2O3 films tended to crystallize in quite early stages of the growth at 350°C 共Fig. 2兲. The critical crystallization thickness appeared to be around 10 nm. In the films with thickness higher than 10 nm, cubic Gd2O3 was formed. Reflections from other phases

Results and Discussion Structure and composition of the films.— TOF-ERDA measurements were carried out on a 65 nm thick Gd2O3 film for the sake of convenience. The film was grown at 350°C using 2500 deposition

Figure 2. Gd2O3 film structures represented by XRD patterns taken from the films with different thicknesses and on HF-etched 共Si–H兲 or SiO2-covered Si 共SiO2 /Si兲 substrates indicated by labels. The upmost pattern represents a reference well-crystallized film with relatively higher thickness.


G209

Figure 3. 共a兲 Current 共I兲 against effective voltage 共VG-VFB兲 curves measured at several temperatures between 77 and 300 K corresponding to Al/Gd2O3 /n-Si MIS devices with 2.2 nm thick Gd2O3, 共b兲 effective voltage 共VG-VFB兲 values corresponding to 2.5 mA/cm2 current density as a function of temperature for different samples described by labels, 共c兲 temperature dependence of the current measured at constant voltage, and 共d兲 current-electric field dependency corresponding to the Al/Gd2O3 /SiO2 /n-Si sample with as-deposited 8.5 nm thick Gd2O3 film.

were not detected in the samples of this series. Annealing at 750°C in O2 under 1 atm pressure for 5 min did not noticeably change the film structure 共Fig. 2兲. Electrical measurements.— Figure 3 shows current measurement results at several temperatures between 77 and 300 K. As the electron encountered different barriers for gate injection and substrate injection, I-V plots were markedly asymmetrical. The leakage current was higher at positive bias than at negative bias, because the charge conduction was controlled by the metal/oxide interface instead of by the silicon/oxide interface.25 Also, a saturation of the current in inversion 共negative bias兲 was produced due to the exhausting of the minority carriers injected from the substrate.26 So, we only present here the results obtained under positive bias as the best indicator of film quality, as it has been done by several authors.27,28 As-deposited Al/Gd2O3 /HF-etched-n-Si, 750°C annealed Al/Gd2O3 /HF-etched-n-Si, and as-deposited Al/Gd2O3 /SiO2 /n-Si samples, all of them containing 2.2 nm thick Gd2O3, are compared in Fig. 3a. Effective voltage 共VG-VFB兲 values instead of VG values are displayed to take into account the different C-V behavior of each sample. It seems clear that the as-deposited Al/Gd2O3 /HF-etched-n-Si sample exhibits the best I-V characteris-

tics, with an effective conduction onset of about 2.70 V at 77 K. This onset decreases as temperature increases, reaching 2.35 V at room temperature. The annealed sample displays much poorer characteristics, the effective conduction onset being 1.50 V at 77 K and 1.45 V at room temperature. The unannealed sample in which Gd2O3 has been deposited onto oxidized silicon has an intermediate behavior. Also, the conduction threshold voltage is higher at 300 K than at 77 K. Moreover, conduction onset initially decreases from 77 to 235 K, as expected, but from 250 K this onset progressively increases. This means that there exists some temperature-activated mechanism, probably related to the SiO2 film, which progressively blocks the current through these thin films above 250 K. This effect was not observed either in thicker samples or in 2.2 nm thick oxide films deposited on HF-etched substrates. One tentative explanation for the differences in the conduction onset and behavior of the thinnest dielectric stack of silicon oxide is the existence of thermally activated defects inside the dielectric. These defects are activated at temperatures higher than 250 K and remain negatively charged. This negative charge induces an extra positive charge in the substrate and/or interface layer, diminishing the local electric field in the region close to the interface and giving place to a flatband voltage shift toward more positive values, VFB, and lower currents. A direct


G210

Table I. Activation energy values and PF coefficients obtained from current measurements corresponding to several MOS samples based on atomic-layer-deposited Gd2O3 thin films. Oxide thickness and annealing temperature are also indicated.

MOS Structure

Gd2O3 Thickness 共nm兲 2.2 2.2 2.2 8.5 8.5 18.1

Al/Gd2O3 /HF-etch-n-Si Al/Gd2O3 /SiO2 /n-Si Al/Gd2O3 /HF-etch-n-Si Al/Gd2O3 /SiO2 /n-Si Al/Gd2O3 /SiO2 /n-Si Al/Gd2O3 /HF-etch-n-Si

Annealing

Activation energy, ⌬E␴ 共meV兲

PF coefficient 共␤PF /10−5 eV m1/2 V−1/2兲, electric field range 共MV/cm兲

As deposited As deposited 750°C As deposited 750°C As deposited

159 — 50.1 24.4 61.6 314

4.04共2.9–3.8兲 0.81共2–3.3兲 1.21共0.5–0.7兲 2.71共0.6–1.5兲 6.73共0.5–0.6兲 14.25共0.2–0.5兲

consequence is the displacement of the conduction onset to higher effective gate voltages. In Fig. 3b the effective voltage values corresponding to 2.5 mA/cm2 current density are displayed for several samples. For all the cases, the effective voltage value monotonically decreases as temperature increases. Only the Al/Gd2O3 /SiO2 /n-Si sample with 2.2 nm thick as-deposited Gd2O3 shows a different behavior for temperatures higher than 250 K, due to the anomalous behavior mentioned above. Effective voltage values are clearly higher for annealed than for as-grown samples in the cases of films deposited on SiO2 /Si substrates, whereas the opposite trend is observed for films deposited on HF-etched Si. The effective voltage values of the as-deposited samples fabricated on oxidized silicon clearly increase with the film thickness, in good agreement with the dependence of leakage current and breakdown voltage with the GdScO3 film thickness reported by Zhao et al.29 Figure 3c shows the current-temperature dependence for the Al/Gd2O3 /SiO2 /n-Si sample with 8.5 nm thick as-deposited Gd2O3. In the 200–300 K temperature range the relationship between ln共I兲 and 1000/T is clearly linear. Such as Arrhenius plot indicates a conduction mechanism controlled by Poole–Frenkel 共PF兲 emission. It is known that for the Schottky emission mechanism an Arrhenius plot of ln共I/T2兲 against 1000/T is obtained. Schottky emission is controlled by the quality of the metal-insulator interface, while the PF mechanism is bulk-limited and relies on the traps in the insulator. The PF is associated with the field-enhanced thermal excitation of charge carriers from traps. As it is shown in the inset, the slopes of the lines do not vary appreciably with the applied voltage, indicating that the conduction takes place through an activated process having a single activation energy, ⌬E␴, which follows the relation30

冉

I = I0 exp −

⌬E␴ KT

冊

关1兴

The activation energy values corresponding to several samples are listed in Table I. Irrespective of the substrate treatment and the film thickness, the activation energy values obtained for the annealed samples correspond to the previously reported soft-optical phonon energy 共in the 55 ± 10 meV range兲, obtained from flatband transient measurements.24 However, activation energy values of asdeposited samples scatter between 24 and 314 meV, indicating that other different mechanisms take place as well, and so the combination of all of them is detected. Figure 3d shows the plot of I/E 共in logarithmic scale兲 against at several temperatures, corresponding to the E1/2 Al/Gd2O3 /SiO2 /n-Si sample with 8.5 nm thick as-deposited Gd2O3. As it is shown in the inset, there is a linear dependence in the high-field range, as required by the PF equation

冉

I = I0 exp

␤PFE KT

1/2

冊

E

关2兴

The obtained value of ␤PF in the 0.6–1.5 MV/cm electric field range is 2.71 ⫻ 10−5 eV m1/2 V−1/2. The current in the lower electric field region is probably due to tunneling of electrons from the

silicon substrate through the SiO2 film, according to the model proposed by Novkovski and Atanassova.26 Indeed, I/E 共in logarithmic scale兲 against E1/2 plots of samples in which a SiO2 layer between the silicon substrate and the Gd2O3 film is not present 共not shown兲 exhibited only one region instead of the two clearly observable regions in Fig. 3d. The PF field-lowering coefficient values, ␤PF, corresponding to several samples, as well as the electric field range where the linear behavior has been observed, are listed in Table I. In order to estimate a theoretical value of ␤PF it is necessary to know the dielectric constant of the Gd2O3 layer at optical frequencies. From optical transmission spectra we measured a refractive index of about 1.92–1.96, thus the optical dielectric constant 共ODC兲 would be about 3.7–3.8. This value is similar to those attributed to high-k dielectrics such as La2O3 共ODC = 3.2,31 ODC = 4.032兲 and Ta2O5 共ODC = 4.428兲. By using this value of ODC we obtain ␤PF = 3.9–4.0 ⫻ 10−5 eV m1/2 V−1/2, which agrees well with the experimental value corresponding to the 2.2 nm thick as-deposited Al/Gd2O3 /HF-etch-n-Si sample 共see row 1 in Table I兲. However, despite the good fit of PF plots, it is clear that ⌬E␴ and ␤PF values differ significantly between all the samples. These differences must be related to the physical structure of the films. In Fig. 1 we can observe the existence of an interface layer 共IL兲 with thickness very dependent on the annealing conditions. For instance, in the case of 2.2 nm thick samples, the interface layer 共probably due to silicate formation兲 has a thickness of about 2.5 nm in the case of the asdeposited film and of about 5 nm after a 750°C annealing. As the IL thickness increases the value of ␤PF decreases due to the resulting lower energy barrier. The high dispersion observed in ⌬E␴ must be related to the interfacial layer instabilities. For a given Gd2O3 thickness, the lower the energy barrier, the lower the value of ␤PF; that is, the electric field barrier lowering is directly related to the barrier height. The IL layer seems to be very sensitive to the process parameters. In situ characterization techniques could be a good approach to a better knowledge of the nature of these substrate-tooxide transition layers. In high-k dielectrics, trap-related mechanisms typically prevail at moderate voltages, while tunneling dominates at much higher fields.27 Indeed, as we have shown elsewhere,24 the I-V characteristics corresponding to “fresh-samples,” i.e., the very first measurements carried out on these samples 共not shown兲, exhibit much greater conduction onset voltage values 共of about 4–7 V, depending on the oxide thickness and fabrication parameters, which correspond to electric fields between 6 and 8 MV/cm兲 and can be fitted according to the law that governs a phonon-assisted tunneling 共PAT兲 between localized states in the insulator bandgap,33 as follows

冉冊

I ⬀ exp

A F1/4

关3兴

Although these first I-V curves are obtained limiting the current values to avoid breakdown, subsequent I-V curves show poorer characteristics with onset values much lower. We explain this behavior as due to the fact that the localized states are not ionized in the fresh samples. When high voltages are applied these defects are


Figure 4. 1 MHz C-V curves corresponding to Al/Gd2O3 /HF-etched-n-Si MIS devices with as-deposited films measured at 共a兲 room temperature and 共b兲 77 K.

Figure 5. 1 MHz C-V curves corresponding to Al/Gd2O3 /n-Si MIS devices with 8.1–8.5 nm thick Gd2O3 films measured at 共a兲 room temperature and 共b兲 77 K. Substrates were either HF-etched Si or SiO2 /Si, indicated by labels.

Cm = ionized in a nonreversible way. Afterward they do not recover the original configuration, giving place to conduction mechanisms different from those observed in fresh samples. Because breakdown current conditions are not reached in any case we preserve the samples from potential unreliability. C-V curves measured at 1 MHz are shown in Fig. 4 and 5. To avoid the inaccuracies due to the relaxation processes caused by slow traps in the dielectric, a large holding time 共100 s instead of the usual 10 s delay time兲 between bias application and capacitance measurement is needed. That is particularly important for roomtemperature measurements. However, at 77 K this long time is not necessary because slow traps are not activated at such low temperatures. Similar instabilities have been reported in gadolinium scandate thin-film-based metal-insulator-semiconductor 共MIS兲 structures.34 Moreover, all C-V curves 共Fig. 4 and 5兲 show anomalous behavior. This is mainly due to the high leakage currents existing in these samples. The capacitance meter assumes that the device under test consists of a capacitance, Cm, in parallel with a conductance, Gm. However, real devices consist of a series resistance, Rs, arising from the finite resistances of the silicon substrate and the gate contact, and the parallel of the oxide capacitance 共Cox兲 and conductance, Cox, due to gate leakage current and loss through interface traps. In consequence, there is an important deviation between the measured capacitance, Cm, and the real capacitance, Cox, given by35

G211

Cox 共RsGox + 1兲2 + 共␻CoxRs兲2

关4兴

Equation 4 indicates that the measured capacitance is lower than the true oxide capacitance. These deviations are more important as the higher the dielectric leakage 共Gox兲 and the series resistance are. For this reason, C-V curves do in fact hardly reach accumulation in leaky samples. Because leakage current increases as the oxide thickness diminishes, this effect is more pronounced for the thinnest samples. Another consequence of these deviations is that equivalent oxide thickness 共EOT兲 or capacitor equivalent thickness 共CET兲 values cannot be obtained from the experimental curves. The effect of the as-deposited Gd2O3 thickness in Al/Gd2O3 /HF-etched-n-Si samples on the shape of the C-V curves can be seen in Fig. 4. When the oxide thickness decreases, flatband voltage shifts to more negative values, denoting the presence of fixed charges. These fixed charges have been attributed to oxygen vacancies.36 Gadolinium can only exist in the +3 oxidation state,37 thus under equilibrium conditions 共provided that Gd does not change its valency and oxidation state兲 the Gd2O3 bulk cannot act as an effective source for oxygen supply to the silicon/dielectric interface.38 So, the presence of oxygen vacancies is expected. At room temperature 共Fig. 4a and 5a兲, all C-V curves exhibit hysteresis, however this phenomenon has not been detected in C-V curves measured at 77 K 共Fig. 4b and 5b兲, indicating that slow traps do not exchange charge at low temperatures, suggesting a thermally activated mechanism. The effects of substrate treatment and thermal annealing on C-V behavior can be seen in Fig. 5 for the 8.1 nm thick Gd2O3 films.

G212


Figure 6. Interfacial state densities measured using DLTS on several Al/Gd2O3 /n-Si MIS devices.

Although the room-temperature C-V curves of the as-deposited samples exhibit a lower flatband voltage shift toward negative values than the annealed ones, their shapes are clearly more anomalous 共Fig. 5a兲. An Al/Gd2O3 /SiO2 /n-Si capacitor with annealed Gd2O3 requires around 3 volts to pass from accumulation to inversion and vice versa. Also, this sample demonstrates a great amount of hysteresis. At 77 K 共Fig. 5b兲, the films grown on HF-etched substrates clearly show better C-V behavior than those grown on SiO2 /n-Si. Figure 6 shows interfacial state densities obtained from DLTS. With regard to as-deposited HF-etched substrates, Dit diminishes as Gd2O3 thickness increases: the 2.2 and 18.1 nm thick samples exhibit Dit values around 2–3 ⫻ 1012 and 1–3 ⫻ 1011 cm−2 eV−1, respectively. In order to understand this result, we must keep in mind that although the deposition conditions are equal for all the samples in terms of temperature, precursors, pressure, reactor, pulse, and purge times, the samples are not identical because they are grown to different thicknesses. This means that the deposition time has been longer for thicker films, ALD being a relatively slow method. This in turn means that crystalline order in the thicker films is usually better and the crystallization may reach back down to the interface, and thus a low interfacial state density would be apparent. Also, thermal annealing improves interface quality: the annealed 2.2 and 8.1 nm thick samples exhibit Dit values around 4–5 and 1–2 ⫻ 1011 cm−2 eV−1, respectively. Interestingly, the samples fabricated on oxidized silicon substrates have higher interfacial state densities than those fabricated on HF-etched silicon; the annealed 8.5 nm thick sample exhibits a Dit value of around 4–5 ⫻ 1012 cm−2 eV−1. This result, besides the C-V results, indicates that Gd2O3 /SiO2 stacks are very defective, possibly due to some reaction occurring between thin SiO2 and Gd2O3 film deposited. It is also known that Gd2O3 can be grown epitaxially on silicon. Instead of Si共100兲 used in the present study, Si共111兲 and also Si共110兲 particularly promote epitaxial growth of Gd2O3 with preferred 共111兲 orientation, improving the dielectric performance.39 In the case of the Gd2O3 films grown on the technologically more conventional Si共100兲, the films may rather become 111-textured corresponding to the densest packing of the layer and growth in the direction of the lowest energy surface. Orientation features remain beyond the scope of the present study and cannot be detected by grazing incidence X-ray diffraction 共XRD兲. However, one can speculate that some interaction between the cubic lattices of substrate and film occurs while first layers grown and/or first nuclei might form commensurate interface to the etched substrate. Such an interface may exhibit lower electronic defect densities compared to the film grown on amorphous substrate surface 共SiO2兲. Interface properties of the

Figure 7. DIGS density obtained from conductance transients corresponding to Al/Gd2O3 /HF-etched-n-Si MIS devices with as-deposited 18.1 nm thick Gd2O3. The spatial distance to the dielectric/silicon substrate interface is denoted by xc, and ET is the energy position with respect to the silicon conduction bandedge.

Gd2O3 /SiO2 stack would need deeper investigations, because the effects cannot be deduced from XRD measurements; the thinnest films remained X-ray amorphous. It has been possible to record conductance transients only for the thickest film. For thinner samples, instabilities in conductance signal have not allowed us to measure DIGS densities. Three-dimensional graph of DIGS density as a function of energy position and spatial coordinate, corresponding to the Al/Gd2O3 /HF-etched-n-Si sample with as-deposited 18.1 nm thick Gd2O3, is shown in Fig. 7. DIGS density reaches maxima values of 2–2.5 ⫻ 1011 cm−2 eV−1 located at about 25 Å from the dielectric/semiconductor interface and at energy positions between 120 and 240 meV above the semiconductor conduction band. These results are similar to DIGS values measured in HfO240 and Al2O341 as-deposited films under similar conditions and are only slightly higher than those measured in HfSixOy.42 Figure 8 shows flatband voltage transients, recorded by keeping the capacitance constant at the initial flatband condition. These measurements give information about phonon-assisted tunneling mechanisms between localized states in the bandgap of the insulator.24 Amplitude and time constants of transients depends on dielectricthickness, thermal annealing, and substrate treatment 共Fig. 8a兲. Flatband transient amplitudes of the annealed samples are higher than those of the as-deposited samples, especially in the oxidized substrate cases. As for temperature dependence, the amplitude of transients increases with temperature, but the time constant scarcely varies for thickness greater than 5.7 nm, as is shown in Fig. 8b, in which normalized transients are obtained by dividing experimental transients by their value at 600 s. However, for the thinnest samples 共2.2. nm兲 some temperature dependence is apparent, especially near room temperature, as is shown in Fig. 8c. The singularity of the thinnest sample behavior agrees well with its anomalous temperature dependence of the I-V curves described above. Conclusion Gd2O3 thin films were grown from tris共2,3-dimethyl-2butoxy兲gadolinium共III兲, Gd关OC共CH3兲2CH共CH3兲2兴3, and H2O precursors at 350°C on Si共100兲. The films tended to crystallize in cubic phase with critical crystallization thickness around 10 nm. The stoichiometric oxygen-to-gadolinium atomic ratio measured in 65 nm


G213

teristics than those deposited on SiO2 /Si, in terms of leakage current and flatband voltage. In this regard, the films possessed electrical characteristics noticeably different from more conventional highpermittivity materials, e.g., HfO2. Thermal annealing improves Al/Gd2O3 /HF-etched Si samples in terms of Dit but leads to higher values of leakage current and flatband voltage. However, thermal annealing improves I-V characteristics but raises flatband voltage of Al/Gd2O3 /SiO2 /Si samples. Both the interfacial state density and the flatband voltage shift value decreases when the oxide thickness of as-deposited Al/Gd2O3 /HF-etched Si samples increases. DIGS values obtained for the 18 nm thick unannealed Al/Gd2O3 /HF-etched Si sample are very similar to those measured in HfO2 film-based MIS structures. Flatband transient amplitudes increase when thermal annealing is applied, both in samples fabricated on oxidized and on HF-etched substrates. Acknowledgments The study was partially supported by the local government 共Junta de Castilla y León兲 under grant no. VA018A06 and by the Spanish TEC2005 under grant no. 05101/MIC. The authors are indebted to Dr. Kai Arstila for the ERDA results. Universidad de Valladolid assisted in meeting the publication costs of this article.

References 1. 2. 3. 4. 5. 6.

7. 8. 9.

10. 11. 12. 13. 14. 15.

16. 17. 18. 19. 20. 21. 22. 23.

Figure 8. 共a兲 Flatband transients, measured at 300 K, corresponding to several Al/Gd2O3 /HF-etched n-Si capacitors with 2.2 and 8.1 nm thick Gd2O3 films. 共b兲 Normalized flatband transients, measured at temperatures between 160 and 300 K, corresponding to capacitors with 8.1 nm and 共c兲 2.2 nm thick Gd2O3 films annealed at 750°C.

24. 25. 26. 27. 28. 29.

thick film was close to 1.4 ± 0.5, allowing the oxygen deficiency in the films. The contents of residual hydrogen and carbon reached 1.0 ± 0.5 and 0.6 ± 0.3 atom %, respectively. Unannealed Gd2O3 films on HF-etched Si exhibit better charac-

30. 31. 32.

K. J. Hubbard and D. G. Schlom, J. Mater. Res., 11, 2757 共1996兲. J. Robertson, J. Vac. Sci. Technol. B, 18, 1785 共2000兲. M. Leskelä and M. Ritala, J. Solid State Chem., 171, 170 共2003兲. M. Leskelä, K. Kukli, and M. Ritala, J. Alloys Compd., 418, 27 共2006兲. M. Hong, A. R. Kortan, J. Kwo, J. P. Mannaerts, J. J. Krajewski, Z. H. Lu, K. C. Hsieh, and K. Y. Cheng, J. Vac. Sci. Technol. B, 18, 1688 共2000兲. J. Kwo, M. Hong, A. R. Kortan, K. T. Queeney, Y. J. Chabal, J. P. Mannaerts, T. Boone, J. J. Krajewski, A. M. Sergent, and J. M. Rosamilia, Appl. Phys. Lett., 77, 130 共2000兲. M. Hong, M. Passlack, J. P. Mannaerts, J. Kwo, S. N. G. Chu, N. Moriya, S. Y. Hou, and V. J. Fratello, J. Vac. Sci. Technol. B, 14, 2297 共1996兲. M. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts, and A. M. Sergent, Science, 283, 1897 共1999兲. J. Kwo, M. Hong, A. R. Kortan, K. L. Queeny, Y. J. Chapal, R. L. Opila, Jr., D. A. Muller, S. N. G. Chu, B. J. Sapjeta, T. S. Lay, et al., J. Appl. Phys., 89, 3920 共2001兲. M. P. Singh, C. S. Thakur, K. Shalini, S. Banerjee, N. Bhat, and S. A. Shivashankar, J. Appl. Phys., 96, 5631 共2004兲. T. M. Pang, C. S. Liao, H. H. Hsu, C. L. Chen, and J. C. Wang, Appl. Phys. Lett., 87, 262908 共2005兲. S. A. Park, Y. S. Roh, Y. K. Kim, J. H. Baeck, M. Noh, K. Jeong, M. H. Cho, C. H. Chang, M. K. Joo, T. G. Kim, et al., J. Appl. Phys., 98, 024906 共2005兲. L. Z. Hsieh, H. H. Ko, P. Y. Kuei, L. B. Chang, and M. J. Jeng, J. Appl. Phys., 98, 076110 共2005兲. A. C. Jones, H. C. Aspinall, P. R. Chalker, R. J. Potter, K. Kukli, A. Rahtu, M. Ritala, and M. Leskelä, J. Mater. Chem., 14, 3101 共2004兲. H. Iwai, S. Ohmi, S. Akama, C. Ohsima, I. Kashiwagi, A. Kikuchi, J. Taguchi, H. Yamamoto, I. Ueda, A. Kuriyama, et al., in Physics and Technology of High-k Gate Dielectrics I, S. Kar, D. Misra, R. Singh, and F. Gonzalez, Editors, PV 2002-28, p. 27, The Electrochemical Society Proceedings Series, Pennington, NJ 共2002兲. J. Päiväsaari, M. Putkonen, and L. Niinistö, Thin Solid Films, 472, 275 共2005兲. T. Suntola, Thin Solid Films, 216, 84 共1992兲. D. V. Lang, J. Appl. Phys., 45, 3023 共1974兲. M. Schulz and N. M. Johnson, Appl. Phys. Lett., 31, 622 共1977兲. L. He, H. Hasegawa, T. Sawada, and H. Ohno, J. Appl. Phys., 63, 2120 共1998兲. T. Hashizume, H. Hasegawa, R. Riemenschneider, and H. L. Hartnagel, Jpn. J. Appl. Phys., Part 1, 33, 727 共1994兲. S. Dueñas, R. Peláez, H. Castán, R. Pinacho, L. Quintanilla, J. Barbolla, I. Mártil, and G. González-Díaz, Appl. Phys. Lett., 71, 826 共1997兲. H. Castán, S. Dueñas, J. Barbolla, E. Redondo, N. Blanco, I. Mártil, and G. González-Díaz, Microelectron. Reliab., 40, 845 共2000兲. S. Dueñas, H. Castán, H. García, L. Bailón, K. Kukli, M. Ritala, and M. Leskelä, Microelectron. Reliab., 47, 653 共2007兲. B. O. Cho, J. Wang, L. Sha, and J. P. Chang, Appl. Phys. Lett., 80, 1052 共2002兲. N. Novkovski and E. Atanassova, Appl. Phys. A, 83, 435 共2006兲. W. Yang, J. Marino, A. Monson, and C. A. Wolden, Semicond. Sci. Technol., 21, 1573 共2006兲. N. Novkoski, Semicond. Sci. Technol., 21, 945 共2006兲. C. Zhao, T. Witters, B. Brijs, H. Bender, O. Richard, M. Caymax, T. Heeg, J. Schubert, V. V. Afanas’ev, A. Stesmans, et al., Appl. Phys. Lett., 86, 132903 共2005兲. N. A. Hegab and H. E. Atya, J. Ovonic Research., 2, 21 共2006兲. Y. Kim, S. Ohmi, K. Tsutsui, and H. Iwai, Jpn. J. Appl. Phys., Part 1, 44, 6A and 4032 共2005兲. S. Kar and R. Singh, in Physics and Technology of High-k Gate Dielectrics I, S.

G214

33. 34. 35.

36. 37.


Kar, D. Misra, R. Singh, and F. Gonzalez, Editors, PV 2002-28, p. 13, The Electrochemical Society Proceedings Series, Pennington, NJ 共2002兲. G. A. Niklasson and K. Brantervik, J. Appl. Phys., 59, 980 共1986兲. M. Wagner, T. Heeg, J. Schubert, St. Lenk, S. Mantl, C. Zhao, M. Caymax, and S. De Gendt, Appl. Phys. Lett., 88, 172901 共2006兲. W. J. Zhu, M. Khare, J. Snare, P. R. Varekamp, S. H. Ku, P. Agnello, T. C. Chen, and T. P. Ma, Proceedings of the International Symposium on VLSI Technology Systems Applications, Hsinchu, Taiwan, p. 212 共2001兲. A. Laha, E. Bugiel, H. J. Osten, and A. Fissel, Appl. Phys. Lett., 88, 172107 共2006兲. R. L. Nigro, V. Raineri, C. Bondiorno, R. Toro, G. Malandrino, and I. L. Fragala,

Appl. Phys. Lett., 83, 129 共2003兲. 38. M. Czernohorsky, E. Bugiel, H. J. Osten, A. Fissel, and O. Kirfel, Appl. Phys. Lett., 88, 152905 共2006兲. 39. A. Laha, H. J. Osten, and A. Fissel, Appl. Phys. Lett., 89, 143514 共2006兲. 40. S. Dueñas, H. Castán, H. García, J. Barbolla, K. Kukli, J. Aarik, and A. Aidla, Semicond. Sci. Technol., 19, 1141 共2004兲. 41. S. Dueñas, H. Castán, H. García, A. de Castro, L. Bailón, K. Kukli, A. Aidla, J. Aarik, H. Mändar, T. Uustare, et al., J. Appl. Phys., 99, 054902 共2006兲. 42. S. Dueñas, H. Castán, H. García, L. Bailón, K. Kukli, M. Ritala, M. Leskelä, M. Rooth, O. Wilhelmsson, and A. Harsta, J. Appl. Phys., 100, 094107 共2006兲.