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etching and ashing. Based on the analysis, new test structures are suggested also. II. EXPERIMENT. Gate oxides in MOS devices are degraded after plasma ...



The percent differences reported in the last column also quantify their impact on device gate capacitances (for any given area).

Overestimation of Oxide Defects Density in Large Test Capacitors Due to Plasma Processing


Hyungcheol Shin, Minkyu Je, and Chenming Hu

A new method is presented to measure the amplitude of the first three harmonics of the dispacement current flowing into a MOS capacitor biased with a small AC signal that allows to determine the first two derivatives of the C –V plot, in turn required to work out the thickness of the capacitor insulator. The method satisfactorily overcomes the noise problem affecting the determination of such derivatives from conventional C –V plots, and provides a reliable tool to measure the thickness of ultrathin (tunnel) oxides, suitable to be used for technology development.

Abstract—Oxide shorts density obtained from large test capacitors is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. The observed difference in failure rate is explained by the different oxide charging currents for the weak spots in the two devices during plasma processing. This experiment can explain the observed lower density of shorts after plasma processing in IC’s, which is composed of many small devices, than in test structures which are large capacitors. Suggestions on the test structures are presented.

I. INTRODUCTION ACKNOWLEDGMENT The authors are grateful to SGS-Thomson Microelectronics, Agrate Brianza, Milan, Italy, for providing the devices used for the experiments of this work. REFERENCES [1] B. Ricc`o, P. Olivo, T. N. Nguyen, T.-S. Kuan, and G. Ferriani, “Oxidethickness determination in thin-insulator MOS structures,” IEEE Trans. Electron Devices, vol. 35, pp. 432–439, 1988. [2] R. Rios and N. D. Arora, “Determination of ultrathin gate oxide thickness for CMOS structures using quantum effects,” in IEDM Tech. Dig., 1994, pp. 613–616. [3] B. Majkusiak and A. Jakubowski, “A technical formula for determining the insulator capacitance in a MOS structure,” Solid-State Electron., vol. 35, pp. 223–224, 1992. [4] G. Sarrabayrouse, F. Campabadal, and J. L. Prom, “Oxide-thickness determination from C=V measurements in an MOS structure,” Proc. Inst. Elect. Eng., vol. 136, pp. 215–216, 1989. [5] H. Reisinger, H. Oppolzer, and W. H¨onlein, “Thickness determination of thin SiO2 on silicon,” Solid-State Electron., vol. 35, pp. 797–803, 1992. [6] P. M. D. Chow and K. L. Wang, “A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1299–1304, 1986.

Large test capacitors are widely used for monitoring the density of oxide defects. However, it has been noted that these large test capacitors seem to severely overestimate the density of oxide shorts. In other words, the shorts density value obtained from the test capacitor would predict significantly lower product circuit yields than the yields actually obtained in IC’s. In this brief, an explanation for this anomaly is proposed in terms of oxide stressing due to plasma etching and ashing. Based on the analysis, new test structures are suggested also. II. EXPERIMENT Gate oxides in MOS devices are degraded after plasma etching and ashing due to electrical stress during the process [1]–[5]. The test structures used are n+ polysilicon-gate MOS capacitors fabricated ˚ gate oxides grown in on n-type (100) silicon substrates with 64 A dry oxygen at 900  C. After gate definition, LTO was deposited. After etching the aluminum, subsequent photoresist stripping was done in a barrel-type stripper under normal conditions. The ashing gas was oxygen at 280 mTorr. The gas flow was 50 sccm and the power was 400 W. Wet processes were used for all processing steps except ashing. Control wafers receiving only wet processes were also fabricated. The photoresist stripping experiments were done for the three types of test structures under the same plasma conditions stated above. Fig. 1 shows simplified schematics of the three capacitors. Type A [Fig. 1(a)] is a large test capacitor with an oxide area of 32105 m2 . Type B [Fig. 1(b)] is composed of 3000 small capacitors (oxide area of 100 m2 ) each having a small isolated polysilicon gate topped by a small isolated piece of Al. The Al pads were later connected together with a second layer of Al defined by wet etching for breakdown testing. Type C [Fig. 1(c)] is the same as type B except that it has a single large Al pad connecting all 3000 polysilicon gates such that the individual gates are connected during plasma photoresist stripping. The total oxide area for type B and C capacitors are the same as Manuscript received October 21, 1996; revised Febraury 23, 1997. The review of this brief was arranged by Editor G. W. Neudeck. This work was supported by SRC, Sandia Laboratory, Signetics, TI, Rockwell International, and AMD under the MICRO program and ISTO/SDIO administered by ONR under Contract N00014-92-J-1757. H. Shin and M. Je are with Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon 305-701, Korea. C. Hu is with the Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA 94720 USA. Publisher Item Identifier S 0018-9383(97)06140-6.

0018–9383/97$10.00  1997 IEEE







Fig. 1. Schematic top views of capacitors. (a) A large single-test capacitor. Al area is 4 m2 . (b) 3000 small capacitors electrically separated during photoresist ashing. Each Al area is 800 mm2 . Only 16 capacitors are shown. (c) 3000 small capacitors connected together during ashing. Al area is 3 106 m2 .



Fig. 2. More shorts are created by resist ashing process for 60 min in large capacitors (A) than in ensembles of small capacitors (B) although they have the same total oxide area and type B has six times larger total Al area. If the 3000 small capacitors were connected during resist ashing (C), much more shorts were observed because of the larger Al area.

the area of type A capacitor, therefore they should have the same number of defects or more defects if there is a contribution from the capacitor edge.

III. RESULTS Fig. 2 compares the oxide breakdown voltage distribution after photoresist stripping for a large single capacitor (type A) and for separated small capacitors whose gates are connected together by a wet-etched second layer of Al (type B). The breakdown distributions of control capacitors are also shown in the figure. More shorts were observed in the type A capacitor, even though the oxide area is the same for the two devices and total Al pad size of the type B capacitor (2:4 2 106 m2 ) is six times larger than that of the type A capacitor (4 2 105 m2 ). This result confirms prior observations that large capacitor structures yield a larger defect density than a multiple of small capacitors. The type B capacitor has similar failure statistics as wet-processed control capacitors. This suggests that type A capacitor’s higher incidence of shorts is attributable to

Fig. 3. Deduced oxide charging current during photoresist stripping and Al etching at different rf powers. The Al etching was done in a parallel plate etcher with the following conditions. The rf frequency was 13.56 MHz; the main etching gas was Cl2 ; the pressure was 250 mTorr; and the power was 250 W.

dry processing [1]–[9]. The question is why the type B structure is less susceptible to dry processing-induced damage. In a type A capacitor, all the oxide charging current collected by the single large Al pad is available to flow through the weakest spot in the oxide. Therefore the breakdown voltages of weak spots were reduced from 6–8.5 V to 0–5 V (Fig. 2). Since type B capacitor gates are isolated during the process, the weakest spot is stressed by the current collected by the very small Al pad connected to the that small capacitor, therefore resulting in lower failure rate. Also note that the breakdown voltages of the intrinsic capacitors are not shifted at all. Therefore, the weakest spot in a type B capacitor gets less stress than the same weakest spot in a type A capacitor during plasma process, resulting in a lower oxide failure rate. Using similar reasoning, the type C structure is expected to have the highest density of shorts. This is indeed the case (Fig. 2). By



comparing the CV curve of a plasma-processed capacitor with the CV’s of antenna-free or wet-processed capacitors after a constant current stress, one can deduce the oxide charging current experienced by the oxide during the processing [8]. The charging current is proportional to the Al pad area during plasma ashing [8], therefore the failure rate of type C capacitors are even higher than that of type A capacitors since type C capacitor has eight times larger Al antenna area. IV. SUMMARY


[10] P. Olivo, T. Nguyen, and B. Ricco, “High-field-induced degradation in ultrathin SiO2 films,” IEEE Trans. Electron Devices, vol. 35, pp. 2259–2267, Dec. 1988. [11] R. Rofan and C. Hu, “Stress-induced oxide leakage,” IEEE Electron Device Lett., vol. 11, pp. 632–634, 1991. [12] H. Shin, K. Noguchi, and C. Hu, “Modeling oxide thickness dependence of charging damage by plasma processing,” IEEE Electron Device Lett., vol. 14, pp. 509–511, Nov. 1993.


After plasma photoresist stripping, density of oxide shorts obtained from large test capacitors is higher than that obtained from separated small capacitors even though the total oxide areas are the same for the two structures. The stress current for the weakest spot is larger in the larger capacitor. This experiment can explain the observed lower density of shorts in IC’s, which are composed of many small devices, than in test structures which are large capacitors even though the test structure’s antenna ratio is actually smaller. To reduce this discrepancy, it is recommendable that the test structures are made of not-too-large individual oxides and poly gates, which are then connected by metal. Fig. 3 shows the inferred oxide charging current during etching and ashing [8], [9]. Empirically, 10 nA of oxide charging current per gate appears to be acceptable without distorting the defect data, therefore each unprotected gate electrode can be up to 104 m2 in area and 103 m in peripheral length. The separate poly-Si gates can then be connected by metal, which should be protected with a pn diode. It is known that a protection pn diode can be added to the metal to reduce plasma etching damage in the oxide [6], [7]. This shunt protection diode can minimize oxide stressing during plasma etching and ashing by providing a leakage path (at the process temperature and under plasma illumination) for the oxide charging current. The use of shunt diode in large test capacitors is probably justifiable in view of the realization that plasma stress has much less damaging effect on the small oxides in real circuits.

Optimizing Quarter and Sub-Quarter Micron CMOS Circuit Speed Considering Interconnect Loading Effects Kai Chen, Chenming Hu, Peng Fang, Min Ren Lin, and Donald L. Wollesen

Abstract— An experimentally confirmed accurate CMOS gate delay model is applied to the CMOS ring oscillators with interconnect loading. The optimum gate oxide thickness Tox should be chosen differently as interconnect loading varies. Guidelines in choosing optimum Tox for different interconnect loading, combined with channel length and power supply scaling, are obtained.

I. INTRODUCTION Propagation delay tpd of unloaded CMOS ring oscillators has been studied [1]. However, in real integrated circuits, particularly for the sub-quarter micron technologies, interconnect capacitance Cint can no longer be ignored [2], [3]. It is particularly true for signal lines and clock buses where Cint is especially significant. II. MODELING


C V 1 tpd = L dd 3:7 Idsatn

REFERENCES [1] C. Gabriel and J. C. Mitchener, “Reduced device damage using an ozone based photoresist removal process,” in Proc. SPIE, 1989, vol. 1086, pp. 598–603. [2] S. Fang and J. McVittie, “Thin-oxide damage from gate charging during plasma processing,” IEEE Electron Device Lett., vol. 13, pp. 288–290, May 1992. [3] S. Fang and J. McVittie, “A model and experiments for thin oxide damage from wafer charging in magnetron plasmas,” IEEE Electron Device Lett., vol. 13, pp. 347–349, June 1992. [4] Y. Kawamoto, “MOS Gate insulator breakdown caused by exposure to plasma,” in Proc. 1985 Dry Process Symp., Inst. Elect. Eng. Jpn., 1985, pp. 132–137. [5] Y. Ksunokuni, K. Nojiri, S. Kuboshima, and K. Hirobe, “The effect of charge build-up on gate oxide breakdown during dry etching,” in Ext. Abstr. 19th Conf. Solid-State Devices and Materials, 1987, pp. 195–198. [6] F. Shone, K. Wu, J. Shaw, E. Hodelet, S. Mittal, and A. Haranahalli, “Gate oxide charging and its elimination for metal antenna capacitor and transistor in VLSI CMOS double-layer metal technology,” in Symp. VLSI Tech. Dig. Papers, 1989, pp. 73-74. [7] H. Shin, J. Ma, and C. Hu, “Impact of plasma charging damage and diode protection on scaled thin oxide,” in IEDM Tech. Dig., 1993. [8] H. Shin, C.-C. King, and C. Hu, “Thin oxide damage by plasma etching and ashing processes,” in Proc. IEEE IRPS, 1992, pp. 37–41. [9] H. Shin and C. Hu, “Dependence of plasma-induced oxide charging current on Al antenna geometry,” IEEE Electron Device Lett., vol. 13, pp. 600–602, Dec. 1992.


CMOS ring oscillator propagation delay tpd can be calculated by the following equation [1]: +




where drain saturation current [1]

Idsat = Idsato


2Idsato Rs

Vgs 0 Vt

0 Vgs 0IVdtsat+o REssatL


: (2)

Here, different Taylor expansion to get (2) is used from that of [1]. Equation (2) is preferred because for the limiting case of large Rs , Idsat should approach zero. Idsato is the saturation current when Rs = 0 2 (Vgs 0 Vt ) W e Cox Idsato = (3) 2 v L 2Le 1 + (Vgs 0 Vt )  e and e is an empirical function of Vgs , Vth , and Toxe as reported in [4]. Manuscript received September 12, 1996; revised March 18, 1997. The review of this brief was arranged by Editor D. A. Antoniadis. This work was supported by SRC Contract 94-DC-324 and 95/96-SJ-417, the Joint Services Electronics Program, F49620-94-C-0038, and AFOSR F49620-94-1-0464. K. Chen and C. Hu are with the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720 USA. P. Fang, M. R. Lin, and D. L. Wollesen are with Advanced Micro Devices, Sunnyvale, CA 94088 USA. Publisher Item Identifier S 0018-9383(97)06141-8.

0018–9383/97$10.00  1997 IEEE