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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 12, DECEMBER 2000

Analytical Model and Characterization of Abnormally Structured MOSFETs Jae-Sung Lee, Associate Member, IEEE, and Yong-Hyun Lee, Member, IEEE

Abstract—Electrical characteristics of abnormally structured n-MOSFETs having uncontacted active regions are experimentally investigated using test devices with various gate width. Linear resistance and saturation drain current of devices are estimated by a simple schematic model, which consists of parallel-connected conventional devices having parasitic resistor. A comparison of experimental results of conventional and abnormal devices gives the parasitic resistance caused by abnormal active structure. The increment rate of the parasitic resistance depending on gate width shows two categories, which are logarithmic increment at narrow device and exponential increment at wider device. The performance degradation in the wider device is also explained by the reduction of effective channel area. The suggested model provides a physical analysis of the abnormal transistor and shows good agreement with the measured drain current in linear and saturation regions for both forward- and reverse-modes. Index Terms—Abnormally structured MOSFET, channel modification, effective bulk charge, parasitic resistance, uncontacted source/drain region.

model of devices. Neither of these works has provided the analytical model for parasitic resistance induced by the abnormal structure. This paper describes electrical characteristics and physically based analytic model of a 0.35 m abnormally structured n-MOSFETs having irregular source/drain contacts and asymmetric source/drain areas. The parasitic resistances of source and drain sides related to the structure of device are extracted by the comparison of drain current in both linear and saturation regions between various devices. The dependence of the effective gate-induced bulk-depletion charge under channel on the device width is also investigated with threshold voltage. Our suggested model is certified with a two-dimensional (2-D) device simulator. While abnormally structured MOSFETs having irregular source/drain contacts and asymmetric source/drain areas can be designed with arbitrary structures, here in this work, we only consider several simple structures which is suitable for our purpose.

I. INTRODUCTION

A

BNORMALLY structured MOSFET’s with irregular source/drain contacts, polygonal source/drain diffusion areas, or curved gate patterns are innovative devices to reduce layout size in VLSI circuit design. However, there exits an unavoidable intrinsic parasitic series resistance associated with the structure of MOSFET’s. The parasitic effects of source and drain side are quite different. The parasitic resistance of source side induces serious decrease in effective gate voltage, whereas the parasitic resistance of drain side does not much affect drain current when MOSFET is operated in saturation region. Design engineers may overestimate the circuit performance in circuit simulation unless the current degradation effects from those abnormal transistors are considered. Therefore, it is important to assess its impact on MOSFET model parameters for circuit simulation. Several works for abnormal structured MOSFETs have been reported in the literature [1]–[5]. Ohzone and Matsuyama [1] measured the characteristics of a trapezoidal gate MOSFET, while Wong and others [2] characterized a dc model for MOSFETs with gates of asymmetric trapezoidal shape. In both works they considered only the structure of 45 angle gate and normal width. Park and others [3] developed a characterization tool applicable to abnormal structure; but did not suggest analytical Manuscript received October 7, 1999; revised June 1, 2000. The review of this paper was arranged by Editor J. M. Vasi. J.-S. Lee is with Uiduk University, Kyoungbuk-do 780–713, Korea (e-mail: [email protected]). Y.-H. Lee is with Kyoungpook National University, Taegu, Korea, Publisher Item Identifier S 0018-9383(00)10399-5.

II. DEVICE FABRICATION Three test structures used in the experiments were designed, as shown in Fig. 1, to investigate the parasitic effects of asymmetric source/drain areas. The layouts in Fig. 1(a) and (b) are the main structures for conventional and abnormal devices. The layout in Fig. 1(c) is prepared to estimate the suggested model for device in Fig. 1(b). The as-drawn gate length is fixed as 0.35 m, while the channel width varies from 1.6 to 27.2 m. The lateral length ( ) of uncontacted source regions in the abnormal structure is also varied from 0.4 to 0.7 m to show the parasitic effect on the same structure, keeping the space between contact m . and gate as 0.6 m and the area of contact as The test structures are n-MOSFETs of surface channel and LDD. They were fabricated by a twin-tub CMOS process. The processing sequence of the abnormal device is the same as that of the conventional device. The starting material was a 25 cm p-type substrate. The gate oxide thickness of 7 nm and the height of the gate polysilicon of 250 nm were achieved. All active contact and gate contact regions are fully silicided with Ti for improved performance. Active regions except contact regions, however, are silicided optionally to extract parasitic resistance depending on active geometry. The metallurgical channel length is estimated to be 0.27 m. The process steps were implemented by 2-D process simulator to achieve doping profiles. The surface boron concentration reaches cm at the channel region. N source/drain region concentration formed by arsenic–ion implantation is about cm with 0.17 m junction depth.

0018–9383/00$10.00 © 2000 IEEE

LEE AND LEE: ABNORMALLY STRUCTURED MOSFETS

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(a)

Fig. 2. Forward saturation drain current dependence on gate width for conventional and abnormal devices.

(b)

(c) Fig. 1. Layouts of test structures (gate length: 0.35 m, contact size: 0.6 m). The lateral length (l) of uncontacted source region is varied from 0.4 to 0.7 m. (a) Conventional device. (b) Abnormal device to treat mainly. (c) Abnormal device to estimate the suggesting model.

The n-MOSFET characteristics were measured by an HP4156B, where substrate bias was 0 V. And then device simulation was done to evaluate electrical characteristics. III. DEVICE CHARACTERISTICS AND DISCUSSION A. Electrical Characteristics The use of Ti–silicide on source/drain regions will reduce the parasitic resistance so that the electrical characteristics of abnormal transistor are effectively enhanced. For the purpose of device geometric sensitivity study, abnormal device, having the nonsilicided active region, was mainly evaluated to magnify the parasitic effect. In this section, linear threshold voltage, liner resistance, and saturation drain current are estimated for electrical characteristics of devices. Linear resistance is calculated by the current 0 and 0.1 V when 3.3 V. Saturavariation between 3.3 V. All values tion drain current is measured at in this section represent the average for measured values of 38 devices. Fig. 2 shows forward saturation drain current as a function of gate width for both conventional and abnormal devices. As expected, the abnormal device shows lower drain current than that of the conventional device. The measured result indicates that the saturation drain current of abnormal device depends on silicide process so that silicided abnormal device, having width

Fig. 3. Reverse saturation drain current dependence on gate width for conventional and abnormal devices. Region 1 represents the width range that devices show the same results. The degradation of saturation current for nonsilicided abnormal device is shown in region 2.

less than 15 m, is compatible with conventional device. The measured saturation current of devices for the reverse-mode is shown in Fig. 3. Conventional and abnormal devices show the same result in spite of their different structures when they have the width less than 10 m. This width region is represented as region 1 in Fig. 3. Theoretically, devices may have the same saturation current through the whole width if their source resistances are the same and their drain resistances are much smaller than channel resistance [6]. The degradation of saturation current for nonsilicided abnormal device, as shown in region 2 of Fig. 3, indicates that the parasitic drain resistance increases extremely as the gate width increases. Fig. 4 shows linear resistance as a function of gate width for both conventional and abnormal devices. The effect of linear resistance on active geometry in the abnormal device is also shown with changing the lateral length ( ) of uncontacted source/drain regions. It is clear that the linear resistance is related to the parasitic resistance of uncontacted active region. The results for both forward- and reverse-modes are almost same because the drain current in the linear region is in inversion proportion to the sum of the source and drain resistances [6]–[8]. Fig. 5 shows the gate width dependence of threshold voltage for both conventional and abnormal devices. The threshold

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(a)

Fig. 4. Linear resistance as a function of gate width for devices. Solid and dot lines represent silicided and nonsoilicided devices, respectively.

(b) Fig. 6. Schematic model for abnormal device based on physical analysis. (a) Equivalent circuit. (b) Physical view; shaded area represents transistor including resistor .

R

Q

tance. The current SPICE fitter equations give for the linear drain current [9]. (1) Fig. 5. Linear threshold voltage as a function of gate width for devices. Solid and dot lines represent silicided and nonsilicided devices, respectively.

voltage is given as the value of ( ) at the onset of strong inversion. The threshold voltage decrease as gate width becomes wide for nonsilicided abnormal devices. The decrement rate of threshold voltage in nonsilicided abnormal device is relatively large in comparison with that of conventional devices. The silicided abnormal devices show almost same result with the conventional device.

. is the gain constant ratio bewhere tween linear and saturation regions, is the velocity saturation constant, is the threshold voltage, and is the mobility degradation parameter. For abnormal devices, degradation of the drain current in the linear region would be explained with the voltage drop only in source and drain resistance because channel resistance is much , smaller in the linear region. With the parasitic resistance, internal to the abnormal device, the total linear region resistance is (2)

B. Theoretical Schematic Model We assume that the electrical behavior of an abnormal MOS transistor is equivalent to that of a conventional MOS transistor in series with a source resistor. To represent abnormal devices of which gate width are increasing more realistically, the equivalent circuits, having different resistance, are connected in parallel, as shown in Fig. 6(a). The schematic model is based on physical analysis represented in Fig. 6(b). For example, shaded and a resistor . Each transistor in area includes a transistor this model has the same geometry of which channel width and gate length are 1.6 and 0.35 m, respectively. The resistance of each resistor depends on the distance from the gate to a source contact, as shown in Fig. 6(b). The linear drain current equation is derived with the source parasitic resistance included as part of the total channel resis-

Using (1) and (2) and

gives

(3) (4)


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where . For , (3) and (4) reduce to (1), which is for conventional device. with fixed in the conventional In general for any given , in the linear region is given device the channel resistance, . It is based on the assumption that the parasitic acby tive resistance in the conventional device can be neglected compared with that in the abnormal device. The linear drain current, , in the arbitrary abnormal device including and the cor, can be responding parasitic resistance,

(5)

Referring to the schematic model in Fig. 6(a), the linear drain current of each transistor can be represented as

Fig. 7. Parasitic resistance as a function of width of un-contacted source region (l 0:7 m). Solid lines fit the measured values. Region 1 and 2 represent the ranges of logarithmic and exponential increment, respectively.

=

and

is the same as that of conventional device with gate width and are the resistance related to the un-con1.6 m. tacted source region. Finally, the linear drain current of actual abnormal device is calculated by the sum of each current. For example, the linear drain current of abnormal device with gate ( m) width 4.8 m is represented as . C. Device Analysis and Model Verification values for each transistor model of Fig. 6 are calcuThe lated by the eqn (5) with several measured values. During the , drain and gate voltages were maintained at measurement of 0.1 and 3.3 V, respectively in order to satisfy linear condition. Fig. 7 shows the width of un-contacted source region versus , calculated from the eqn (5) for nonits parasitic resistance, m. The solid lines silicided abnormal device having values inshow the tendency of the measured resistance. crease as logarithmic function for gate width in normal width device, while as exponential function in wide device. To explain this discrepancy as different mechanism the gate width region is divided as region 1 and region 2, which were also used in Fig. 3 to explain the gate width range where the parasitic resistance is exceedingly increasing. If the schematic model in Fig. 6 of which transistors have a same geometry is valid for a whole gate width range the corresponding parasitic resistance, , will follow the logarithmic tendency for gate width. The deviation from this basic principle indicates the additional resistance component in wider device due to the secondary mechanism. The range of each region given in Figs. 3 and 7 is almost the same when the width of un-contacted source area in the result of Fig. 7 is added with the width of contacted source area, 1.6 m.

Fig. 8. Comparison of calculated and measured parasitic linear resistance for another abnormal device. The insert shows layout and schematic circuit for the device.

We applied the schematic model including the extracted parasitic resistance of Fig. 7 to another abnormal structure. Fig. 8 shows the comparison of calculated and measured linear resistance depending on gate width for abnormal device of Fig. 1(c). The insert represents the structure of device and its schematic model. The device shows the symmetry between right and left is generated in both sides depending sides so that the same on gate width. Solid line is the result calculated by the extracted resistance from Fig. 7. The same tendency and good agreement between the measured and calculated results verify the accuracy of the model. Fig. 9 shows the measured and the calculated saturation drain current versus gate width for the forward- and reverse-modes in the structure of Fig. 1(b), respectively. As one can see, there are , two distinct regions: one region where channel resistance, dominates over the parasitic resistance and the other where the parasitic resistance dominates over the channel resistance. The saturation drain current in the former region is directly related to the gate width. The reverse-mode exhibits higher drive current than the forward-mode, and this is explained the effective gate voltage of the forward-mode is lower than of the reverse-mode due to the parasitic source resistor. The difference between the measured and the calculated current in the reverse-mode can

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Fig. 9. Measured and calculated saturation drain current as a function of gate width for forward- and reverse-modes.

be explained as relatively narrow drain-side width at the reverse-mode of actual device. MOSFET drain current is degraded by body effect charge near drain as the channel potential increment induced by conduction current produces an effective reverse body bias from the channel to the bulk [2], [10]. The resulting body effect charge can be reduced with making drain side narrow. Therefore, because the current in reverse operation was calculated with the model suggested in forward-mode, and hence, was not included above effect, the measured current in reverse operation is enhanced by narrow drain-side width than the calculated current. Through the effect of narrow drain structure, channel modification due to the parasitic resistance can be considered in our abnormal device. The abnormal device with the wide un-contacted active area can limit the drain current flow due to its large parasitic resistance. This effect induces the channel modification. The threshold voltage versus the gate width for nonsilicided abnormal devices, as shown in Fig. 5, can be attributed to the modification of channel area. A general threshold voltage model for traditional MOSFETs can be expressed as [11]–[13] (6) where

Fig. 10. Reduction rate of effective channel area depending on gate width for abnormal devices. The effective channel area is varied severly in region 2. Shaded area, S in the insert represents the asssumed effective channel area.

bulk doping concentration; are the area of the layout gate and the area of the channel which is not contributed to current flow in the abnormal structure, respectively. The silicided conventional device would hold its effective channel area for the variation of gate width. Fig. 10 shows the variation of effective channel area for abnormal devices depending on gate width. The effective channel area was estimated from (6) and (7), and the measured values. The insert in Fig. 10 represents the simple view of channel modification. , represents the assumed effective channel Shaded area, area. As the gate width becomes wider, the rate of reducing effective channel area increases in the nonsilicided abnormal devices, resulting lowering the threshold voltage. The region 2 where the effective channel is started to modify dominantly corresponds to the gate width region where linear resistance increases exponentially depending on gate width, as shown in Fig. 7. All values for silicided devices are in 10% variation. This means the silicded abnormal device shows the constant effective channel area that is nearly the same characteristics with the conventional device. and

IV. CONCLUSION

flatband voltage; Fermi potential; unit-area gate-oxide capacitance; effective gate width; effective channel length; effective bulk-charge in depletion region under the inversion channel. By considering the effect of current restriction in wider abin (6) can be normal devices, the effective bulk charge be the gate-induced depletion-layer thickness, modeled. Let is the total gate-induced bulk-depletion charge, and is the depletion charge under the inversion layer where the current flow is restricted. The effective bulk charge is represented as (7) where unit charge;

Electrical properties of abnormally structured n-MOSFET’s with 0.35 m gate length were characterized based on an analytical model that includes parasitic resistance and channel modification. The analytical model closely predicted the experiment behavior of the forward and the reverse saturation drain current and the resistance in the linear region as function of gate width up to 27.2 m. The parasitic resistance of abnormal devices with gate width up to about 8.0 m increases as a logarithmic function with gate width, while for wider devices the parasitic resistance increases exponentially. A comparison of threshold voltage of conventional and abnormal devices results led to the conclusion that the exponentially increased parasitic resistance of uncontacted active region in the wider device is the main cause of the reduction of effective channel area. The model is useful for circuit simulation when using abnormally structure MOSFETs and can also be used for physical analysis of abnormal devices.


REFERENCES [1] T. Ohzone and N. Matsuyama, “Electrical characteristics of CMOSFET’s with gates crossing source/drain regions at 90 and 45 ,” in Proc. IEEE 1995 Int. Conf. Microelectron. Test Structure, vol. 8, pp. 187–192. [2] S. C. Wong et al., “A DC model for asymmetric trapezoidal gate MOSFET’s in strong inversion,” IEEE Trans. Electron Devices, vol. 45, pp. 1459–1467, July 1998. [3] J. K. Park et al., “A characteristics tool for current degradation effects of abnormally structured MOS transistors,” in Proc. IEEE 1997 Int. Conf. Simulation of Semiconductor Processes and Devices, pp. 41–43. [4] A. El-Hennawy and Al-Ghamdi, “Performance improvement of MOSFET lasers by using trapezoidal gate MOSFET’s,” in Proc. Inst. Elect. Eng., Circuits Devices Syst., vol. 141, 1994, pp. 69–72. [5] H. Hwang, H. Shin, D. G. Kang, and D. H. Ju, “Current-crowding effect in diagonal MOSFET’s,” IEEE Electron Device Lett., vol. 14, pp. 289–291, June 1993. [6] N. G. Einspruch, Advanced MOS Device Physics. New York: Academic, 1991. [7] A. Raychaudhuri, M. J. Deen, M. I. H. King, and J. Kolk, “Finding the asymmetric parasitic source and drain resistance from the A.C. conductances of a single MOS transistor,” Solid-State Electron., vol. 39, pp. 909–913, 1996. [8] K. K. Ng and W. T. Lynch, “The impact of intrinsic series resistance on MOSFET scaling,” IEEE Trans. Electron Devices, vol. ED-34, pp. 503–511, Mar. 1987. [9] C. Duvvury et al., “An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices,” Solid-State Electron., vol. 27, pp. 89–96, 1984. [10] Y. P. Tsividls, Operation and Modeling of the MOS Transistors. New York: McGraw-Hill, 1987. [11] N. D. Arora, “Semi-empirical model for the threshold voltage of a double implemented MOSFET and its temperature dependence,” Solid State Electron., vol. 30, pp. 559–569, 1987.

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[12] J. S. T. Huang and J. W. Schrankler, “Flat-band voltage dependence on channel length in short-channel threshold model,” IEEE Trans. Electron Devices, vol. ED-32, pp. 1001–1002, May 1985. [13] E. H. Li, K. M. Hong, Y. C. Cheng, and K. Y. Chen, “The narrow-channel effect in MOSFET’s with semi-recessed oxide structures,” IEEE Trans. Electron Devices, vol. 37, pp. 692–701, Mar. 1990.

Jae-Sung Lee (A’96) was born in Kimchon, Korea, in 1964. He received the B.S., M.S., and Ph.D. degrees in electronic engineering from Kyoungpook National University, Korea, in 1987, 1989, and 1996, respectively. From 1996 to 1998, he was with Hyundai Electronics Industries, System IC Laboratory, Inchon, Korea. He was engaged in the reliability and the development of deep submicron CMOS devices. He is now an Assistant Professor at Department of Computer and Communication Engineering, Uiduk University, Kyoungju, Korea. His current research interests include reliability issues in MOSFETs, device physics, modeling and characterization.

Yong-Hyun Lee (M’93) received the B.S., and M.S. degree in electronic engineering from Kyoungpook National University, Korea, in 1975 and 1977, respectively, and the Ph.D. degree in electronic engineering from Choongnam National University, Korea, in 1991. Since 1979, he has been with Kyoungpook National University, Taegu, Korea, where he is currently a is a Professor of the School of Electronic and Electric Engineering. His current research interests include advanced device fabrication technology, novel device structures and materials, thin-film transistors, microwave devices, and display technologies. He was a Visiting Professor at the University of Arizona, Tempe, in 1983. Dr. Lee is a Member of the IEEE Electron Devices Society.