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George T. T. Sheng, Andrew C. Yen, and John L. F. Wang ... Y. Zhang, J. Xie, G. T. T. Sheng, A. C. Yen, and J. L. F. Wang are with the. Institute of ...

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001

[5] B. Yu, Y.-J. Tung, S. Tang, E. Hui, T.-J. King, and C. Hu, “Ultra-thin-body silicon-on-insulator MOSFET’s for terabit-scale integration,” in Proc. Int. Semiconductor Device Research Symp., 1997, pp. 623–626. [6] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Ultra-thin body SOI MOSFET for deep-sub-tenth micron era,” in IEDM Tech. Dig., 1999, pp. 919–921.

Gate-Induced Drain Leakage Current Enhanced by Plasma Charging Damage Siguang Ma, Yaohui Zhang, M. F. Li, Weidan Li, Joseph Xie, George T. T. Sheng, Andrew C. Yen, and John L. F. Wang Abstract—Correlation between gate-induced drain leakage current and plasma charging damage is investigated for (GIDL) current the p-MOSFETs. and maximum charge pumping current show the same trend as a function of antenna area ratio (AAR) and cell location. is mainly attributed to the increase of Si/SiO Enhancement of interface traps generated in the plasma processes and is not related to the small amount of trapped charge in the oxide. Index Terms—CMOSFET, leakage current, plasma charging damage.

I. INTRODUCTION Gate-induced drain leakage current (GIDL) [1] is a major source of off-state current. It is important to understand the causes of GIDL since it is essential to minimize the off-state current in the low-power integrated circuits. For a fresh MOSFET, GIDL is attributed to band-to-band tunneling process at Si/SiO2 interface due to the gate-induced high field at the deep-depleted gate-to-drain overlap region [1], [2]. There are also some works concerning the enhancement of GIDL as a symptom of MOS device degradation. Chen et al. [3] and Hori [4] observed that band-to-defect tunneling via the Si/SiO2 interface traps enhances GIDL in MOSFET. More recently, Wang et al. [5] and Lai et al. [6] developed an interface trap-assisted two-step tunneling model for increased GIDL after hot-carrier stress. On the other hand, Lo et al. [7] argued that both Si/SiO2 interface traps and oxide-trapped charge play important roles in the GIDL degradation. Plasma-induced damage (PID) in gate oxide has been a major concern in the manufacture of deep submicrometer MOSFETs [8]–[10]. Plasma processes can introduce constant Fowler-Nordheim (FN) current stress, which results in gate oxide degradation or even breakdown [11], [12]. Gate oxide degradation by PID may cause variations of device parameters such as threshold voltage Vth , subthreshold swing SS , transconductance Gm [8], [10], etc. Both PID and GIDL have strong relations with the gate oxide degradation. However, there is no report of plasma charging effect on GIDL. It is not obvious whether PID will Manuscript received March 14, 2000; revised October 20, 2000. This work was supported by The Singapore National Science and Technology Board Research Grant NSTB/17/2/3, RIC-University Research Project 681305 and the National University of Singapore Research Grant RP3982754. The review of this brief was arranged by Editor R. Singh. S. Ma and M. F. Li are with the CICFAR, Department of Electrical Engineering, National University of Singapore, Singapore 119260. W. Li is with LSI Logic Co., Santa Clara, CA 95054 USA. Y. Zhang, J. Xie, G. T. T. Sheng, A. C. Yen, and J. L. F. Wang are with the Institute of Microelectronics, Singapore 117684. Publisher Item Identifier S 0018-9383(01)03257-9.

Fig. 1. I -V subthreshold characteristics for p /pMOSFETs at the same cell location with different antenna area ratios (AARs). I is AAR dependent, as shown in the inset. To exclude any contribution from displacement current through the antenna, V is scanned at different speed and different direction (low to high, or high to low) to check the reproducibility of the measured current. The reproducibility is excellent. The gate current I is also monitored at the same time. I is lower than 5 10 A in all cases. The I measured at V = 0:1 V with positive V is only for reference, and can not be used to measure GIDL in this case, since the noise and I current are at the same level of I current of 10 A.

0

2

induce detectable change of GIDL, since PID is induced by area uniform current stress, while a very local region close to the drain mainly affects GIDL. This brief investigates the correlation between GIDL and PID in thin gate oxide MOSFETs. II. EXPERIMENT The devices used to evaluate the plasma charging damages were 20 m/0.4 m p+ -polysilicon gate p-channel MOSFETs with 50  A gate oxide. Different antenna structures were fabricated in metal 1 layer. An HP4156A parameter analyzer was used for device parameter extraction. Interface traps were measured using charge pumping technique [13], [14]. The gate pulses, supplied by an HP8112A pulse generator, have a fixed high level Vh and varying base level Vb with 50% duty cycle with a frequency of 200 kHz and a 50 ns/V rise/fall gradient. During the charge pumping measurement, the trapezoidal pulse is applied to the gate, the substrate is grounded, and the dc charge pumping current is measured from either drain junction or the substrate while the source junction is left floating [13]. This test configuration enables us to eliminate the contribution from the interface traps at the source junction and extract specific signal related to the interface traps for our interests concerning GIDL. III. RESULTS AND DISCUSSION

Fig. 1 shows the subthreshold characteristics for p+ =pMOSFETs with different antenna area ratio (AAR) in the same cell location. As can be seen, compared with the reference device (with no antenna), there is a significant increase in GIDL current IGIDL in the devices with antenna structure. IGIDL magnitude increases with increasing AAR. In this brief, all IGIDL are defined as drain current measured at the fixed condition of Vg = 0 V and Vd = 03:3 V. In Fig. 2(a), the IGIDL magnitudes of p+ =pMOSFETs with different AAR are plotted as a function of cell location. The measurements were carried out on seven cells along a central line across the wafer. It can be seen that IGIDL changes regularly according to the distance between the device site and

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001

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Fig. 3. Threshold voltage as a function of cell location, of devices with different AAR.

location. This means that the amount of oxide trapped charge by PID is small and random distributed in the devices. Therefore, in our case, oxide trapped charge has no major contribution to the enhancement of GIDL current. IV. CONCLUSION Fig. 2. (a) I magnitudes and (b) I magnitudes, as a function of cell location, of devices with different AAR. In the insets, a linear relationship can be observed between I and I or N .

the center of the wafer: the larger the distance, the smaller the IGIDL value. On the other hand, larger value of IGIDL can be observed for larger AAR. Since generally the MOS devices with larger AAR sustain more severe plasma damages [10], our finding shows that the enhancement of GIDL current has strong correlation with the plasma charging damage. Fig. 2(b) shows the charge pumping measurement results of the same devices on the same wafer for the GIDL measurements indicated in Fig. 2(a). As is well known [15], the maximum of the charge pumping current Icp;max is proportional to the area density of interface traps Nit . Icp;max in Fig. 2(b) shows the same trend with that of IGIDL in Fig. 2(a) as a function of AAR and device location. These observations reveal that the enhanced IGIDL has strong correlation with the increased interface traps induced by plasma charging damage. Furthermore, the inset in Fig. 2(a) shows the plot of IGIDL as a function of Icp;max , the data of IGIDL and Icp;max are collected from Fig. 2(a) and (b), respectively. A linear relationship between these two parameters is obtained. Using equation Icp;max qf Nit W L, where q is the elementary charge, f is the gate pulse frequency, W is the effective channel width, and L is the channel length, the inset curve in Fig. 2(b) leads to the following equation:

=

1IGIDL=w



1 = 6:64 1008 pA cm. This

 Nit

where W is the channel width and  2 1 relationship is in accordance with the model proposed in [4]. Since Nit measures the density of the interface traps uniformly induced in the channel region by plasma process, and IGIDL is only related to the number of interface traps located in a narrow region close to the drain, the coefficient  is likely to be dependent on the MOS device structure. We also measured the threshold voltage of the same devices on the same wafer. As seen in Fig. 3, the threshold voltages of different devices show small random shifts and no clear correlation with AAR or cell

For pMOSFETs with 5-nm gate oxide thickness, IGIDL is clearly observed as a function of AAR and cell location. Combined with the charge pumping measurements, it is verified that the enhancement of IGIDL is due to the increase of Si/SiO2 interface traps generated in the plasma processes. A linear relationship between IGIDL and the interface trap density is obtained. Oxide trapped charges induced by plasma processes are small and have no correlation with GIDL current. Therefore GIDL current enhancement is mainly due to the plasma-induced interface traps, not oxide charge. Since standby power dissipation is one of the most crucial factors for deep submicrometer MOSFET devices, care should be taken of the effect of plasma charging not only for the reliability aspects, but also for the performance degradation of devices, especially the drain current in off-state. REFERENCES [1] J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, “Subbreakdown drain leakage current in MOSFET,” IEEE Electron Device Lett., vol. ED-8, pp. 515–517, Nov. 1987. [2] H. Wann, P. K. Ko, and C. Hu, “Gate-induced band-to-band tunneling leakage current in LDD MOSFETs,” in IEDM Tech. Dig., 1992, pp. 147–150. [3] I.-C. Chen, C. W. Teng, D. J. Coleman, and A. Nishimura, “Interface-trap enhanced gate-induced leakage current in MOSFET,” IEEE Electron Device Lett., vol. 10, pp. 216–218, May 1989. [4] T. Hori, “Drain-structure design for reduced band-to-band and band-todefect tunneling leakage,” in Symp. VLSI Tech. Dig., 1990, pp. 69–70. [5] T. Wang, T. Chang, and C. Huang, “Interface trap induced thermionic and field emission current in off-state MOSFETs,” in IEDM Tech. Dig., 1994, pp. 161–164. [6] P. T. Lai, J. P. Xu, W. M. Wong, H. B. Ho, and Y. C. Cheng, “Correlation between hot-carrier-induced interface states and GIDL current increase in n-MOSFETs,” IEEE Trans. Electron Devices, vol. 45, pp. 521–528, Feb. 1998. [7] G. Q. Lo and D.-L. Kwong, “Roles of oxide trapped charge and generated interface states on GIDL under hot-carrier stressing,” in IEDM Tech. Dig., 1990, pp. 557–560. [8] J. P. McVittie, “Process charging in ULSI: Mechanisms, impact and solutions,” in IEDM Tech. Dig., 1997, pp. 433–436. (invited paper). [9] H. Shin, C. C. King, T. Horiuchi, and NAME? Hu, “Thin oxide charging current during plasma etching of aluminum,” IEEE Electron Device Lett., vol. 12, pp. 404–406, Aug. 1991.

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[10] D. Park and C. Hu, “Plasma charging damage on ultrathin gate oxide,” IEEE Electron Device Lett., vol. 19, pp. 1–3, Jan. 1998. [11] S. Fang, S. Murakawa, and J. P. McVittie, “A new model for thin oxide degradation from wafer charging in plasma etching,” in IEDM Tech. Dig., 1992, pp. 61–64. [12] H. Shin, K. Noguchi, and C. Hu, “Modeling oxide thickness dependence of charging damage by plasma processing,” IEEE Electron Device Lett., vol. 14, pp. 509–511, Nov. 1997. [13] C. Chen and T. P. Ma, “Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFETs,” IEEE Trans. Electron Devices, vol. 45, pp. 512–520, Feb. 1998. [14] W. K. Chim, S. E. Leang, and D. S. H. Chan, “Extraction of metal-oxide semiconductor field-effect-transistor interface state and trapped charge spatial distribution using a physics-based algorithm,” J. Appl. Phys., vol. 81, no. 4, pp. 1992–2001, Feb. 1997. [15] G. Groseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, “A reliable approach to charge pumping measurements in MOS transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 42–53, Jan. 1984.

be carried out at low temperature (600  C). The low-temperature metal-induced lateral crystallization (MILC) technique was proposed for obtaining large grain poly-Si thin film [4]. However, this technique might result in contamination to the poly-Si thin film. It is well known that laser (in particular excimer laser) crystallization is the most attractive method to form high-performance poly-Si thin-film at low temperature [5]–[7] compared to solid phase crystallization (SPC) [8] and rapid thermal annealing (RTA) [9]. However, excimer laser crystallization has the serious problem that the solidification velocity during the melt-growth period is too high for the film to form nuclei and to grow sufficiently. Therefore, the grain size of the poly-Si film is not large enough. Therefore, the bridge method [10] and the technique of low-temperature substrate heating during laser irradiation [11] were introduced to reduce the solidification velocity. This imposes extra requirement on the single-step laser crystallization method and makes it rather complicated. In this paper, we present a simple two-step laser crystallization method. The grain size of the poly-Si film was enlarged significantly due to the reduction of nuclei time during laser crystallization, and no substrate heating is needed.

A Novel Two-Step Laser Crystallization Technique for Low-Temperature Poly-Si TFTs Xiangbin Zeng, Zhongyang Xu, Johnny K. O. Sin, Yongbin Dai, and Changan Wang Abstract—We present investigations on a novel technique for preparing low-temperature poly-Si thin-film on glass substrate using two-step laser crystallization. In the first step, seeds are created by excimer laser induced crystallization of very thin (2–6 nm) amorphous silicon (a-Si) thin-film deposited by plasma enhanced chemical vapor deposition (PECVD). A second (a-Si) thin-film of 80–120 nm is used to obtain large crystalline grains grown around the seed crystallites during the second laser crystallization. Using this two-step crystallization (TSC) approach, we fabricated poly-Si thin-film transistors (TFTs) with electron mobility of 103 cm /V s and ON/OFF current ratio of 10 . They are two times and four times higher than those of the poly-Si TFTs fabricated in the same run using conventional single-step excimer laser crystallization. Index Terms—Laser crystallization, low temperature poly-Si, thin film transistors, .

I. INTRODUCTION Significant interest has been generated on polycrystalline silicon (poly-Si) thin-film transistors (TFTs) because of their higher field-effect mobility compared to amorphous silicon (a-Si) TFTs currently used for large-area electronics [1]–[3]. The properties of the poly-Si thin-film depend on its grain size, and large grain size is desirable. TFTs built using large grain size will have large field-effect mobility and large ON-state current. This allows the integration of the peripheral driver circuits along with the active-matrix liquid crystal display (AMLCD) on the same substrate. In order to fabricate poly-Si TFTs on glass substrate, all of the fabrication processes must Manuscript received May 5, 2000; revised November 2, 2000. This work was supported by the RGC Competitive Earmarked Research Grants, Hong Kong SAR Government, HKUST6209/98E. The review of this brief was arranged by Editor C.-Y. Lu. X. Zeng and J. K. O. Sin are with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong. Z. Xu, Y. Dai, and C. Wang are with the Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, China. Publisher Item Identifier S 0018-9383(01)03258-0.

II. DEVICE FABRICATION Fig. 1 shows the major fabrication steps of the poly-Si TFT using the two-step laser crystallization approach. The top gate structure was used. The substrate used was Corning 7059 glass. First, an a-SiNx thin-film of 300 nm was deposited using plasma enhanced chemical vapor deposition (PECVD) at 240  C and used as the passivation layer to prevent contamination of the active layer from the substrate pollutants. After that, an a-Si film of 2–6 nm was deposited using PECVD at 200  C, as shown in Fig. 1(a). The a-Si thin-film was then irradiated using the XeCl excimer laser with a power density of 235 mJ/cm2 [Fig. 1(b)] and converted to poly-Si thin-film. The wavelength of the excimer laser was 308 nm, pulse width is 28 ns, and the maximum power of a single pulse is 300 mJ. The second layer of a-Si film of 80 nm–120 nm was deposited and dehydrogenated at a temperature of 450  C in vacuum (1002 Torr) for 2 h [Fig. 1(c)]. The second a-Si film was laser crystallized using the same conditions as those stated above except that a power density of 329 mJ/cm2 was used [Fig. 1(d)]. With the crystallized poly-Si film formed, conventional top-gate TFTs were built with an a-SiNx film (200 nm) deposited using PECVD at 240  C as the gate insulator. Finally, the chromium film was deposited and patterned as the electrodes [Fig. 1(e)], and the devices were hydrogenated using H2 RF plasma for 2 hours at a temperature of 240  C, a power of 260 W, a pressure of 2 Torr, and a H2 flow rate of 70 sccm. III. EXPERIMENTAL RESULTS AND DISCUSION Channel width W and channel length L of the poly-Si TFTs fabricated using the conventional single-step crystallization (SSC) and two-step crystallization (TSC) approaches are identical with W equals to 100 m and L equals to 10 m. The grain size of the TSC poly-Si thin-film is more than 1.0 m. It is 2.5 times larger than that of the SSC poly-Si thin-film (about 400 nm). Fig. 2 shows the gate transfer characteristics of the poly-Si TFTs fabricated on the different films. The drain voltage VDS is at 10 V. The ON/OFF current ratio of the TSC-TFTs is four times higher than that of the SSC-TFTs. The drain current-voltage (I 0V ) characteristics of the different poly-Si TFTs were shown in Fig. 3. At VGS and VDS of 10 V, the drain to source current of the TSC poly-Si TFTs is over two times higher than that of the SSC-TFTs. This is because the crystallization of the poly-Si thin-film prepared by the TSC method is more efficient and effective than that by the SSC method. A summary of the parameters of the TFTs built using

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