Electronic Devices

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Introduction to

Microelectronic & Nanoelectronic Devices

Prof. Dr. Muhammad EL-SABA

2010/2011

Electronic Devices

Copyright © 2001-2010, by the author. All rights reserved. 1st Edition 2001 2nd Edition 2005 3rd Edition 2011 Reproduction or translation of any part of this work, without permission of the copyright owner, is unlawful. Requests for permission or further information should be addressed to the author, at the Dept. of Electronic Engineering, Faculty of Engineering, 1 Sarayat street, 11517Abbasia, Cairo, Egypt. E-mail Address [email protected]

-iiProf. Dr. Muhammad EL-SABA

Electronic Devices

Preface Electronic devices are widely used, in our daily life in so many applications. Witness the explosion in the uses of electronics in computers, information technology, consumer electronics, healthcare, sensing, automotive applications and communications systems, etc. This book gives an introduction to electronic devices. The book covers the curriculum of basic electronic devices and their operation principles. We chose a midway between just mentioning the final I-V or C-V characteristics of each device and their full derivation from scratch. The first approach may be more suitable for technicians rather than engineers. On the other hand, the experience showed that the full mathematical derivation of the device characteristics may deviate the attention of the student to tiny details, away from the main subject of the device principles and applications. Instead, we show the reader the physical principles, on which the device characteristics are based and demonstrate the main procedure, which is usually followed to derive these characteristics. We then explain the distinct regions on the device I-V characteristics, and the device modes of operation. We then show the main functions the device can perform in each mode of operation, such as amplification or switching. We also show the different circuit configurations of each device and its small and large signal circuit models. Finally we demonstrate some of the most important applications that exploit the device characteristics. The book is divided into 12 chapters and six appendices. The appendices contain the acronyms and the SPICE simulator models and parameters of all the devices contained in this book. In each chapter, I handle one of the fundamental devices, such as the P-N junction diode, the bipolar junction transistor (BJT) and the MOSFET. In the beginning I present the device structure and physical operation, with the least amount of mathematics for the derivation of its current-voltage (I-V) characterizes. Afterwards, I present the different possible circuit configurations of the device, its small signal and large signal AC models and its famous applications. The deviations from the ideal characteristics are also presented in this stage. Finally, I present the laboratory testing procedure as well as the device ratings and its parameters for circuit simulation. The first Chapter of this book is an introduction and revision of semiconductors and their important properties. Chapter 2 is dedicated for P-N junction diodes. At -iiiProf. Dr. Muhammad EL-SABA

Electronic Devices

the end of this chapter we introduce almost all the P-N junction related devices, such as P-I-N diode, Zener diode, tunnel diode, resonant tunnel diode (RTD), impact ionization and transient transfer (IMPATT) diode, laser diode, photodiode, and solar cells. Chapter 3 is dedicated for bipolar junction transistors (BJT’s) and the related devices, such as the heterojunctions bipolar devices (HBT). Chapter 4 includes the description of metal-semiconductor (MS) contacts and Schottky diodes. Chapter 5 is dedicated for basic field effect transistors (FET), such as Junction FET (JFET), metal-epitaxial semiconductor FET (MESFET) and high-electron mobility FET (HEMT) as well as modulation-doped FET (MODFET). Chapter 6 handles the metal-oxide-semiconductor (MOS) structures and their C-V charactieristics. Chapter 7 is dedicated for MOS transistors (MOSFET) and their characteristics and variant structures. Chapter 8 handles the power devices, including siliconcontrolled rectifier (SCR), thyristors, Diac, Triac, gate-turn-off thyristor (GTO), power BJT and power MOSFETs such as lateral diffused MOS (LDMOS) as well as insulated-gate BJT (IGBT). In Chapter 9 I present memory devices, such as static and dynamic RAM cells as well as nonvolatile memory devices. These last three chapters are dedicated for graduate students to comprehend the physical foundation of nanoscience and nanotechnology. Chapter 10 is dedicated for low-dimensional structures and quantum devices. Two-dimensional structures (such as quantum wells), one-dimensional wires and zero-dimensional quantum dots are covered. Chapter 11 demonstrates physical basis and the recent advances in nanotubes and nanodevices. Chapter 12 covers the basic principles of spintronic devices. A proper background in undergraduate-level quantum mechanics, statistical mechanics and solid state physics is required. So far, I have not found a single textbook that covers all the contents of this book. After completing this course, the student will be in a position to decide on the best way to choose the suitable device for a specific application, define its characteristics, and understand its operation. The book is typically fundamental, although it is analysis-oriented. This leaves room for students to do projects based on literature studies or their own research work. In particular, the course involves hands-on lab assignments and mini-project, to characterize the basic electronic devices. Prof. Dr. Muhammad EL-SABA Cairo in Feb. 2011 -ivProf. Dr. Muhammad EL-SABA

Electronic Devices

CONTENTS

Subject

Page

PREFACE

ii

CHAPTER 1: Introduction to Electronic Devices

1

1-1.

1-2.

1-3. 1-4. 1-5. 1-6. 1-7.

1-8. 1-9.

1-10. 1-11. 1-12. 1-13.

1-1.1. Energy levels and Energy Bands 1-1.2. Conductors and Insulators

3 3 5

Intrinsic & Extrinsic Semiconductors

7

1-2.1. n-type and p-type Semiconductors 1-2.2. Majority and Minority Carriers 1-2.3. Concentration of Electrons and Holes A- Case of n-type Semiconductors B- Case of p-type Semiconductors

8 10 12 12 12

Fermi Energy Level Drift and Diffusion in Semiconductors Generation-Recombination Mechanisms Continuity Equation in Semiconductors Semiconductor Equations 1-7.1. Homogeneous Semiconductor Equations 1-7.2. Heterogeneous Semiconductor Equations Quasi-Fermi Levels Noise in Semiconductor Devices 1-9.1. Noise Modeling i. Thermal Noise ii. Shot Noise iii. Flicker (1/f) Noise 1-9.2. Equivalent Input Noise 1-9.3. Noise Figure and Noise 1-9.4. Calculation of Noise Figure from Input Noise Technology of Semiconductor Devices Summary Problems Bibliography

14 15 19 21 22 23 23 25 28 28 28 29 30 31 31 32 33 37 39 42

Energy Band Theory in Solids

-vProf. Dr. Muhammad EL-SABA

Electronic Devices

Subject CHAPTER 2: P-N Junctions 2-1. 2-2. 2-3.

43

Chapter Overview & Learning Objectives Formation of a P-N Junction Operation of the P-N Junction 2-2.1. Forward Bias 2-2.2. Reverse Bias

2-4. 2-5.

Terminal (I-V) Characteristics of P-N Junctions Characteristics of Real P-N Junctions 2-5.1. Recombination in the Space Charge Region 2-5.2. High Injection Current 2-5.3. Avalanche Breakdown

2-6. 2-7. 2-8.

2-9.

2-10. 2-11.

2-12. 2-13. 2-14. 2-15. 2-16.

Capacitance of a P-N Junction AC Circuit Model of a P-N Junction Diode Transient Behavior of a P-N Junction Application of a P-N Junction 2-9.1. Diode as Rectifier 2-9.2. Peak Detector 2-9.3. Clipping Circuits 2-9.4. Clamping Circuits 2-9.5. Voltage Multipliers P-N Heterojunction Diodes Other Diode Structures 2-11.1. Zener Diode 2-11.2. P-I-N Diode 2-11.3. Schottky Barrier Diode (SBD) 2-11.4. IMPATT Diode 2-11.5. Tunnel Diode 2-11.6. Resonant Tunnel Diode (RTD) 2-11.7. Solar Cell 2-11.8. Photodiode 2-11.9. Light Emitting Diode (LED) 2-11.10. Laser Diode Laboratory Testing of P-N Junction Diodes Diode Ratings Computer Simulation & Modeling Parameters Summary Problems -vi-

Prof. Dr. Muhammad EL-SABA

Page

45 46 49 53 55 56 58 58 59 60 64 66 67 69

70 73 73 74 75 77 78

78 79 81 83 86 88 91 95 98 102 112 113 114 117 124

Electronic Devices

Subject 2-17. 2-18.

127 129

Chapter Assessment Bibliography

CHAPTER 3: Bipolar Junction Transistor 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7.

3-8. 3-9. 3-10.

3-11.

3-12. 3-13. 3-14.

3-15.

Chapter Overview and Learning Objectives BJT Structure Theory of Operation of the BJT BJT Circuit Configurations BJT Operating Modes BJT Currents BJT Models 3-7.1. Ebers-Moll Model 3-7.2. Gummel-Poon Model Model Static I-V Characteristics of a BJT BJT Circuit Analysis (DC Analysis) Small Signal Models of a Bipolar Transistor 3-10.1. Hybrid- Model 3-10.2. Hybrid Parameters Model BJT as an Amplifier (AC Analysis) 3-11.1. Active Mode Biasing Schemes 3-11.2. Calculation of the AC Voltage Gain 3-11.3. AC Beta Factor 3-11.4. Examples BJT as a Switch BJT Switching Times Physical Limitations of the BJT 3-14.1. Voltage Limitations (Breakdown Voltage) 3-14.2. Early Effect 3-14.3. Current Limitations (Maximum Current) 3-14.4. Variation of Gain with Collector Current 3-14.5. Kirk Effect 3-14.6. Maximum Power 3-14.7..Safe Operating Area (SOA) of a BJT 3-14.8.. Thermal Derating BJT Fabrication Technology -vii-

Prof. Dr. Muhammad EL-SABA

Page

131 133 134 136 136 137 138 148 148 149 152 155 158 158 159 161 161 162 163 165 167 170 173 173 175 177 178 179 179 180 182 185

Electronic Devices

Subject 3-16. Other BJT Structures 3-16.1. Unijunction Bipolar Transistor (UJT) 3-16.2. Hetrojunction Bipolar Transistor (HBT) 3-16.3. Resonant tunneling Bipolar Transistor (RTBT) 3-17. Laboratory Testing of a BJT 3-18. Computer Simulation & Modeling Parameters 3-19. Summary 3-20. Problems 3-21. Chapter Assessment 3-22. References CHAPTER 4: Metal-Semiconductor (M-S) Contacts 4-1. 4-2.

4-3.

4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 4-10. 4-11. 4-12. 4-13. 4-14. 4-15.

Chapter Overview & Learning Objectives Introduction to M-S Junctions 4-2.1. Workfunction of a Metal 4-2.2. Thermionic Emission Current (Richardson’s) 4-2.3. Electron Affinity in a Semiconductor Metal-n-type Semiconductor Contact 4-3.1. Case 1: m > s (Schottky Barrier Contact) 4-3.2. Case 2: m < s (Ohmic Contact) Metal-p-type Semiconductor Contact Ohmic MS Contact Tunnel MS Contact Annealed and Alloyed MS Contacts (Silicides) Small Signal Model of a Schottky Barrier Diode Capacitance of MS Structure Measurement of MS Contact Barrier Height Switching performance of the SBD Applications of MS Contacts Summary Problems References

-viiiProf. Dr. Muhammad EL-SABA

Page 189 189 191 195 197 199 200 204 208 210 211 213 213 214 215 216 222 223 223 224

225 226 228 231 231 232 236 237 238 241 244

Electronic Devices

Subject CHAPTER 5: Junction Field Effect Transistor (JFET) 5-1. 5-2. 5-3. 5-4. 5-5. 5-6.

5-7. 5-8. 5-9. 5-10. 5-11. 5-12.

Chapter Overview and Learning Objectives JFET Structure JFET Characteristics JFET Small Signal Model JFET Amplifiers Other FET Structures 5-6.1. MESFET 5-6.2. MODFET (HEMT) FET Noise Model JFET Testing Summary Problems Chapter Assessment References

CHAPTER 6: Metal-Oxide-Semiconductor (MOS) Structure 6-1. 6-2. 6-3. 6-4.

6-5.

6-6.

6-7. 6-8. 6-9.

Chapter Overvieew & Learning Objectives Energy Band diagram of an MOS MOS Flatband Voltage MOS Biasing Regimes 6-3.1. Accumulation Mode 6-3.2. Depletion Mode 6-3.3. Inversion Mode MOS Capacitance 6-5.1. Simple Model 6-5.2. Exact Analysis 6-5.3. Advanced Analysis & Quantum Effects Charge-Coupled Devices (CCD) 6-6.1. CCD Diffusion Time 6-6.2. CCD Camera Summary Problems References

-ixProf. Dr. Muhammad EL-SABA

Page 245 247 248 248 253 253 256 256 258 261 261 263 265 267 268 269 271 272 273 275 276 276 280 282 283 285 286 289 289 292 294 298 300

Electronic Devices

Subject CHAPTER 7: MOS Field Effect Transistor (MOSFET) 7-1. 7-2. 7-3. 7-4.

7-5. 7-6. 7-7. 7-8. 7-9. 7-10.

7-11.

7-12. 7-13. 7-14. 7-15. 7-16. 7-17.

Chapter Overview & Learning Objectives Types of MOS Transistors (MOSFET’s) MOSFET Structure MOSFET I-V Characteristics & Modes of Operation

7-4.1. Linear Mode 7-4.2. Saturation Mode MOSFET Sub-threshold Regime MOSFET Small Signal Circuit Model MOSFET as an Amplifier MOSFET as a Switch MOSFET Scaling MOSFET Degradation & Hot-Carrier Effects 7-10.1. Hot-carrier Injection Currents 7-10.2. Gate Tunneling Currents Advanced MOSFET Structures 7-11.1.. CMOS Technology 7-11.2. Poly-Silicon Gate Technology 7-11.3. Silicon & SiGe on Insulator (SOI & SGOI) 7-11.4. Multi-Gate and 3-D MOSFET Structures 7-11.5. Thin-Flm Transistors (TFT) 7-11.6. Active-Matrix LCD MOSFET Testing Computer Simulation & Modeling Parameters Summary Problems Chapter Assessment References:

CHAPTER 8: Semiconductor Power Devices 8-1. 8-2.

Overview and Learning Objectives Bipolar Power Devices 8-2.1. Power PIN i. PIN operation & I-V Characteristics ii. PIN Switching Characteristics -x-

Prof. Dr. Muhammad EL-SABA

Page 301 303 305 311 308 309 310 314 315 316 318 319 322 323 325 329 329 330 332 334 336 337 340 341 342 345 348 349 351 353 355 355 359 363

Electronic Devices

Subject

8-3.

Page

8-2.2. Power BJT i. Safe Operating Area (SOA) ii. Emitter Current Crowding iii. Kirk Effect iv. Switching Times & Switching losses A. Turn-ON Characteristics B. Turn-OFF Characteristics C. Switching Losses of a power BJT 8-2.3. Power Darlington Transistors 8-2.4. Thyristors i- Thyristor Structure & Operation ii- Thyristor I-V Characteristics iii- Thyristor Fabrication Techniques iv- Thyristor Packaging v- Thyristor Testing vi- Thyristor Application Circuits vii- Other Thyristor Devices 8-2.5. Diac and Triac 8-2.6. GTO iGTO Basics ii- GTO Structure iii- GTO Operation iv- GTO Switching Circuits 82.7. Integrated-Gate Control Thtristor (IGCT) MOSFET Power Devices 8-3.1. DMOS 8-3.2. LDMOS 8-3.3. VMOS 8-3.4. MCT 8-3.5. IGBT i. IGBT Structures ii. IGBT Operation

366 366 368 370 370 371 374 376 377 378 378 381 383 385 386 387 389 390 394 394 395 396 397 400 401 401 402 404 405 406 408 408

A. Forward Blocking Mode B. Reverse Blocking Mode

409 409

iii. iv. v. vi.

IGBT I-V Characteristics IGBT Circuit Models IGBT Switching Characteristics IGBT Ratings -xi-

Prof. Dr. Muhammad EL-SABA

410 412 412 413

Electronic Devices

8-4. 8-5. 8-6. 8-7.

8-8. 8-9. 8-10. 8-11.

Subject Switching Performance of Power Devices Protection of Power Devices Packaging & Thermal Design of Power Devices Applications of Power Devices 8-7.1. Rectification (AC-DC Conversion) 8-7.2. Inverters (DC-AC Conversion) 8-7.3. Converters (DC-DC Conversion) 8-7.4. Cycloconverters (AC-AC Conversion) Comparison of Power Devices & Vacuum Tubes Summary Problems References

Chapter 9: Memory Devices 9-1. 9-2. 9-3.

9-4.

9-5.

447

Overview and Learning Objectives History of Memory Technology MOSFET Memory Devices 9-3.1. SRAM Cell 9-3.2. DRAM Cell i- DRAM Reading ii- DRAM Writing ‘1’ iii- DRAM Writing ‘0’ iv- DRAM Refreshing v- DRAM Variants vi- DRAM Modules Bipolar Memory Devices 9-4.1. BJT SRAM Cell 9-4.2. Thyristor Memory Cell 9-4.3. BiCMOS SRAM Cell Nonvolatile Memory Devices 9-5.1. Basic Programming Mechanisms i- Fowler Nordheim (F-N) Tunneling ii- Hot-carrier Injection (HCI)

9-5.2. Basic Erasing Mechanisms i- UV Emission ii- Fowler Nordheim (F-N) Tunneling

9-5.3. Programming / Erasing Characteristics 9-5.4. Nonvolatile Memory Reliability -xiiProf. Dr. Muhammad EL-SABA

Page 416 421 423 427 427 429 429 430 432 434 442 445

449 451 454 454 457 461 462 462 462 464 466 468 468 468 470 471 475 475 477 478 478 479 479 480

Electronic Devices

9-6.

9-7. 9-8.

9-9. 9-10. 9-11.

Subject 9-5.5. Flash Memory Emerging Memory Technologies 9-6.1. FRAM 9-6.2. MRAM 9-6.3. PCRAM 9-6.4. TMO RAM 9-6.5. ReRAM Memory Errors: Detection & Correction Simulation of Memory Devices 9-8.1. Simulation of a MOS SRAM Cell 9-8.2. Simulation of Memory Failure Summary Problems References

Chapter 10: Low-dimensional Structures & Quantum Devices 10-1. 10-2.

10-3. 10-4.

10-5.

10-6. 10-7. 10-8. 10-9.

Introduction & Learning Objectives Two-dimensional Electron Gas (2DEG) 10-2.1. In-Plan and Vertical Transport in 2 DEG i- Schrödinger-Poisson Model ii- In-plane Conductivity of a 2DEG iii- Vertical Transport 10-2.2. Resonant Tunneling 10-2.3. Resonant Tunneling Diode (RTD) Quasi-one-dimensional (Q1D) System Quantum Dots (Q0D) 10-4.1. Classical Coulomb Blockade 10-4.2. Quantum Coulomb Blockade Single Electron Transistor (SET) 10-5.1. SET Operation 10-5.2. Accurate Measure of Charge 10-5.3. Room Temperature Operation 10-5.4. Future Perspectives Quantum-Dot Lasers Summary Problems References -xiii-

Prof. Dr. Muhammad EL-SABA

Page 481 485 485 487 489 492 493 495 496 496 498 500 505 507 509 511 513 515 516 518 519 519 520 522 523 526 529 530 533 536 537 539 540 542 544 545

Electronic Devices

Subject Chapter 11 Nanowires, Nanotubes and NanoDevices 11-1. 11-2. 11-3. 11-4. 11-5.

Overview & Learning Objectives Nanotechnology & Nano Effects Nanowires Silicon Nanowire Transistor (SiNWT) Carbon Nanotubes 11-5.1 Single-Wall Naotubes (SWNTs) 11-5.2 Energy Band Structure of SWNT’s 11-5.3 Transport of Charge Carriers in SWNT’s 11-5.4. Stuffed Single-Wall Nanotubes (SSWNTs) 11-6. Nanotube Devices 11-6.1, Nanotube FET (NTFET) 11-6.2, Complementary Nanotube FET (CNTFET) 10-6.3, Nanotube Solar Cells 10-6.4, Nanotube Memory 11-7. Other Applications of Nanotechnology 10-7.1.Electronics, Communications & Computer 10-7.2. Biomedical Applications 10-7.3. Water Purification & Environmental 10-7.4. Toxicology of Nanotubes 11-8. Nano-electromechanical Systems (NEMS) 11-8.1. NEMS functions 11-8.2. Nano-Machines 11-8.3.Nano-Optoelectronic Systems (NOEMS) 11-8.4. Challenges of NEMS 11-8.5. How to fabricate NEMS 11-9. Summary 11-10. Problems 11-11. References Chapter 12: Spintrobic Devices 12-1. 12-2. 12-3.

547 549 549 552 555 557 558 561 565 568 570 571 573 576 578 579 580 584 585 586 587 588 588 589 590 592 594 596 598 601

Overview & Learning Objectives

Magnetic Semiconductors Spin Relaxation Mechanisms 12-3.1. D’yakonov-Perel (DP) Mechanism -xiv-

Prof. Dr. Muhammad EL-SABA

Page

603 605 608 608

Electronic Devices

Subject 12-3.2. Bir-Aranov-Pikus (BAP) Mechanism 12-3.3. Elliot-Yafet (EY) Mechanism 12-3.4. Rashba Effect 12-3.5. Other Mechanisms

12-4. 12-5. 12-6.

Spin Relaxation Time Spin Transport Equations Spintronic Devices 12-6.1. 12-6.2. 12-6.3. 12-6.4. 12-6.5. 12-6.6. 12-6.7. 12-6.812-6.9.

12-7. 12-8. 12-9. Appendices Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F

Spin Injectors Spin Aligners & Filters Spin Detectors Spin FET Magnetic Bipolar Transistor (MBT) Magnetic Tunnel Transistor (MTT) GMR MRAM MRI

Summary Problems References

List of Symbols SPICE Model of a P-N Junction SPICE Model of a BJT SPICE Model of a JFET SPICE Model of a MOSFET SPICE Model of an IGBT

608 608 609 609 610 612 614 614 615 615 616 616 619 620 621 622 624 626 627 629 631 635 637 639 643 647 649

Acronyms

-xvProf. Dr. Muhammad EL-SABA

Page

Microelectronic & Nanoelectronic Devices

Chapter 1

Introduction to Electronic Devices Contents: 1-1.

Energy Band Theory in Solids 1-1.1. Energy levels and Energy Bands 1-1.2. Conductors and Insulators

1-2.

Intrinsic & Extrinsic Semiconductors 1-2.1. n-type and p-type Semiconductors 1-2.2. Majority and Minority Carriers 1-2.3. Concentration of Electrons and Holes A- Case of n-type Semiconductors B- Case of p-type Semiconductors

1-3. 1-4. 1-5. 1-6. 1-7.

Fermi Energy Level Drift and Diffusion in Semiconductors Generation-Recombination Mechanisms in Semiconductors Continuity Equation in Semiconductors Semiconductor Equations 1-7.1. Semiconductor Equations in Homogeneous Semiconductors 1-7.2. Semiconductor Equations in Heterogeneous Semiconductors

1-8. 1-9. 1-10. 1-11. 1-12. 1-13.

Quasi-Fermi Levels Noise in Semiconductor Devices Technology of Semiconductor Devices Summary Problems References

-1Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

-2Prof. Dr. Muhammad El-SABA

Chapter 1

Microelectronic & Nanoelectronic Devices

Chapter 1

2

Introduction to Electronic Devices In this chapter, we summarize some fundamental concepts about semiconductors, which are used to fabricate electronic devices. We briefly demonstrate how to exploit these properties to make useful electronic devices and integrated circuits. Upon completion of this Chapter, students should: Understand the fundamentals of solid-state physics, such as the energy band theory, the electron drift and the concept of holes, which are necessary for the comprehension of electronic devices. Review the fundamentals of semiconductors and carrier transport equations, which are necessary for the analytical description of the operation of semiconductor devices. Be acquainted with the appropriate approaches in device modeling. 2-1. Energy Band Theory in Solids Transistors, diodes, integrated circuits and many solid-state electronic devices have semiconductor technology in common. Before looking at how these devices work, it is necessary to have a basic understanding of conductors, insulators and semiconductors. 1-1.1. Energy Levels and Energy Bands in Solids In isolated atoms, the electrons are arranged in orbits with strict numbers of electrons and are orbiting around their nuclei with certain energy levels. For instance, the Si atom has 14 electrons; the first orbit (1s2) only contains two electrons, and the second (2s2 and 2p6) has eight the third (3s2 and 3p2) has four electrons. In this case, the relation between the electron energy, E, and the electron wave-vector, k, consists of a set of discrete (quantized) points in the k space. When isolated atoms are brought together, to form a crystalline solid, various interactions (due to attraction and repulsion forces) occur between neighboring atoms. At the position of equilibrium, the forces of attraction and repulsion between atoms are balanced and the total potential energy of the system becomes minimal. The adjacent atoms of most intrinsic semiconductors, like Si, are bonded with covalent bonds. -3Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

As the electron clouds of individual atoms are overlapped, the height of potential wells of different atoms is lowered and electrons of higher energies are no longer belonging to a specific atom. As a consequence of the overlapping process, the electron energy levels are split into dense groups of levels, known as energy bands. Usually, these energy bands are separated by successive forbidden regions, that we call energy gaps.

(a)

(b)

Fig. 1-1. Schematic representation of the diamond lattice and its atoms (a), and a twodimensional representation of the covalent bond (b)

Fig. 1-2. Schematic of energy level splitting and formation of energy bands in a diamond crystal of N atoms as a function of inter-atomic distance R.

-4Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

Figure 1-2 shows the development of the one-electron energy bands in diamond crystals from the discrete energy levels of an isolated atom. As shown in figure, when the separation between atoms is decreased, the energy levels of single atoms (1s, 2s, etc.) are split into bands of a huge number of adjacent energy levels. Figure 1-3, depicts the energy band diagram at the state of equilibrium. The highest filled energy band, in the energy band diagram, is usually called: the valence band. Also, the energy band just above the valence band is called the conduction band. The valence band and the conduction band are separated by a region called the energy gap. The height of energy gap is given by:

Eg = Ec - Ev

(1-1)

where Ec is the lowest (bottom) level in the conduction band and Ev is the highest (top) level in the valence band. So, in crystalline solids, the E-k relation, at a certain point in the physical crystal lattice, is characterized by a sequence of alternating allowed energy bands and energy gaps. The E-k relation of electrons inside a solid crystal, in the various directions of the k-space, is usually called the energy band structure of that solid. E Energy gap

Conduction Band

Ec

Eg

Ev

Band of allowed energy levels

Valence Band V.B.

Fig. 1-3. Schematic of the energy band diagram (versus crystal spatial position).

1-1.2. Conductors and Insulators In terms of electricity there are two main classes of material: namely: conductors and insulators. From their names it can be gathered that conductors will conduct electricity, whereas non-conductors act as insulators preventing the flow of an electric current. -5Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

An electric current is made up of the flow of free electrons. This means that for a current to flow, the electrons must be able to move freely within the material. At any instance, such free electrons are moving freely but randomly. By placing a potential difference across a conducting material the free electrons can be drifted in a certain direction and this constitutes an electric current. Metals are all conductors of electricity, and a number of other substances also conduct it to varying degrees. Other substances do not have free electrons moving around the lattice. Electrons are firmly held within their atoms and cannot escape easily. Accordingly when a potential is placed across the substance very few electrons will move and very little or no current will flow. These substances are called insulators.

Fig. 1-4. Classification of solids into conductors, semiconductors and insulators.

-6Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

1-2, Intrinsic & Extrinsic Semiconductors As the name suggests a semiconductor is neither a true conductor nor an insulator, but half way between. A number of materials exhibit this property, and they include germanium (Ge), silicon (Si), gallium arsenide (GaAs), and a variety of other substances. To understand how it acts as a semiconductor it is necessary to first look at their atomic structure. For instance, let‘s jet a look at the silicon material as an example of semiconductors. The electrons in the outer shell of silicon are shared to make up a crystal lattice, with covalent bond, as shown in Fig.1-5. When this happens there are no free electrons in the lattice, making silicon a good insulator at zero absolute temperature.

Si

Si

Si

Si

Si

Si

Figure 1-5. Illustration of the covalent bond

A similar picture can be seen for Ge. It has also four electrons in the outer shell. Thus, at absolute zero temperature, the crystal lattice of such elements has no free electrons and these elements behave as insulators. However, at room temperature (about 300K) some of the shared electrons will have enough energy to break their covalent bonds (and overcome the energy gap between the valence band and the conduction band) and roam freely in the crystal. The density of the quasi-free electrons in a semiconductor is called the intrinsic carrier concentration of that semiconductor, and termed by ni. These free (or quasi free) electrons can only convey a very small current if the semiconductor is subjected to an electric field. Such pure (undoped) semiconductors are called intrinsic semiconductors.

-7Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

1-2.1. N-type and P-type Semiconductors The conductivity of semiconductors changes very significantly by adding small amounts of impurities. Doped semiconductors are called extrinsic semiconductors, and their conductivity depends on the type of added impurities. If traces of impurities of 5th-valent materials (having five electrons in the outer shell, like phosphorous) are added they increase the number of electrons in the crystal lattice of the semiconductor. The extra electron in the outer shell, becomes almost free to move around the lattice. This increases the number of free electrons and enables an appreciable current to flow if a potential is applied across the semiconductor material. As this type of semiconductor materials has extra electrons in the lattice it is called N-type semiconductor. Typical impurities that are used for doping N-type semiconductors are phosphorous (P) and arsenic (As). Such impurities are called donors. It is also possible to place elements with only three electrons in their outer shell into the crystal lattice. When this happens the silicon wants to share its four electrons with another atom with four atoms. However as the impurity has only three, there is a space or a hole for another electron. As this type of material has electrons missing it is known as P-type material. Typical impurities used for doping P-type material are boron (B), and aluminum (Al). Such impurities are called acceptors.

Semiconductor

Intrinisic n= p

Extrinsic n p

n-type n>p

p-type p>n

Fig. 1-6. Types of semiconductors.

-8Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

Fig. 1-7. Doping elements.

Example 6-2 What is the Arsenic weight to be added to a 100 gm of silicon melt to produce a 1017 electron/cm3 n-type silicon? Solution In a 100 gm of Si there are N atoms such that. N(Si) = Weight of Si [gm] / Weight of one Si atom [gm] where the weight of Si atom = Atomic weight of Si / Avogadro‘s number = 28 [amu/Si atom] / 6 x 1023 [amu / gm] = 4.67x10-23 [gm] Thus, N(Si) = 100[gm] / 4.67x10-23[gm] = 2.14 x 1024 atom The density of Si atoms is equal to 5x1022 atom/cm3 and the density of As atoms needed is 1017 atom/cm3, then the number of As atoms needed is:

1017 [atom / cm3 ] 24 N ( As)  [atom]  4.28 x 1019 atom 22 3 x 2.14 x10 5x10 [atom / cm ] The required weight of As needed is then given by: Weight (As) [gm] = N(As) [atom] x Weight of one As atom [gm/atom] where the weight of As atom = Atomic weight of As / Avogadro‘s Number = 75 [ amu] / 6x1023 [amu/gm] = 1.25 x 10-22 [gm] Hence, Weight (As) = 4.28x1019 [atom] x 1.25 x 10-22 = 5.35 x 10-3 [gm] -9Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

1-2.2. Majority and Minority Carriers It is easy to see how electrons can move around the lattice and carry a current, under the effect of electric field. However it is not quite obvious for vacant places or holes. This happens when an electron from a complete orbit moves to fill a hole, leaving a hole where it came from. Another electron from another orbit can then move in to fill the new hole and so forth. The movement of the holes in one direction corresponds to a movement of electrons in the other, hence an electric current. Hole

Fifth Electron

Donor Atom

Acceptor Atom

Fig. 1-8. Basic bond pictures of N-type and P-type semiconductors

Therefore, both electrons and holes can carry charge and drift, under the effect of electric field, resulting in an electric current. Consequently, both electrons and holes are known as charge carriers. Holes are the majority charge carriers for a P-type semiconductor and electrons are majority carriers for an N-type semiconductor. In an N-type semiconductor, the donor impurities create a donor energy level Ed, in the energy gap, of the semiconductor. The donor ionization energy Eid is equal to the energy required for transition from Ed to Ec, or

Eid (donor ) = Ec - Ed

(1-2)

As for the most of V-group impurities Ed is close to the bottom of conduction band, and Eid is only few milli electron volts (44 meV for P in Si). Such impurities are called shallow levels impurities. Similarly, the acceptor impurities create an acceptor energy level Ea, in the energy gap, of the semiconductor. The acceptor ionization energy Eia is equal to the energy required for transition from Ev to Ea , or Eia (acceptor) = Ea - Ev -10Prof. Dr. Muhammad El-SABA

(1-3)

Microelectronic & Nanoelectronic Devices

Chapter 1

For most III-group impurities, Eia is in the order of 10m eV, so that Na-  Na at room temperature. The following figure depicts the energy band diagram of P -type and N -type semiconductors, with their acceptor and donor energy levels. Note that the relative density of ionized donors, (Nd+/Nd) is a function of temperature. Also, the relative density of ionized acceptors, (Na-/Na) is a function of temperature, as indicated in the figure below.

(a) Acceptors (in p-type)

(b) Donors (in n-type)

Fig.1-9. Energy levels and partial ionization of acceptor (a) and donor (b) impurities

Fig.1-10. Relative density of ionized donors (P in Si), as a function of temperature.

-11Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

1-2,3, Concentration of Electrons and Holes in Semiconductors According to the neutrality condition in a semiconductor we have:

no  N a  po  N d

(1-4)

where no and po are the density of electrons and holes in the semiconductor at equilibrium. Also Nd+ and Na- are the densities of ionized donors and acceptors in the semiconductor, respectively. Also, the mass-action law dictates that

no . po  ni2

(1-5)

where ni is the intrinsic-carrier concentration 34

* *   m m nd pd 15   T 3 2 exp ni  4.82  10 2  m  o  

 Eg     2k BT 

(1-6)

where mnd* is called the density-of-states effective-mass in the conduction band , m*pd is the valence band density-of-states effective-mass, and mo is the rest mass of electrons in free space (9.1x10-31 kg). In Si, mnd* = 1.08 mo and m*pd = 0.81 mo. The following figure shows the intrinsic carrier concentration of Si, Ge, and GaAs as a function of temperature. A- Case of Intrinsic Semiconductors In intrinsic semiconductors, the number of electrons is equal to the number of holes (vacant places or broken bonds). Therefore, in thermal equilibrium we have:

no  po  ni

(1-7)

B- Case of Extrinsic Semiconductors By solving the above algebraic equations, we can calculate no and po

no 

N

 d



  2n  N a  1  1    i   2  Nd  Na  -12-

Prof. Dr. Muhammad El-SABA

   

2

   

(1-8a)

Microelectronic & Nanoelectronic Devices

po

N 

 a



  2n  N d  1  1    i   2  Na  Nd 

Chapter 1

   

2

   

(1-8b)

where the  sign (inside the square brackets) stands for the type of majority carries. That is the + sign is taken when we calculate no from (16a) in n-type materials or po from (1-6b) in p-type materials.

Fig 1-11. Intrinsic carrier concentrations of Si, Ge and GaAs versus temperature.

-13Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

Similarly, for n-type semiconductor (Na- = 0), we have: 2   2ni   N d  no  1  1      N d , 2   N d   

ni2 nd2 po   no N d

(1-9)

Also, for p-type semiconductor (Nd+=0), we have: 2   2ni   N a  po  1  1      N a , 2   N a   

ni2 nd2 no   po N a

(1-10)

1-3. Fermi Energy Level The Fermi level (EF) is a reference energy level, which is typically used in the energy band diagram to illustrate the type of semiconductors and how they are populated with charge carriers. The difference between the Fermi energy and the vacuum level of any material is termed the workfunction (m = Eo - EF). The Fermi energy level in non-degenerate (not highly-doped) semiconductors is situated inside the energy gap. In N-type semiconductors, EF is situated near the conduction band edge (Ec) meaning the number of electrons is greater than the number of holes. Also, In P-type semiconductors, EF is situated near the valence band edge (Ev) meaning the number of holes is greater than the number of electrons. However, in both cases, the Fermi level position is a unction of temperature.

Intrinsic semiconductor, n-type semiconductor, p-type semiconductor Fig. 1-12. Variation of the Fermi level position with temperature, in semiconductors

-14Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

The density of electrons and holes can be expressed in terms of the distance between EF and the band edges as follows:

 E  EF  no  NC exp  C  k BTL  , 

 E  Ev  po  NV exp  F  k BTL  

(1-11)

where NV and NC are the effective density of states in the conduction band and valence band, respectively. Also, kB is the Boltzmann constant and TL is the semiconductor crystal lattice temperature. It should be noted that the Fermi level (or chemical potential) of any two solids in contact must be equal in thermal equilibrium. 1-4. Drift and Diffusion Currents in Semiconductors The motion of free charge carriers (electrons and holes) in a solid semiconductor is different from the motion in free space because of collisions with the vibrating nuclei of the solid. If an electric field  is applied to a semiconductor, the free electrons will be affected by a force F=-e. and they begin to drift against the field, as shown in Fig. 1-13.

Fig. 1-13. Scattering and drift of electrons under the effect of electric field.

If the concentration of free electrons in the conduction band of the semiconductor is n (electrons/cm3) and their average drift velocity is vn, then the electron current density Jn (A/cm2) is given by:

Jn = - e n vn = n . -15Prof. Dr. Muhammad El-SABA

(1-12a)

Microelectronic & Nanoelectronic Devices

Chapter 1

where n = - e n (vn /  ) is called the electrical conductivity of electrons. Unlike metals the conductivity of semiconductors depends actually on many ambient parameters such as temperature, illumination, etc. Regarding the electrons in the valence band, it is more convenient to consider the motion of holes instead. This is because the number of holes is usually much less than the number of valence electrons. If we have a Ptype material with p holes (vacant bonds) per cm3 in the valence band, then the current produced by the motion of valence electrons to fill in these holes is equal to the current produced by the motion of holes, along the field direction. Therefore, the hole current density Jp is given by:

Jp = e p vp = p 

(1-12b)

where p = e p (vp /  ) is called the electrical conductivity of holes and vp is their average velocity.

Fig. 1-14. Drift of electrons and holes under the effect of electric field.

It comes out from the above discussion that the steady-state carrier drift velocity is proportional to the electric field. The constant of proportionality between the carrier drift velocity vdrift and the electric field called the carrier drift mobility and termed by 

vdrift = ±  

with

= e  / m*



is

(1-13)

where m* is the effective mass of charge carriers and  is the mean time between collisions. The mobility of electrons is denoted by n and the mobility of holes is denoted by p. -16Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

Thus, we can write: vn (drift) = - n 

for electrons

vp (drift) = + p 

for holes

(1-14a) (1-14b)

The total drift current density is given by the sum of electron and hole drift current densities:

Jdrift = Jn(drift) + Jp(drift) =  

(1-15)

where  = n +p = enn + epp is the total conductivity of electrons and holes of the semiconductor. When there exists a spatial variation of carrier concentration (electrons or holes), carriers will move from the location of higher concentration to the location of lower concentration. This process is called the charge carrier diffusion. The current resulting from the diffusion of electrons (or holes) is proportional to their gradient such that:

Jn, diffusion = e Dn  n

(1-16a)

Jp, diffusion = -e Dp  p

(1-16b)

where the constants of proportionality Dn and Dp are called the diffusion coefficients of electrons and holes, respectively. Note that in onedimension, the gradient operator is replaced by the differentiation d/dx.

Figure 1-15. Diffusion of electrons in a semiconductor.

-17Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

According to Einstein relations, the carrier diffusion coefficient is proportional to the carrier drift mobility such that: Dn/n = VT ,

Dp/p = VT

(1-17)

where VT = (kB TL/e) is the thermal voltage When both carrier-concentration gradient and electric field are present in a semiconductor, the resultant current is the sum of carrier-drift and carrier-diffusion currents.

Jn = Jn, drift+ Jn, diffusion = en n + e Dn n

(1-18a)

Jp = Jp, drift +Jp, diffusion = e p p  - e Dpp

(1-18b)

The above current equations are the basis of the so-called drift-diffusion model (DDM) of semiconductors.

-18Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

1-5. Generation-Recombination Mechanisms in Semiconductors When the thermal equilibrium state is disturbed in a semiconductor, by the influence of external force (e.g. via an optical excitation), the charge carrier densities (n, p) change from equilibrium values (no, po) so that

n = no +  n ,

p = po +  p

(1-19)

where the quantities n and p are called the excess carrier concentrations. Hence at non-equilibrium:

n.p  ni2

(1-20)

Both n and p may be positive (due carrier injection into the semiconductor) or negative (due to carrier extraction from the semiconductor). When there is an excess carrier concentration, the semiconductor will try to restore its equilibrium state by endeavoring carrier generation or carrier recombination processes. At the thermal equilibrium state, the thermal generation rate (of electronhole pairs), gth, is compensated by a default recombination rate (of electron-hole pairs), Ro, such that the net recombination rate U = Ro - gth is null (zero) and there exists no excess carriers.

Figure 1-16. Generation & recombination mechanisms in a semiconductor. C.B stands for the conduction band and V.B. stands for the valence band of the semiconductor.

-19Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

When n and p are negative, meaning that np < ni2 , then the thermal generation mechanism gth (which takes place regardless of the presence of excess carriers) will dominate the default recombination Ro to restore the equilibrium state. On the other hand, when n and p are positive, meaning that np > ni2, then the recombination mechanism will dominate the thermal generation. Therefore, the net recombination rate of electrons and holes is given by:

Un  Rn  gth 

n

n

,

U p  R p  g th 

p

p

(1-21)

where n and p are called the electron and hole lifetimes, respectively. As shown in figure 1-8, the recombination of charge carriers, may be direct (radiative) or indirect (non-radiative). In the former case, the recombination is associated with emission of a photon with equivalent energy of the energy gap. In the later case, the recombination, releases smaller energy, which is transmitted to crystal lattice vibrations. When a semiconductor is doped with impurities that produce profound energy levels in the energy gap (like gold, Au), these levels will act as trapping centers for carries. Therefore, carriers will prefer to transit for a while at these trapping levels during their transitions between conduction and valence bands. In such a case, the steady-state rate of indirect recombination in the bulk of a non-degenerate semiconductor is given by the following Shockley-Read-Hall expression:

U SRH

np  ni2   po ( p  p1 )   no (n  n1 )

(1-22)

where no and po are the minority carrier lifetimes in heavily-doped semiconductors. They can be defined in terms of the density of traps Nt [cm-3] and the capture rates of electrons and holes Cn, Cp [cm3/s] as follows:

 no 

1 Nt Cno

 po 

-20Prof. Dr. Muhammad El-SABA

1 Nt C po

(1-23)

Microelectronic & Nanoelectronic Devices

Chapter 1

1-6. Continuity Equations When the thermal equilibrium state in a semiconductor is disturbed, the net recombination rate of carriers (U=R-G) is non zero. Therefore, the density of carriers will change with time. The continuity equations for electrons and holes in a semiconductor read:

n 1  (Gn  Rn )  . J n t e p 1  (G p  R p )  . J p t e

(1-24a)

(1-24b)

where the electron and current densities, (Jn and Jp), can be expressed by equations (1-16a) and (1-16b), respectively.

Figure 1-17. Charge continuity in a semiconductor.

-21Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 1

1-7. Semiconductor Equations By substituting the electron current density expression (1-16) into the continuity equation (1-24) and assuming the electron mobility is constant, we obtain the following equation for electrons in the x-direction:  n   t   Gn  Rn x





x

 x n  n n   n x   Dn x x

 2 npx x 2

(1-25a)

Similarly, the continuity equation for holes in the x-direction reads:



 p   t   Gp  Rp x



x

 p p

 x p  2 pnx  p x  Dp x x x 2

(1-25b)

In order to solve the above 2 equations in (n, p and x ), they must be complemented by the Poisson equation which relates the carrier densities n, p with the electric field x or potential  (x = -d/dx). .D  

 2 e  ( n  p  N d  N a ) 2  x

or

(1-26a)

where  is the electric charge density, D = is the electric field displacement vector1, or is the permittivity of the semiconductor and r being its relative value. In 3-dimensions, the Poisson equation reads:

 2  

p  e

 n  N d  N a



(1-27b)

When the density of trapping centers Nt in the semiconductor is significant, it must be included in the Poisson equation, so that: 2  

p  e

 n  N d  N a  N t 

(1-27c)

Also the time variation of trap density could be described by an additional continuity equation that must be added to the previous set of semiconductor equations. N t  U p -U n = (G p  R p ) - (Gn  Rn ) t 1

(1-28)

In case of polar semiconductors, D = (+P), where P is the polarization vector.

. Prof. Dr. Muhammad El-SABA

-22-

Microelectronic & Nanoelectronic Devices

Chapter 1

In addition, if the external bias and hence the electrostatic potential and electric field are time variant, the total current density should be appended by the so-called displacement current such that J = Jn+ Jp,+Jd, where Jd = ∂ /∂t . When the variation of trap density with time is not important (when no fast states are present in the semiconductor), then one can set Up=Un in the above set of equations. 1-7.1. Semiconductor Equations in Homogeneous Semiconductors The continuity equations (1-21a), (1-21b) together with the Poisson equation (1-27) are called the semiconductor equations. When these equations are coupled, with the current equations (1-16), they form the so-called drift-diffusion model (DDM). In this model, we assume a constant carrier temperature, which is equal to the lattice temperature. Therefore, it should be noted that the current equations (1-16) are only valid for homogenous semiconductor structures at low electric fields. 1-7.2. Semiconductor Equations in Heterogeneous Structures There exist so many semiconductor devices which comprise different semiconductor materials and heterojunctions. The central feature of heterojunction devices is that the bandgaps of the participating semiconductors are usually different. Figure 1-18 depicts the energy band diagram of a heterojunction of two different semiconductors. The alignment of energy bands of different semiconductors may be ruled by the Anderson rule. According to this rule, the energy of the carriers of at least one of the band edges must change as carriers pass through the heterojunction. Therefore, in heterojunction devices and heterostructures the semiconductor properties vary with position. If a heterojunction is made between two materials for which there exists a continuum of solid solutions, such as AlxGa1-xAs with 0 0.5V. When the applied bias is greater than 0.8V, the Ohmic drops across the quasi-neutral regions should be considered and added like a series resistance. Note that the onset of the high injection regime depends on the semiconductor material, which is utilized to fabricate the P-N junction 2-5.3. Avalanche Breakdown At sufficient high reverse bias (near a certain threshold, called the breakdown voltage VB) the reverse current increases abruptly. This abrupt increase in reverse current is due to the multiplication of high energy charge carriers, by impact ionization, in the depletion region. Impact ionization is characterized by a parameter called the impact ionization coefficient (n and p for electrons and holes, respectively). It is logic to expect that the ionization coefficients would be a function of carrier energy and the electric field. For instance, one may simply consider n = p = 1.8 x 10-26 ζ 7 in silicon. When increasing the reverse bias voltage, the reverse current gets multiplied by the avalanche multiplication process. The reverse current multiplication factor (M), across the space charge region is related to the ionization coefficients () by the following relation (for electrons).

89 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

(2-19a)

Similarly, the multiplication factor for holes is given by: (2-19b)

Here xn and xp are the space charge widths in the N- and P-sides (equivalent to Wn and Wp). When the avalanche multiplication becomes large (M∞), a very large reverse current begins to flow. Consequently, the device may breakdown, unless a series resistance is connected to limit current. The expression for multiplication factor shown above suggests that multiplication can be empirically modeled as follows:

M = [1 – (V/VB)n ]-1

(2-19c)

The exponent n depends on the P-N junction structure (n≈4 for abrupt silicon P+-N junction).

Fig. 2-11. Multiplication factor in silicon diode (APD) as a function of voltage,

The breakdown criteria (VVB and M∞) may be simply written as follows, when n = p = eff :

∫ aeff .dx = 1 90 Prof. Dr. Muhammad El-SABA

(2-19d)

Fundamentals of Electronic Devices

Chapter 2

where the integration is taken along the space-charge region (-xn > x > xp). According to Fulop, the effective impact ionization coefficient is given by

aeff .= ao ζ7

(2-19e)

For silicon we have, ao is about 1.8x10-38 cm6/V. This law is useful to derive a closed-form of the breakdown voltage of P-N junctions.

Fig. 2-12. Illustration of the impact ionization process and breakdown in P-N junctions

Fig. 2-13. Impact ionization coefficient in silicon as a function of electric field,

For Si, the maximum electric field at breakdown is then given by: 7/8

ζc = 4010 x NI 91 Prof. Dr. Muhammad El-SABA

(2-20a)

Fundamentals of Electronic Devices

Chapter 2

Also, the space charge region width at breakdown is given by:

WB = 2.67 x 1010 NI -7/8

(2-20b)

The breakdown voltage of an abrupt P-N junction may be then expressed as follows:

VB = 60 (Eg /1.1)3/2 (NI /1016)-3/4

(2-21)

Here NI is the doping concentration of the low-doped side of the P-N junction, where the depletion region has a wider extension. The following figure depicts the breakdown voltage of abrupt P-N junctions of different semiconductors, as a function of doping. Note that the above relation is only valid for long abrupt P-N junctions, where the low-doped side is not entirely depleted. As the depletion region width increases with applied reverse voltage, it is desirable to increase the diode base length in order to have a high breakdown voltage. However, increasing the base width will increase the Ohmic drop across the P-N junction in forward bias.

Fig. 2-14. Breakdown voltage of abrupt P-N junction, as a function of doping.

In order to cope with this problem, the low-doped base region of the diode is usually followed by a highly doped layer, before the contact region. If the diode base layer is completely depleted the space charge region becomes trapezoidal, as shown in figure 2-15. In this case, the 92 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

diode is called a punch-through diode. Therefore, the diode can support more applied reverse bias, without need to increase the base width. The breakdown of a punch-through diode is related to the breakdown voltage of a long (abrupt junction) diode, VB, by the following relation:

VBPT = 2VB (Wb/W).[ 1 - ½(Wb/W ) ]

(2-22)

where W is the depletion region width, as given by equation (2-11), and Wb is the base length of the punched-through diode.

Fig. 2-15. Long diode & punch-through diode and their field distribution at high reverse bias

The above discussion is valid for one-dimensional diodes. Such one dimensional junction diodes can be obtained by crystal growth or by beveling the diffusion junction sides. The beveled P-N junction structure is sometimes called the MESA diode. In planar technology, the diffused junctions will have either a cylindrical or spherical sides. As the potential lines become closer near the junction corners, the electric field is higher at the junction sides and the breakdown takes place there, at voltage well below the values calculated for one-dimensional diodes. The relative breakdown voltage (VBC/VB) of cylindrical and spherical junctions, as a function of the curvature (rj/W) is shown in figure 2-16.

93 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

Fig. 2-16. Planar P-N junction and doping profile

For instance, the relative breakdown cylindrical junction voltage (with respect to plane abrupt junction) may be expressed as follows: (2-23)

Fig. 2-17. Relative breakdown voltage of cylindrical and spherical Silicon junctions (with respect to plane abrupt junction).

2-6. Capacitance of a P-N Junction We have seen so far that there is a charge separation in the transition region of a P-N junction. This transition region behaves like a capacitor, and the capacitance is given by:

 e o  s  N a .N d  CT   A.   W 2 V  V a  Na  Nd  bi

 o A

    

1/ 2

(2-24a)

where A is the cross section area of the P-N junction and the transition region width W = Wn+Wp. Therefore, the capacitance can be varied by changing the applied voltage (Va). In practice, reverse bias is 94 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

needed so that the current flow is small. The P-N junction device, which is used as a voltage-variable capacitor, is known as a varactor diode. The capacitance of a reverse-biased P-N junction is sometimes called the transition capacitance. The transition capacitance of an abrupt P-N junction may be put in the following form:

CT 

CTo V  1   a   Vbi 

with CTo 

 o s A 2 o s e

 Na  Nd   N a .N d

  Vbi 

(2-24b)

For instance, if we have a Si diode with cross section A=10-3 cm2, Na = 1018 cm-3; Nd = 1015 cm-3, s= 11.7, Vbi= 850 mV, then CTo 10pF. In forward bias, one can also observe another capacitance called diffusion capacitance, due to excess stored charges, Qs, across the two sides of the P-N junction. The diffusion capacitance of a forward-biased P-N junction, Cd, is given by:

Cd 

dQs dQs dI d  a  .  dVd dId dVd rd

(2-24c)

where rd = dVd/dId is the forward dynamic resistance of the P-N junction and a = Qs/Id is the average lifetime of minority carriers, in the two sides of the junction. The following figure depicts the variation of the junction capacitance (Cj=CT+Cd) as a function of the applied voltage. As shown in the following figure this variation depends on the diode doping profile.

95 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

Fig. 2-18. Transition and diffusion capacitances of a P-N junction

Practically, the P-N junction capacitance varies with bias as follows:

Cj 

C jo   Va  1      Vbi 

m

(2-24d)

where the index m depends on the doping profile. For Si we have m= ½ for abrupt doping profile and m =1/3 for linear (graded) doping profiles.

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Fig. 2-19. The junction capacitances of a P-N junction

Example 2-3. Consider an abrupt p-n diode with Na = 1018 cm-3 and Nd = 1016 cm-3. Calculate the built-in voltage, the depletion region width and the junction capacitance at zero bias. The diode area equals 10-4 cm2. Take s=1pF/m Repeat for a one-sided diode and calculate the relative error. Solution The built in potential of the diode equals Vbi =VT ln(NaNd/ni2) = 0.83V The depletion layer width at zero bias is given by:

W

2 o s  Na .  Nd  e  Na Nd

 2 o s .Vbi  Va   Vbi  0  0.33m eN d 

The junction capacitance at zero bias equals

C jo 

 o s A W

 3.17 pF Va 0

Repeating the analysis while treating the diode as a one-sided diode, one only has to consider the region with the lower doping density so that

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W  Wn 

Chapter 2

2 o s Vbi  Va   0.31m eNd

And the junction capacitance at zero bias equals

C jo 

 o s A W

 3.18 pF Va 0

The error is 0.5%, which justifies the use of the one-sided approximation

2-7. Circuit Models of a P-N Junction Diode The diode allows current to flow in only one direction. The perfect diode would be a conductor in one direction (forward bias) and an insulator in the other direction (reverse bias). If a large signal is applied, the diode may switch between forward and reverse bias regions, according to the applied signal amplitude. In many situations, using an ideal diode approximation, as a switch, is acceptable.

Fig. 2-21. Ideal diode (switch) model.

2-7.1. Large-signal (DC) Circuit Model of a P-N Junction The diode modeling involves the formulation of either small-signal linearized model, which is valid about an operating point or a piecewiselinear equation model. The linearized equation model describes the circuit in terms of its equivalent passive elements and controlled voltage/current sources. The following figure depicts a practical model of the P-N junction diode, which includes a barrier voltage and series resistance in the forward direction. This model is suitable for DC and large signal circuits. The linear forward resistance (RF) can be calculated from the slope of the linear portion of the I-V characteristics. However, this is usually not necessary since the forward resistance value is almost constant. For low-power Ge and Si diodes the RF value is about 2 to 5, while higher power diodes have RF closer to 1. In forward bias, the drop Vd is about 0.3V for Ge diodes and 0.7V for Si diodes. 98 Prof. Dr. Muhammad El-SABA

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Fig. 2-22. Large signal diode model, with barrier voltage and forward resistance

Example 2-4. Assume a low-power diode with a forward resistance value of 5. The barrier voltage V is 0.3V. Determine the diode current Id if the diode is connected to a series resistance Rs=50 and an applied voltage Va = 5V. Solution We write the KVL equation for the circuit: VA = Id RS - V – Id RF ID = (Va – V)/(RS + RF ) = (5 – 0.3)/( 50 + 5) = 85.5 mA

Diode Circuit

Equivalent Circuit

Fig. 2-23. Diode model and équivalent circuit

2-7.2. Quiescent Point of a Junction Diode The quiescent point (Q-point) of a diode is the operating point, which indicates its DC current (Id) and DC voltage drop (Vd). The Q-point can be obtained graphically from the diode I-V characteristics. The example, below, shows how the Q-point is determined using the I-V curve of the diode and the load line. The load line plots the possible combinations of diode current and voltage for a given circuit. The maximum Id equals Va/Rs, and the maximum Vd equals Va. The Q-point is located where the load line and the characteristic curve intersect. 99 Prof. Dr. Muhammad El-SABA

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Figure 2-25. Illustration of the Q-point and the graphical solution of a diode. circuit

2-7.3. Small-signal (AC) Circuit Model of a P-N Junction The small circuit model is constructed by linearizing the diode I-V characteristics around a certain Q-point. Figure 2-17(c) depicts the smallsignal model of a forward biased P-N junction at low frequencies. The dynamic resistance rd depends on the forward diode current Id (at the Qpoint) and is typically in the order of Ohms. Mathematically speaking, the diode dynamic resistance is given by: rd 

dVd .VT  dI d Id

(2-25)

where  is the non-ideality factor of the P-N junction. At high frequency, we have to consider the P-N junction capacitance. The diode capacitance includes the diffusion capacitance Cd =a/rd in parallel with the transition capacitance CT in forward bias and only the transition capacitance CT in reverse bias. Therefore, the transition capacitance CT, which is present in both reverse and forward biased diodes, is due to space-charge layer around the diode junction. On the other hand, the diffusion capacitance Cd is present only in forward bias because it is due to stored minority carriers under forward biased conditions. In both cases, the diode capacitance (Cj=CT+Cd) is a function of the applied bias, as given by equation (224d). The figure 2-24 depicts the small-signal AC model of a P-N junction. A more general diode model, which is suitable for computer simulation, is given in Appendix B of this book.

Figure 2-24. Small-signal (AC) model of a P-N junction diode.

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2-8. Transient Behavior of a P-N Junction Diode We know that an ideal diode conducts current in one direction (forward) and blocks current in the other direction (reverse). A common use of the P-N junction is to switch between the on-state and the off state. However, when a real P-N junction is subjected to fast switching or step voltage it doesn’t change from forward to reverse state instantaneously, but needs a certain time to recover from a strong forward conduction state to cut-off. The phenomenon of charge storage during forward conduction is present in all semiconductor junction diodes and is due to finite lifetime of minority carriers in semiconductors. The following figure depicts the collapse of the stored charge in one side of a P-N junction diode (holes in the n-side), when the diode is switched off. When diode is forward biased, a charge Qs is stored in the device. This stored charge depends on: 1. Intensity of the forward anode current IF in steady state. 2. Minority carrier lifetime τ, i.e. the mean time a free charge carrier moves inside a semiconductor region before recombining. Figure 2-26 depicts the switching-off waveforms of a P-N junction. As shown in figure, the total reverse recovery time (trr) is composed of two components, namely: the storage time (ts) and the fall time (tf). The storage time (ts) is given by:

erfc[(ts/)½] = IF / (IR + IF)

(2-26a)

where erfc() is the error function. When both forward and reverse currents flow for long time, compared to the lifetime , then one can use the following approximate relation for ts:

ts   ln [1+(IF / IR)]

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(2-26b)

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Fig. 2-26. Switching characteristics of a P-N junction diode.

Fig. 2-27. Collapse of the stored charge (here holes in the n-side) in a P-N junction diode, when it is turned off.

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The fall time (tf) is the time required for the reverse current, IR, to fall from 90% to 10% of its maximum value (IR =E2/R). It is given by the following equation:

erfc[(tf /)½] +[(tf /)] -½.exp[-(tf /) ]= 1+0.1(IR / IF)

(2-26c)

The delay time (td) is the time required for the forward current, IF, to rise from 0% to 10% of its maximum value (IF =E1/R). The rise time (tr) is the time required for the forward current, IF, to rise from 10% to 90% of its maximum value (IF =E1/R). Note 2-2. Charge Control Model of a P-N Junction Consider the N-side quasi-neutral region of a forward-biased P-N junction:

pn  2pn pn can be put in the  DP  t x2 p (epn ) epn J  P  following form in N-side quasi neutral region t x p Integrating over the N-side quasi-neutral region results: dQp Q  I P ( xn )  p dt p where Qp is the, excess minority carriers stored in the N-side quasi-neutral regions:  n2 Qp  eA pn ( x)dx  eApn ( xn ) Lp =  eA i e qVA / kT  1 L p xn Nd Where we substituted the excess hole pn expression in a normal long diode. In a short diode, the same expression holds, with replacing the diffusion length with half the P-side neutral width Ln  ½ Wp’.Similarly, we can write the following equation for excess charge in the P-side neutral region dQn Q  I n ( x; )  n with dt n  n2 Qn  eA n p ( x)dx  eAn p ( x p ) Ln =  eA i eqVA / kT 1 Ln xp Na The steady-state diode current (I =In +Ip) can be viewed as the charge supply required to compensate for charge loss by recombination (for long base) or collection at the contacts (for narrow base).  Qn Qp I  τn τp Note that for a short diode, the minority carrier life time n, p should be replaced with ½Wn2/Dp and ½Wp2/Dn, respectively. The minority carrier diffusion equation









2-9. Applications of the P-N Junction In this section we depict some important applications of the P-N junction diode in electronic engineering systems. Here, we briefly describe the diode applications in the following circuits: 103 Prof. Dr. Muhammad El-SABA

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1- Rectification and DC power supplies, 2- Peak detectors, 3- Clipping circuits, 4- Clamping circuits, and 5- Voltage multipliers 2-9.1. Diode as a Rectifier (Rectification) Generally speaking, rectification is the conversion of alternating current (AC) to direct current (DC). This usually involves a device that only allows one-way flow of electrons. We have seen that the P-N junction can be operated as a rectifier element, because of its high resistance in the reverse direction and its very low resistance in the forward direction. Figure 2-27 depicts the rectifier action on AC input voltage, in different circuit configurations. If we need to rectify AC power to obtain the full use of both half-cycles of the sine wave, a certain circuit must be used. This circuit is called a full-wave rectifier. One kind of full-wave rectifier, called the center-tap rectifier, uses a transformer with a center-tapped secondary winding and two diodes, as shown in figure 2-27(b). One disadvantage of this full-wave rectifier design is the need of a centertapped transformer. The center-tapped rectifier is only useful for smallpower DC power supplies. Figure 2-27(c) depicts another popular fullwave rectifier circuit, called the bridge rectifier. Note that regardless of the polarity of the input, the current flows in the same direction through the load. That is, the negative half-cycle of source is a positive half-cycle at the load. The current flow is through two diodes in series for both polarities. Thus, two diode drops of the source voltage are lost (0.7x2=1.4V for Si) in the diodes. This is a disadvantage compared with a full-wave center-tap design. This disadvantage is only a problem in very low voltage power supplies. Finally, diode can be also employed to rectify polyphase AC sources. Figure 2-21(d) depicts 3-phase diode rectifier. In this configuration, each line of the three-phases is connected between a pair of diodes: one to route power to the positive (+) side of the load, and the other to route power to the negative (-) side of the load.

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(a) Half-wave rectifier

(b) Full-wave rectifier

(c) Bridge (full-wave) rectifier

Operation of the bridge rectifier Figure 2-27. Application of the P-N junction diode as a rectifier. (a) Half-wave rectifier. (b) Full-wave rectifier using a center-tapped transformer, (c) Full-wave rectifier, using a bridge rectifier.

The figure 2-28 depicts how the P-N junction diode can be employed in a simple DC power supply, which consists of a simple rectifier and an R-C filter, to obtain an average DC output across a load resistor. The average DC voltage output of such a simple DC power supply is given by the following relation: 105 Prof. Dr. Muhammad El-SABA

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VDC = Vp - ½ V ≈ Vp ( 1 – 1/RLC)

Chapter 2 (2-27)

where Vp is the peak value of the input AC voltage, is its frequency. Also, C is the smoothing capacitor, RL is the load resistance and V ≈ 2Vp/RLC is called the output ripple voltage. The ratio of RMS value of AC component to the DC component in the output (Iac/Idc) is known as the ripple factor

Figure 2-28. Application of the P-N junction diode in a simple power supply

Example 2-5. Consider the 2-diode circuit shown below. Calculate each diode current and voltage drops.

Solution: Make a guess as to one of the possible states of the circuit. If a diode is assumed on, verify the current calculated flows in the correct direction consistent with the diode being on. If a diode is assumed off, verify the voltage across the diode calculated has a polarity consistent with the diode being off. The possible states of the two diodes are as follows: 106 Prof. Dr. Muhammad El-SABA

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We select the ideal diode model. * Assume first both diodes are on, then:

But IA = ID1+ID2 such that ID1 = -0.5 m. This contradicts the assumption that D1 is on. Now, let’s assume diode 1 is on, diode 2 is off:

ID2 = 0 mA , vb = -10V, and hence Vd1 = va –vb = 0 –(-10)V = 10V. This contradicts the assumption that D2 is off. Finally, let’s assume D1 is off and D2 is on IA = ID2. Also we have: 15V-10000 IA- (-10V) = 0, so that IA= 1.7mA. Also, va -0 = Vd1 = 15-10000IA = -1.7V Thus, Assumptions: D1 off and D2 on verified! Check yourself that the fourth combination (both diodes are off) cannot be verified. 2-10.2. Peak Detector As shown in the following figure, the peak detector is a series connection of a diode and a capacitor which produces a DC voltage equal to the peak value of the input AC signal. When the AC input voltage is applied to the peak detector, it charges the capacitor to the peak of the input waveform. The diode conducts during the positive half cycles, and charges the capacitor to the waveform peak

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Figure 2-29. Application of the junction diode in a peak detector circuit.

When the input waveform falls below the attained DC peak, which is stored on the capacitor, the diode is reverse biased, and blocks the current flow from the capacitor back to the input source. Thus, the capacitor retains the peak value even as the waveform drops to zero. This circuit is usually employed in AM radios, in the demodulation stage.

Figure 2-30. Application of the junction diode in a peak detector circuit.

2-10.3- Clipping Circuits The clipping circuit clips the peak of an input waveform to certain amplitude. The following figure shows a bipolar clipping circuit, with two back-to-back diodes. This circuit clips the positive and negative peaks of an AC input to the forward diode drop (≈ 0.7V for Si diodes). Such clipping circuits are usually employed in voltage limiters, in a wide range of applications, like wireless transmitters, as shown in figure 2-32

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Figure 2-31. Simple clipping circuits,

Figure 2-32. Application of the diode clipping circuits in a wireless transmitter.

2-10.4- Clamping Circuits A clamping circuit is used to place either the positive or negative peak of a signal at a desired level. As shown in the following figure, the clipping circuit clamps (or lifts) the peak of a waveform to a specific DC level. As shown in figure 2-33(a), the clamp voltage is 0V, if we ignored diode drop (0.7V in Si diodes). Ignoring the diode forward drop, the positive peak of Va is clamped to the 0V (really 0.7V). On the first positive half cycle, the diode conducts charging the capacitor left end to +5V (4.3V). This is -5V (-4.3V) on the right end at Va. The right end of the capacitor is -5V (-4.3V) with respect to ground. It also has 5V peak coupled across it from source Vs. The sum of the two is a 5V peak riding on a -5V DC (4.3V) level. The diode only conducts on successive positive excursions of source Vc if the peak Vc exceeds the charge on the capacitor. 109 Prof. Dr. Muhammad El-SABA

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The charge on the capacitor is equal to the positive peak of Vc (less 0.7V). The AC riding on the negative end, right end, is shifted down. The positive peak of the waveform is clamped to 0V (0.7V) because the diode conducts on the positive peak.

Figure 2-33. Application of the junction diode in clamping circuits. Three configurations are shown (a) Positive peak clamped to 0 V. (b) Negative peak clamped to 0 V. (c) Negative peak clamped to 5 V

2-10.5- Voltage Multipliers The voltage multiplier can produce an output which is theoretically multiple of the input waveform peak. Thus, it is possible to get 220VDC from a 110VAC source by a voltage doubler. However, in practical circuits the load will lower this value. As shown in figure 2-34()a), the voltage doubler consists of two diodes and two capacitors, connected as clamping circuit and a peak detector. The operation is as follows. The following figure depicts the output waveform of a voltage doubler. During the negative half-cycle of input voltage, diode D1 is forward biased and diode D2 is reverse biased. Therefore, diode D1 is represented by a short and diode D2 as an open. The equivalent circuit then becomes as shown in the following figure. C1 will charge until voltage across it becomes equal to peak value of source voltage VSpk. At the same time, C2 will be in the process of discharging through the load RL. 110 Prof. Dr. Muhammad El-SABA

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Figure 2-34(a) Application of the junction diode in a voltage doubler circuit.

When the polarity of the input voltage reverses (during positive halfcycle), D1 is reverse biased and D2 is forward biased as shown in figure below. In this case, C1 (charged to VSpk) and the source voltage VS now act as two voltage sources in series. Thus C2 will be charged to the sum of the sum of their series peak voltages (2VSpk). As C2 barely discharges between input cycles, the output waveform of the voltage doubler resembles that of a filtered half-wave rectifier. The most common type of voltage multipliers is the half-wave series multiplier, also called the Villard cascade. Such a circuit is shown in figure 2-35.

Figure 2-34(b). Output waveform of the voltage doubler circuit.

Figure 2-34(c). Output waveform of the voltage doubler circuit.

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The voltage multipliers may be employed in high voltage DC power supplies. Voltage multipliers are also extensively used in TV sets, to produce extra high tension (EHT) voltage, which is necessary for the operation of a TV cathode ray tube (CRT).

Figure 2-35. Application of the junction diode in a voltage multiplier circuit.

2-10.6. Temperature Sensor We can make use of a P-N junction as a measuring instrument to determine the ambient temperature. The ordinary semiconductor diode may be used as a temperature sensor. When a constant current (I) passes across a forward biased P-N junction, the forward voltage (Vd) is given by:

Vd = ( kB T / e ) . ln [ 1 + ( Id / Is ) ]

(2-28a)

Figure 2-36(a) depicts the current-voltage characteristics of P-N junction and how it is affected by temperature variations. As shown in figure, the forward voltage drop increases by almost a constant rate (dVd/dT) as temperature increases:

(dVd / dT) = ( kB / e ) . ln [ 1 + ( Id / Is ) ]

(2-28b)

The diode is the lowest cost temperature sensor and can produce more than satisfactory results if you are prepared to undertake a two point calibration and provide a stable excitation current. Almost any silicon diode is ok. The forward biased voltage across a diode has a temperature coefficient of about 2.3mV/°C and is reasonably linear. The measuring circuit is simple as shown in figure 2-36(b). The bias current should be held as constant as possible - using constant current source or a resistor from a stable voltage source. To improve the performance of the diode as a temperature sensor, two diode voltages (V1 and V2) can be measured at different forward currents (I1 and I2), typically selected to be about 1:10 ratio. The absolute temperature can be calculated from the equation: T = (V1 - V2) / (8.7248x10-5 ln( I1 / I2)) 112 Prof. Dr. Muhammad El-SABA

(2-28c)

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The result is in Kelvins (K). This is the method employed by most integrated circuit temperatures sensors and explains why some output a signal proportional to absolute temperature. I

T1 T2

Reverse Saturation current

T3

T3 > T2 > T1

Is Vd Forward Voltage proportional to the Temperature Figure 2-36(b). Variation of I-V characteristics of a junction diode with temperature

Figure 2-36(a). Application of the junction diode as a temperature sensor.

2-11. P-N Heterojunction Diodes Thus far, we described the behavior of homogeneous P-N junctions, which are fabricated from a single semiconductor material, such as Si. However, it is sometimes desirable to make P-N junctions with P-side from a specific semiconductor material and N-side from another one. This structure is called heterojunction. The following figure depicts the energy band diagram of such a heterojunction diode. Note that there exists a discontinuity in conduction and valence bands of the junction. Their magnitudes may be expressed as follows:

EC = 1 - 2

(2-29a)

EV = Eg - EC 

(2-29b)

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Fig 2-37. Band structure of a heterojunction (N-Al0.3Ga0.7As /P-GaAs) in equilibrium.

The barrier height (heterojunction built-in voltage) is given by: eVbi = Eg (GaAs) – e (p +n ) + (GaAs) - (AlGaAs)

(2-29c)

For the case GaAs /AlGaAs heterojunction, EC = (GaAs) - (AlGaAs) = 0.244 eV and EV = Eg - EC = 0.136 eV. One of the intersting P-N heterojunctions is the N-GaN / P-SiC structure. This structure is obtained by deposition of GaN on SiC. Usually GaN is deposited on (0001) face of a SiC substrate. Both Si and Mg can be used as donor and acceptor impurities, respectively. Ni, Ti or Pd metals are employed to form Ohmic contact for the top-GaN. The turn-on voltage of such diodes is about 2V, which corresponds to the built-in potential of the heterojunction.

2-12. Special Diode Structures There exist a variety of semiconductor diodes that are typically used in electrical and electronic circuit applications. These diodes include Zener diode, P-I-N diode, varactor diode (varicap), Schottky barrier diode (SBD), resonant tunneling diode (RTD) and tunnel diode.

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Fig 2-37. Band structure of a heterojunction (N-Al0.3Ga0.7As /P-GaAs) in equilibrium.

2-12.1. Zener Diode The Zener diode is a special P-N junction diode with highly doped sides. The highly doped regions of the P-N junction results in a high electric field across a very thin depletion region, as shown in figure 2-38. This results in tunneling current leading to a non-destructive breakdown (when connected with a limiting resistor). For tunneling, there should be a sufficient field greater than a certain critical value ζcr in the order of 2x107 V/cm. In this condition, the Zener breakdown voltage is given by:

VZ 

 o s . cr2  Na  Nd  2e

  N N  a d 

(2-30)

Fig. 2-38. Band structure of a Zener diode.

Zener diodes can be formed to breakdown at voltages from about 4 volts to several hundred volts. The I-V characteristics of the Zener diode are shown in figure 2-39. The constant reverse voltage VZ of the Zener diode makes it a valuable component for the regulation of the output voltage 115 Prof. Dr. Muhammad El-SABA

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against both variations in the input voltage from an unregulated power supply or variations in the load resistance.

Fig. 2-39. The I-V characteristics of a Zener diode

Fig. 2-40. Application of a Zener diode in voltage regulation.

The analysis of Zener diode circuits is very similar to the analysis of P-N diodes. The first step is to determine the state of Zener diode, whether it is OFF or ON. Next, the Zener is replaced by its appropriate model. When the Zener is operating in the breakdown region, it is represented by a voltage source (VZ) and a small series resistance (rZ). Finally, the unknown quantities are determined from the equivalent circuit. Example 2-6 Show how to design a 5V stabilized power supply from a 12V DC power supply, given that the maximum power rating PZ of the Zener is 2W. Solution 116 Prof. Dr. Muhammad El-SABA

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a) The maximum current flowing through the Zener is given by. Maximum Zener current (Iz) = Pz/Vz = 2W/5V= 400 mA b) The minimum value of the series resistor, RS is given by: Rs = (Vs –Vz )/Iz = (12-5) / 400mA = 17.5 k c) The load current IL if a 1kΩ load resistor is connected across the Zener. IL = Vs /RL = 5V / 1k =5 mA d) The total supply current IS is then: Is = IL + Iz = 5mA+400mA = 405 mA Example 2-7 For the circuit shown below, find (i) the output voltage (ii) the voltage drop across series resistance and (iii) the current through zener diode

Solution. If we removed the Zener diode, the voltage across the open-circuit would be: V = RL.Ei /(R+RL) = 10x120/(5+10) = 80V. Since voltage across Zener diode is greater than VZ (= 50V), the Zener is in the ―Zener ON‖ mode. It can, therefore, be represented by a battery of 50V (assuming internal resistance rz= 0 ), as shown in the above figure. (i) Output voltage = VZ = 50V (ii) Voltage drop across Rs = Input voltage − VZ = 120 − 50 = 70 V (iii) Load current, IL = VZ/RL = 50 V/10 kΩ = 5 mA Current through Rs, I = 70 V / 5 kΩ = 14 mA. As, I = IL + IZ . Therefore, The Zener current, IZ = I − IL = 14 − 5 = 9 mA Zener diodes can be also used in voltage clipping and squaring circuits, as shown in the figure 2-41.

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Fig. 2-41. Application of a Zener diode in voltage regulation.

2-12.2. P-I-N Diode1 The PIN diode is some sort of P-N junction diodes, with a wide, intrinsic semiconductor region between the P-type and N-type semiconductor regions. As a result of its special structure, the P-I-N diode is used in a variety of applications. The properties introduced by the intrinsic layer make it suitable for some applications where ordinary P-N junction diodes are less suitable. There are three main applications for P-I-N diodes, although they can also be used in other areas as well: High voltage rectifier: The P-I-N diode can be used as a high voltage rectifier. The intrinsic region provides a greater separation between the P and N regions, allowing higher reverse voltages to be tolerated. RF (Microwave) switch: The P-I-N diode is an ideal RF switch. The intrinsic layer between the P and N regions, decreases its capacitance, thereby increasing the isolation level, in reverse bias. Photodetector: The intrinsic layer improves the efficiency of the P-I-N photodiode by increasing the volume in which light conversion occurs.

Fig. 2-42. Structure of a typical P-I-N diode.

However, the P-I-N diode has a poor reverse recovery time. At higher frequencies, the device cannot response as quickly because there is no enough time to remove the excess charge. Therefore, the P-I-N diode 1

P-I-N diodes are also presented in Chapter 8 (Power Devices) and Chapter 10 (Microwave devices)

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never turns OFF at high frequencies. Although the P-I-N diode has many applications in high voltage, it is usually employed in RF applications where it is best known. The fact that when it is forward biased, the diode is linear, behaving like a resistor, can be put to good use in a variety of applications. For instance, it can be used as a variable resistor in a variable attenuator, a function that few other components can achieve as effectively. Actually, the P-I-N diode obeys the diode equation only for very slow signals. At high frequency, the diode looks like a perfect resistor. The high-frequency resistance is inversely proportional to the DC current through the diode. The P-I-N series resistance is given by: (2-31) where IF is the forward current and  is the average carrier lifetime in the base region, By changing the bias current through a PIN diode, it is possible to quickly change the RF resistance. This high-frequency resistance may vary over a wide range (from 0.1 Ω to 10 kΩ). Thus the PIN diode is usually employed as a variable RF attenuator. Under reverse bias, a PIN diode has low capacitance. The low capacitance will not pass much of RF signal. Under a forward bias of 1mA, a typical P-I-N diode will have an RF resistance of about 1, making it a good RF switch.

Fig. 2-43. Application of the P-I-N diode, as an attenuator in RF circuits.

Microwave P-I-N diodes are manufactured using an epitaxial process. The i-layer is nominally a 100 -cm layer, grown on a heavily doped P+ or N+ substrate. Such diodes provide adequate switching performance above 2GHz. The depletion region of a P-I-N is larger than in a P-N diode, and almost independent of the applied reverse bias. This increases the area where electron-hole pairs can be generated. For these reasons many photo-detectors include P-I-N diodes. 119 Prof. Dr. Muhammad El-SABA

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Applications of P-I-N diodes also include: IR-remote control, video tape recorders, dimmers, remote control as well as light reflecting switches. More details about P-I-N diodes and their applications in power and microwave applications will come in Chapters 8 and 10 of this book.

Fig. 2-44. Application of the P-I-N diode, as variable attenuator in automatic gain control (AGC) of radio signals.

2-12.3. Schottky Barrie Diodes (SBD)2 Schottky barrier diode (SBD) is a semiconductor diodes based on a metal-semiconductor interface. The earliest study on metal semiconductor system was done by Karl Ferdinand Braun in 1874. The Schottky diode (named after the German physicist Walter Schottky, 1886-1976) is made by joining a suitable piece of metal with a semiconductor. In 1937 Schottky showed that a potential barrier arises in such a structure and that it has rectifying characteristics. SBD’s have very fast switching time and low forward voltage drop.

Fig. 2-45. Schottky barrier diode structure and symbol

Typical applications of SBD’s include RF detection and dischargeprotection for solar cells systems and in power supplies. In such 2

SBD’s are also presented in Chapter 10 (Microwave devices) and Chapter 11 (Photonic Devices).

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applications, the low forward voltage of the BSD leads to increased efficiency. While silicon diodes have a forward voltage drop of about 0.7V and germanium diodes 0.3V, Schottky diodes voltage drop at forward biases is in the range 0.15V to 0.46V at 1mA, which makes them useful in prevention of transistor saturation. Schottky diodes are also used as high sensitivity microwave detectors. Most important difference between P-N junction and Schottky diodes is reverse recovery time, when the diode switches from OFF to ON state and vice versa. Schottky diodes do not have a storage time, and hence the recovery time is trivial. The switching time is ~100ps for the small signal diodes, up to tens of nanoseconds for special high-capacity power diodes. It is often said that the Schottky diode is a majority carrier semiconductor device. This means that if the semiconductor body is doped N-type, only the N-type carriers (mobile electrons) play a significant role in normal operation of the device. The majority carriers are quickly injected into the conduction band of the metal contact on the other side of the diode to become free moving electrons. Therefore no slow, random recombination of N- and P- type carriers is involved, so that this diode can cease conduction faster than an ordinary P-N rectifier diode. This property in turn allows a smaller device area, which also makes for a faster transition. This is another reason why Schottky diodes are useful in switch-mode power converters. The high speed of SBD's permits them to operate at frequencies in the range 200 kHz to 2 MHz, allowing the use of small inductors and capacitors with greater efficiency than other diode types. Schottky diodes can be also used in power supply to isolate the internal battery from mains adaptor input. Small-area Schottky diodes are the heart of RF detectors and mixers, which often operate up to 5GHz. Schottky junctions are also used in the logic gates, as clamps in parallel with the collectorbase junctions of the bipolar transistors to prevent their saturation. Thereby, Schottky diodes can greatly reduce the turn-off delays of the clamped transistors. The most evident limitations of Schottky diodes are the low reverse voltage rating and the high reverse leakage current (for silicon-SBD).The voltage ratings are now up at 200V. More details, about the SBD will come in Chapter 4, when we talk about metalsemiconductor (M-S) contacts. 2-12.4. Step-Recovery Diode (SRD)3 The step-recovery diode (SRD) is sometimes called & fast-recovery diode, snap-off diode, or snap-back diode. The response of a standard P3

SRD’s are also presented in Chapter 10 (Microwave devices)

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N junction is limited by the minority-carrier storage, with the reverse recovery. A step-recovery diode has a special doping profile such that the field confines the injected carriers much closer to the vicinity of the junction. This results in a much shorter transition time ttr. The sharp turnoff of current approaches a square waveform which contains rich harmonics and is often used in applications of harmonic generation and pulse shaping. 2-12.5. IMPATT Diode4 The IMPact ionization Avalanche Transit-Time (IMPATT) diode is a high power P-N junction structure used in high-frequency and microwave applications (up to 100GHz). At constant reverse bias, the IMPATT diode current will oscillate if the applied voltage is just above breakdown of its P+-N junction. IMPATT diode is typically made with silicon carbide (SiC) because of its high breakdown field. These diodes are used in a variety of applications from low power radars to alarms. A. IMPATT Diode Structure The IMPATT diode family includes many different junctions and metal semiconductor devices. Figure 2-46 depicts one of these structures. The first IMPATT oscillation was obtained from a simple silicon P-N junction diode biased into a reverse avalanche breakdown and mounted in a microwave cavity. Because of the strong dependence of the ionization coefficient on the electric field, most of the electron–hole pairs are generated in the P+-N high field region. The generated electrons drifts into the depletion region, while the generated holes moves through the P+-region to the anode contact (A). The time required for electrons to reach the cathode contact (K) represents the transit time of the diode.

Fig. 2-46. Basic structure of IMPATT diode.

The original proposal for a microwave device of the IMPATT type was made by Read. The Read diode consists of two regions as illustrated in figure 2-46, namely the avalanche region and the drift region. The Avalanche region (P+–N region with relatively high doping and high field), in which avalanche multiplication occurs and the drift region (N -– 4

IMPATT’s are also presented in Chapter 10 (Microwave devices), with more details

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region with essentially intrinsic doping and constant field), in which the generated electrons drift towards the cathode contact. A major drawback of IMPATT diodes is their high phase noise. This results from the statistical nature of the avalanche process. Nevertheless these diodes make excellent microwave generators for many applications. 2-12.6. Tunnel Diode5 The tunnel diode (or Esaki diode) is a type of semiconductor diodes, which is capable of very fast operation, well into the microwave region, utilizing quantum mechanical effects. It was named after Leo Esaki, who received the Nobel Prize in Physics in 1973 for discovering the electron tunneling effect used in such diodes. These diodes have a heavily doped P-N junction over only some 10nm width. The high doping results in a narrow energy barrier, where conduction band states on the N-side are more or less aligned with valence band states on the P-side, permitting electrons to tunnel through the barrier. The figure 2-49 depicts the I-V characteristics of the tunnel diode, its circuit symbol and energy band diagram. Under normal forward bias operation, as voltage begins to increase, electrons at first tunnel through the narrow P-N junction barrier because filled electron states in the conduction band on the N-side become aligned with empty valence band hole states on the P-side. As voltage increases further these states become more misaligned and the current drops — this is called negative resistance, because current decreases with increasing voltage.

Fig. 2-49. Tunnel diode I-V characteristics and energy band diagram. 5

Tunnel diode is also presented in Chapter 10 (Microwave devices) and Chapter 12 (Quantum devices)

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As voltage increases yet further, the diode begins to operate as a normal diode, where electrons travel by diffusion across the P-N junction. The tunnel diode showed great promise as a high-frequency oscillator since it operates at frequencies well into the microwave bands. However, since its discovery, other semiconductor devices have surpassed its performance using conventional oscillator techniques. Tunnel diodes are also relatively resistant to nuclear radiation, as compared to other diodes. This makes them well suited to higher radiation environments, in space applications. Figure 2-50 shows an application of the tunnel diode, as an oscillator.

Fig. 2-50. Tunnel diode oscillator circuit.

2.12.7. Resonant Tunnel Diode (RTD)6 A resonant tunnel diode (RTD) is a device which uses quantum effects and negative differential resistance (NDR). RTD’s are formed as a single quantum well structure surrounded by very thin layer barriers. As an RTD is capable of generating a terahertz wave at room temperature, it can be used in ultra high-speed circuits. The figure 2-51 depicts the structure of an AlGaAs/InP RTD. This device is called a double-barrier structure. When a voltage is placed across an RTD, a terahertz wave is emitted which is why the energy value inside the quantum well is equal to that of the emitter side. As voltage increased, the terahertz stops because the energy value in the quantum well is outside the emitter side energy. Tunneling through a double barrier was first discussed by David Bohm in 1951, who pointed out that resonances in the transmission coefficient occur at certain incident electron energies. It turns out that, for certain energies, the transmission coefficient is equal to one, i.e., the double barrier is totally transparent for particle transmission. This phenomenon is called resonant tunneling. The GaAs and AlAs in particular are used to form resonant tunneling structure. This structure can be fabricated by molecular beam epitaxy (MBE). 6

RTD’s are also presented in details in Chapter 8 (Microwave Devices) of this book.

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Also, Si/SiGe heterojunctions can be used to fabricate RTD’s. The typical I-V characteristics of a GaAs/Al0.3GaAs0.7 RTD at low bias regimes are illustrated in figure 2-53. The corresponding energy band diagram and state wavefunctions, are illustrated in figure 2-54. Figure 2-46 shows an application of the RTD, as an oscillator. Because of the negative differential resistance exhibited by RTD’s, and since tunneling is an inherently fast transport mechanism, these devices have been proposed for use in extremely high frequency oscillators.

Fig. 2-51. Structure of AlGaAs/InP double-barrier RTD and its circuit symbol.

Fig. 2-53. Typical I-V characteristics of a GaAs/Al0.3GaAs0.7 RTD.

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Fig. 2-56. Application of an RTD as a negative resistance oscillator.

2-12.8. Solar Cells7 A solar cell or photovoltaic (PV) cell is a semiconductor device that converts light energy into electrical energy by the photovoltaic effect. The solar cell structure is shown in figures 2-57. The equivalent circuit and IV characteristics are also shown in figure 2-58. Groups of PV cells are usually configured into modules, which can be used to charge batteries, operate motors, and to power electrical loads.

Fig. 2-57. Structure of a conventional solar cell 7

Solar Cells are presented in details in Chapter 8 (Photovoltaic Devices) of this Book.

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Fig. 2-58 Solar cell operation, and circuit symbol

The operating current of a solar cell is given by:

  Vd   I  I ph  I d  I ph  Io exp   1  . V   T 

(2-33)

where Iph is the photocurrent, and Id is the diode current. The solar cell IV characteristics depend on the ambient temperature and the semiconductor material, which is used in its fabrication. In fact, the open circuit voltage of the solar cell is proportional to the energy gap of the semiconductor material. Also, the short-circuit current of the solar cell is smaller for higher open-circuit voltage.

Fig. 2-59 Solar cell equivalent circuit and I-V characteristics.

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2-12.9. Photodiode8 The photodiode is a biased version of the solar cell. It works in reverse bias, as shown in figure 2-66. The I-V characteristic of the photodiode is similar to that of the conventional P-N junction, with addition of a photocurrent component due to electron-hole generation n the space charge region.

  Vd  I exp I =Id + Iph = o    VT 

    1  eA.(Wn  W  Wp ).GL  

(2-34)

where the dark current, Id, has the same expression of the conventional diode current, and the photocurrent, Iph, is related to the total space – charge region width (the intrinsic region W plus the depleted regions on both sides Wn+Wp) as well as the light generation rate GL. For short diodes, without intrinsic region, the total depletion width (W+Wn+Wp) should be replaced with the sum of carrier diffusion lengths (Ln+Lp).

Fig. 2-66. Operation of a photodiode, without and with light illumination.

8

Photodiodes are presented in details in Chapter 11 (Photonic Devices).

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Fig. 2-67. The I-V characteristics of a Photodiode, at different illumination powers.

2-12.10. Light-Emitting Diode (LED)9 Light-emitting diode (LED) is a special P-N junction device, which emits visible light when forward biased. Light is emitted when electrons and holes recombine in the space charge region of the P-N junction. The following figure illustrates the operation of the photodiode. LEDs are available in a wide range of shapes, colors and various sizes with different light output intensities.

Fig. 2-70. Structure and radiation pattern of a light-emitting diode (LED). 9

LED’s are presented in details in Chapter 11 (Photonic Devices).

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The first commercially available LEDs started to appear in the late 1960s. The early LEDs used a semiconductor made of gallium, arsenic and phosphorus - GaAsP. This produced a red light, and although the efficiency of the devices was low (typically around 1 - 10 mCd at 20mA) they started to be widely used as indicators on equipment. Later, in 1993 HP started to use GaP (gallium phosphide) to provide high output green LEDs. Also further developments of this technology allowed the production of high output orange lamps. After a decade of intense research, a bright blue LED was successfully produced in 1994, using gallium nitride GaN. Other ways of producing blue light from solid state sources involve doubling the frequency of red or infrared Laser diodes. The subsequent figure shows the I-V characteristics of LEDs of different semiconductor materials (and different colors).

Fig. 2-71. Band structure and operation of a light-emitting diode (LED).

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Fig. 2-72. Forward I-V characteristics of LEDs of different materials.

The nominal forward voltage drop of the LED determines the suitable value of the series resistor to be connected with it, as shown in the following circuit:

Fig. 2-76. Circuit connection of a light-emitting diodes.

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Example 2-11, An amber LED with a forward drop of 2V is to be connected to a 5V DC power supply. Using the circuit above calculate the value of the series resistor required to limit the forward current to less than 10mA. Solution The series resistance is given by: Rs = (Vs - VF)/IF = (5-2)V / 10mA = 300 Most light emitting diodes produce just a single output of colored light. However, multi-colored LEDs that can also produce two or three different colors from within a single device are also available. 2-12.11. Laser Diode10 Laser is the acronym of Light Amplification of Stimulated Emission of Radiation. Like LED’s, Laser diodes are luminescent devices, which emit light in response to electronic excitation. However, the emission involved in LED’s is said to be spontaneous emission, while emission involved in Lasers is said to be stimulated emission.

Fig. 2-81. Laser diode structure and real component.

Laser diodes consist of a P-N diode with an active region where electrons and holes recombine resulting in light emission. In addition, a laser diode contains an optical cavity where stimulated emission takes place. The laser cavity consists of a waveguide terminated on each end by a mirror. The charge accumulation is realized by means of multiple reflection between two reflecting mirrors (or a cavity) whose length is deliberately chosen to match the required radiation wavelength.

10

Laser diodes are presented in details in Chapter 11 (Photonic devices).

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Fig. 2-83. Illustration of the stimulated emission in a Laser diode.

The current for which the gain satisfies the lasing condition is the threshold current of the laser, Ith. Below the threshold current a little light is emitted by the laser device. When the applied current is larger than the threshold value, the output power, Pout, increases linearly with current, as illustrated in figure 2-89, below. The output power therefore equals:

e Pout =  h (I - Ith)

(2-39)

where h is the energy per photon. The factor, , indicates that only a fraction of the generated photons contribute to the output power of the laser as photons are partially lost through the mirror and the waveguide.

Fig. 2-82. Spontaneous and stimulated (Laser) emission from a LED and a Laser diode, versus current.

2-13. Laboratory Testing of P-N Junction Diodes The figure 2-83 depicts an experiment to plot the I-V characteristics of a P-N junction diode. Being able to characterize and test the diode is a very important skill. Since we know that a diode is a one-way valve for electrical current (rectifier), we should verify its one-way nature using a DC battery-powered ohmmeter as shown in figure 2-94. The meter 133 Prof. Dr. Muhammad El-SABA

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should show a very low resistance in forward direction and the other way it should show a very high resistance at (b).

Fig. 2-93. Plotting the diode I-V characteristics, using an ammeter and a voltmeter.

Fig. 2-94. Diode testing using an ohmmeter (a) Low resistance indicates forward bias, (b) Reversing leads shows high resistance indicating reverse bias.

2-14. Diode Ratings A typical diode datasheet will contain figures for the following parameters: Maximum forward voltage (VF), is specified at the diode's rated forward current. Ideally, this figure would be zero. In reality, the forward voltage is described by the diode equation. 134 Prof. Dr. Muhammad El-SABA

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Maximum DC reverse voltage (VR), is the maximum amount of voltage the diode can withstand in reverse-bias mode on a continual basis. Ideally, this figure would be infinite. Maximum repetitive reverse voltage (VRRM), the maximum amount of voltage the diode can withstand in reverse-bias mode, in repeated pulses. Ideally, this figure would be infinite. Maximum (average) forward current (IF), is the maximum average of current the diode is able to conduct in forward bias. This is fundamentally a thermal limitation. Ideally, this figure would be infinite. Maximum (peak or surge) forward current (IFSM), is the maximum peak amount of current the diode is able to conduct in forward bias mode. Again, this rating is limited by the diode junction's thermal capacity, and is usually much higher than the average current rating due to thermal inertia (the fact that it takes some time for the diode to reach maximum temperature for a given current). Ideally, this would be infinite. Maximum total dissipation (PD), the amount of power (in watts) allowable for the diode to dissipate, given the dissipation (P=I 2R) of diode current squared multiplied by bulk resistance. Operating junction temperature (TJ), the maximum allowable temperature for the diode's PN junction, given in degrees Celsius (oC). Storage temperature range (TSTG), the range of allowable temperatures for storing a diode (unpowered). Sometimes given in conjunction with operating junction temperature (TJ). Thermal resistance (Θ), is the temperature difference between junction and outside air (Θ.A) or between junction and leads (ΘL) for a given power dissipation. Expressed in units of degrees Celsius per watt (oC/W). Maximum reverse current (IR), the amount of current through the diode in reverse-bias operation, with the maximum rated inverse voltage applied (VR). Sometimes referred to as leakage current. Ideally, this would be zero, as a perfect diode blocks current when reverse-biased. Typical junction capacitance (CJ), the typical amount of capacitance intrinsic to the junction, due to the depletion region acting as a dielectric separating the anode and cathode connections. This is usually a very small figure, measured in the range of pico Farads (pF). Reverse recovery time (trr), is the amount of time it takes for a diode to ―turn off‖ when the voltage across it switches from forward to reverse polarity. Ideally, this figure would be zero. For typical 135 Prof. Dr. Muhammad El-SABA

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diodes, trr is in the range of tens of micro secends; for a fast switching diode, it may only be a few nanoseconds. Most of the above indicated parameters vary with temperature and other operating conditions, and there is no figure to fully describe a given rating. Therefore, the device manufacturers provide graphs of ratings plotted against several parameters (such as temperature), so that the circuit designer can choose the suitable device for a specific application.

2-15. Computer Simulation & Modeling Parameters Electronic devices are usually described by their nonlinear terminal voltage-current (I-V) characteristics. Circuits containing electronic devices are analyzed and designed either graphically, using measured characteristics or by linearizing their voltage-current characteristics, with suitable circuit models. There exist so many simulation programs that can be used to simulate the behavior of electronic devices and circuits. The circuit simulators replace the active device with its circuit model and perform nodal analysis of the resultant circuit. Among these simulators, the most famous is SPICE. SPICE is the acronym of ―Simulation Program with Integrated Circuit Emphasis‖. PSPICE is a PC version of SPICE, from MicroSim Corporation which was recently acquired by Cadence Corporation. A demo version of the program is available in a limited use from the following link: http://www.orcad.com/Product/Simulation/PSpice/eval.asp The circuit simulator PSPICE supports the following types of Analysis: Quiescent operating point determination (.OP) DC sweeps of current/ voltage sources (.DC) Time-domain (transient) response (.TRAN) Small-signal frequency response (.AC) Fourier analysis (.FOUR) Noise analysis (.NOISE) Sensitivity analysis (.SENS) Thevenin equivalents (.TF) The PSPICE model of P-N junction diodes is depicted in details, together with its parameters, in Appendix B at the end of this Book.

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Fig. 2-95. SPICE model of a P-N junction, in forward bias.

The diode statement begins with a diode element name which must begin with ―D‖ plus optional characters, such as are: D1, d2, Da. Two node numbers specify the connection of the anode and cathode, respectively, to other components. The node numbers are followed by a model name, referring to a subsequent ―.MODEL‖ statement. The model statement line begins with ―.MODEL,‖ followed by the model name matching one or more diode statements. Next, a ―D‖ indicates a diode is being modeled. The remainder of the model statement is a list of optional diode parameters of the form ParameterName = ParameterValue. None are used in Example below. The following Examples have some parameters defined. The list of diode parameters is shown below. General form: D .MODEL D ([parmtr1=x] [parmtr2=y] . . .) Example 2-12: D1 1 2 mod1 .MODEL mod1 D Example 2-13: D2 1 2 Da1N4004 .MODEL Qa1N4004 D (IS=18.8n RS=0 BV=400 IBV=5.00u CJO=30 M=0.333 N=2) A simple strategy is to build a SPICE model from those parameters listed on the data sheet. Another strategy is to take measurements of an actual device. Then, calculate, and adjust the SPICE parameters. 137 Prof. Dr. Muhammad El-SABA

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Table 2-3: Diode SPICE Parameters Symbol Name IS IS RS RS n N τD TT CD(0) CJO υ0 VJ m M -

-

Eg

EG

-

-

xi

XTI

-

-

kf af FC BV IBV

KF AF FC BV IBV

Parameter Saturation current (diode equation) Parsitic resistance (series resistance) Emission coefficient, 1 to 2 Transit time Zero-bias junction capacitance Junction potential Junction grading coefficient 0.33 for linearly graded junction 0.5 for abrupt junction

Activation energy: Si: 1.11 , Ge: 0.67, Schottky: 0.69

IS temperature exponent P-N junction: 3.0, Schottky: 2.0

Flicker noise coefficient Flicker noise exponent Forward bias capacitance coefficient Reverse breakdown voltage Reverse breakdown current

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Units A Ω s F V -

Default 1E-14 0 1 0 0 1 0.5

-

-

eV

1.11

-

-

-

3.0

-

-

V A

0 1 0.5 ∞ 1E-3

Fundamentals of Electronic Devices

Chapter 2

2-16. Summary 

P-N junction is one of the fundamental structures within semiconductor device technology. It has the valuable property that electrons only flow in one direction across it and as a result it acts as a rectifier. After joining ptype and n-type semiconductors, electrons near the p–n interface tend to diffuse into the p region. As electrons diffuse, they leave positively charged ions (donors) in the n region. Likewise, holes near the p–n interface begin to diffuse into the n-type region, leaving fixed ions (acceptors) with negative charge. The regions nearby the p–n interfaces lose their neutrality and become charged, forming the space charge region or depletion layer. When no external energy is applied, an equilibrium condition is reached in which a potential difference is formed across the junction. This potential difference is called built-in potential Vbi = VT ln(NaNd/ni2). When a diode is short circuited, a potential barrier equal to the built-in voltage is developed across the depletion layer, which is approximately 0.7V for Si diodes and 0.3V for Ge diodes. However, even when the P-N junction is short circuited (zero bias), no current pass across the diode. The I-V characteristics of the P-N junction can be deduced from the concentration of excess carriers, which can be obtained by solving the diffusion equation in the quasi neutral regions, on both sides of the depletion region.

The diffusion currents on the two sides give a total of

Unlike a resistor, a diode does not behave linearly with respect to the applied voltage and therefore we cannot describe its operation by Ohm's law. Most textbooks tell us that the I-V characteristics of a P-N junction have an exponential form, typically as follows: 139 Prof. Dr. Muhammad El-SABA

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  V I d  Io exp  d   .VT

Chapter 2

   1  

where the thermal voltage VT =kBTL/e is about 26mV at TL =300K, kB is Boltsmann's constant, Io is the reverse saturation current and  is the ideality factor.

The reverse saturation current Io is given by:

 ni2 Dn ni2 Dp Io  e.A.   Ln Na Lp Nd 

  

Both Io and depend upon the diode structure and ambient temperature. The forward voltage drop, at which the P-N junction diode starts to conduct appreciable current is in the order of 0.7V (for Si diodes), as shown in the following figure. In addition to the diffusion current, one should consider the space-charge recombination current (in forward bias):

Wp Wn   Vd J r  12 eni    exp   n  p   2VT

  

At high current densities, the diode current is influenced by high-level injection phenomena and is given by:

J = 2e (Dp / Lp) ni exp (Vj /2VT) where Vi is the part of applied bias, across the space-charge region of the P-N junction. The rest of applied bias is dissipated as Ohmic drops on the quasi-neutral regions on both sides of the P-N junction. In reverse 140 Prof. Dr. Muhammad El-SABA

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bias, the space-charge generation current should be also considered

W J g  eni .   g

  

The ideal diode will behave like a short circuit (closed switch) when it is forward biased. Also the ideal diode will behave like an open circuit (open switch) when it is reverse biased. Practically, the diode will have a small forward resistance (rd =VT/I) and a very high reverse resistance. The following table shows the various equivalent circuit models of diode

There exist two processes which give rise to breakdown of P-N junctions: (1) Avalanche multiplication by impact ionization, in low-doped junctions (2) Zener breakdown by quantum tunneling, in highly-doped junctions The breakdown voltage of an abrupt P-N junction may be then expressed as: VB = 60 (Eg /1.1)3/2 (NI /1016)-3/4 where NI is the doping concentration of the low-doped side of the junction. The breakdown of a punch-through (short) diode is related to the breakdown voltage of a long diode, VB, by the following relation: VBPT = VB (Wb/W).[ 2 - (Wb/W ) ] where Wb is base width and W is the depletion region width (W=Wn+Wp).

 2  N (V  Va )  Wn   o s a bi   eNd ( N a  N d ) 

1/ 2

,

 2  N (V  Va )  Wp   o s d bi   eNa ( N a  N d ) 

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Chapter 2

There exist so many variant diode structures, which have more or less important applications as P-N junctions. The different diode types of types of diodes include those for small signal applications, diodes for light emission (LEDs) and detection, variable capacitance diodes (varicaps) and Zener diodes. Semiconductor diodes have taken a long rout of temporal evolution to reach to their current technology. The following table shows the milestones in the history of semiconductor diodes Diode Family

Time Frame Construction Galena, Si, with tungsten Cat's Whisker 1906 wire on "sweet spot" Subsequent Ge with tungsten wire, Point Contact improvement usually housed in glass. Stacked Copper oxide Copper Oxide 1927 and Iron disks on a bolt Stacked Selenium and Selenium 1933 metal deposits. Ge or Si, Chemical Junction Diode 1940 deposition of impurities Schottky Barrier Metal deposition on n1938 Diode (SBD) type Silicon Junction diode, doping Varicap Diode profile Junction diode with PIN Diode intrinsic layer Junction diode, doping Zener Diode profile Light Emitting Junction Diode, exposed Diode (LED) junction Junction Diode, exposed Photodiode junction Junction Diode, Wide Solar Cell Area Tunnel diode Highly doped junction Employs impact Impatt diodes ionization phenomenon Step Recovery Junction Diode, with Diode low storage time

142 Prof. Dr. Muhammad El-SABA

Application AM radio reception AM reception, microwave detection High current battery charger High Voltage rectifier, battery charger General purpose, computer diode RF detection, high speed high power rectification Voltage controlled tuning Current controlled attenuation Voltage regulation, clamping Indicator lamp, house lighting Light detection, Optical isolation, Optocouplers Solar electrical power generation Microwave oscillators Microwave oscillators Harmonic generation at microwaves

Fundamentals of Electronic Devices

Chapter 2

2-17. Problems 2-1) What quantities determine the widths of the space charge layer near the stochiometric (metallurgic) P-N-junction? 2-2) When the P-N junction diode is reversed biased, what happens to the majority carriers? 1. They combine with minority carriers at the junction 2. They move toward the junction 3. Both 1 and 2 above 4. They move away from the junction 2-3) What causes junction? 1. Holes 3. Minority carriers

small leakage current in a reverse-biased P-N 2. Electrons 4. Majority carriers

2-4) The depletion region in a P-N junction diode contains (a) only charge carriers (of minority type and majority type) (b) no charge at all (c) vacuum, and no atoms at all (d) only ions i.e., immobile charges 2-5) Consider a semiconductor P-N junction shown in figure. If carriers are injected from one side such that excess hole concentration at the side of the semiconductor is a constant and equal pn(0). It is required to calculate the spatial distribution of excess holes pn(x), across the N side, assuming low-level injection. Assume pn=0 at the end of the diode (x=W). Calculate the hole current density Jp at x= W. Hint: Solve the continuity equation for holes for x > 0 (where there is no generation):

 pn pn  pno  2 pn   Dp t p x 2 2-6) What capacitance dominates the dynamics of the forward and reversed biased diode, respectively? 2-7) Prove that the formula of the P-N junction transition capacitance at reverse bias may be put in the conventional form:

CT = A/W, where W is the depletion region width and A is the diode area 143 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

2-8) The diode in the following circuit has a cut-in voltage of V= 0.6V and a forward resistance rd = 150. If the diode can dissipate a maximum power of 200mW, calculate the maximum battery voltage (VB). Hint: Replace the diode with its equivalent circuit and the circuit to the left of a-b by its Thevenin equivalent circuit.

2-9) Verify the listed expressions for the DC output current and voltage, ripple factor and efficiency of the shown half-wave rectifier circuit.

2-10) Calculate the average DC voltage at the load of the following center-tap full wave rectifier (verify that VDC ≈ 0.65 Vm ≈ 0.9 Vrms)

2-11) Find an expression for the ripple voltage (V) and average DC output voltage (VDC = Vp - ½ V) of the following full-wave rectifier. What will be the average DC value of the output voltage when a capacitor is connected across the output load? 144 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

2-12) Why the Zener diode is considered as a good voltage regulator? 1. It compensates for low supply voltage 2. It uses an unlimited number of carriers 3. Operating in the breakdown region does not harm it 4. The voltage across the diode remains almost constant after breakdown 2-13) Which breakdown theory explains the action that takes place in a heavily doped P-N junction with a reverse bias above 5V? 2-21) Find the built-in potential (Vbi) for a P-N junction Si diode at room temperature if the bulk resistivity of Si is 1cm. The electron mobility in Si is 1400 cm2/V.s , μn/μp = 3.1, ni = 1.5 × 1010 cm−3 at room temperature. 2-22) For the Si P-N junction from the previous problem calculate the width of the space-charge region for the applied voltages −10V and 0.3V. Take s = 11.9 2-23) For the parameters given in the previous problem find the maximum electric field within the space charge region. Compare these values with the electric field within a shallow donor: Eid ≈ e/(saB2), where aB is the Bohr radius of a shallow donor, aB = (s 2/e2mn*) and mn*/mp* = 0.33. 2-24) Calculate the transition capacitance of the P-N junction from the problem 2-22 if the area of the junction is 0.1 cm2. 2-26) At room temperature under the forward bias of 0.15V the current through a P-N junction is 1.66mA. What will be the current through the junction under reverse bias? 145 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

2-27) For a P+N Si junction the reverse current at room temperature is 0.9 nA/cm2. Calculate the minority-carrier lifetime if Nd = 1015 cm−3, ni = 1.5 × 1010 cm−3 and μp = 450 cm2 /V.s. 2-28) How does the reverse current of a Si p-n junction change if the temperature raises from 20 to 50 ◦C? The same for a Ge P-N junction. Band gaps of Si and Ge are 1.12 and 0.66 eV, respectively. 2-30) A Si P+N junction (ni = 1.5×1010 cm−3, s = 11.9) is formed in an ntype substrate with Nd = 1015 cm−3. If the junction contains 1015 cm−3 recombination centers located at the intrinsic Fermi level and the capture cross section σn = σp = 10−15 cm2 (vth = 107 cm/s), calculate generation current density at a reverse bias of 10 V. 2-31) For a Si P-N junction with the p-side doped to 1017 cm−3, the n-side doped to 1019 cm−3 (N+P junction), and a reverse bias of −2V, calculate the generation current density at room temperature, assuming that the effective lifetime is 10−5 s. 2-32) Find the donor/acceptor concentrations for a GaAs P-N junction at which de Broglie wavelength (λ=h/√2m*E) of electrons/holes is equal to the width of the space charge region at 300K. Assume = 3kBT/2, mn*/mo=0.063, mp*/mo= 0.53, s =12.9, ni = 2.1×106 cm−3 and Na = Nd. 2-33) When a Si P+N junction is reverse-biased to 30V, the depletionlayer capacitance is 1.75 nF/cm2. If the maximum field at breakdown is 3×105 V/cm, find the breakdown voltage. Take s= 11.9. 2-34) For a P+N Si junction with Nd = 1016 cm−3, the breakdown voltage is 32V. Calculate the maximum electric field at the breakdown. 2-35) Repeat the solution to Example 2-7, with considering the internal zener diode resistance in breakdown, as rz = 2. 2-36) Consider a Si P-N junction solar cell of area 2cm2. If the doping of the solar cell is Na=1.7×1016 cm−3 and Nd = 5×1019 cm−3, Also, n =10 μs, τp =0.5μs, Dn =9.3 cm2/s, Dp =2.5 cm2/s, and IL = 95 mA, (i) calculate the open-circuit voltage, and (ii) determine the maximum output power of the solar cell at room temperature. 2-37) At room temperature, an ideal solar cell has a short-circuit current Isc= 3A and an open-circuit voltage Voc= 0.6 V. Calculate and sketch its power output as a function of operation voltage and find its fill factor.

146 Prof. Dr. Muhammad El-SABA

Fundamentals of Electronic Devices

Chapter 2

2-19. References [1] N.F. Mott, The Theory of Crystal Rectifiers, Proc. Roy. Soc. London, vol. A 171, pp.27-38, 1939. [2] R. S. Ohl, "Light-sensitive electric device," U.S. Patent 2,402,662. Filed May 27, 1941, Granted June 25, 1946. [3] W. Shockley, "The theory o£ P-N junctions in semiconductors and P-N junction transistors," Bell Syst. Tech. Journal., vol. 28, p.435, 1949. [4] W. Shockley, Electrons and Holes, Van Nostrand, N.J., 1950. [5] C. T. Sah, R. N. Noyce and W. Shockley, ―Carrier Generation and Recombination in P-N Junction and P-N Junction Characteristics,‖ Proc. IRE, Vol. 45, No. 9, p. 1228, 1957. [7] J. L. Moll, "The evolution of the theory for the voltage-current characteristic of P-N junctions," Proc. IRE, vol. 46, p.1076, 1958. [8] John L. Moll, "Variable capacitance with large capacity change," IRE Wescon Convention Record, Part 3, pp.32-36, 1959. [9] S. M. Sze and G. Gibbons, ―Avalanche breakdown voltages of abrupt and linearly graded P-N junctions in Ge, Si, GaAs, and GaP,‖ Applied Physics Letters, vol.8, p.111, 1966. [10] Chih-Tang Sah (University of Illinois) ―The spatial variation of the quasi-Fermi potentials in p-n junctions,‖ IEEE Transaction on Electron Devices, ED-13, 839-846, December 1966. [12] H.A. Watson, ―Microwave Semiconductor Devices and their Circuit Applications,‖ McGraw-Hill, 1969. [14] B. G. Streetman, Solid State Electronic Devices, Prentice Hall, Englewood Cliffs, 1972. [15] S.K. Ghandhi, Semiconductor Power Devices, John-Wiley Sons, New York, 1977. [17] E. S. Yang, Microelectronic devices, McGraw-Hill, NY, 1988. [19] Mike. J. Cooke, Semiconductor Devices, Prentice Hall International, UK, 1990. [22] K. Ismail "Electron resonant tunneling in Si/SiGe double barrier diodes". Applied Physics Letters, Vol. 59, p. 973, 1991. [29] S. M. Sze, Semiconductor Devices, Physics and Technology, JohnWiley Inc., 2d eEdition, 2002. [30] Antonio Luque, Hegedus, (Editors). Handbook of Photovoltaic Science and Engineering. John Wiley and Sons, 2003. [31] W. Koechner, Solid-State Laser Engineering, 6th Edition., Springer, Berlin , 2006. [32] Raymond T. Tung, The physics and chemistry of the Schottky barrier height, Appl. Phys. Rev., Volume 1, Issue 1, p.011304, 2014. 147 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 3

Bipolar Junction Transistors (BJT’s) Contents: 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7. 3-8. 3-9. 3-10.

3-11.

3-12. 3-13. 3-14.

Chapter Overview and Learning Objectives BJT Structure Theory of Operation Circuit Configurations BJT Operating Modes BJT Currents Static I-V Characteristics of a BJT BJT Models BJT Circuit Analysis (DC Analysis) Small Signal Model of a Bipolar Transistor 3-10.1. Hybrid- Model 3-10.1. Hybrid Parameters Model BJT as an Amplifier (AC Analysis) 3-11.1. Active Mode Biasing Schemes 3-11.2. Calculation of the AC Voltage Gain 3-11.3. AC Beta Factor 3-11.4. Examples BJT as a Switch BJT Switching Times Physical Limitations of the BJT 3-14.1. Breakdown Voltage 3-14.2. Maximum Current 3-14.3. Maximum Power 3-14.4. Safe Operating Area (SOA) 3-14.5. Thermal Derating 3-14.6. Variation of Current Gain with Collector Current 3-14.7. High Voltage Effects (Early Effect) 3-14.8. Kirk Effect

131 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices 3-15. BJT Fabrication Technology 3-16. Other BJT Structures 3-16.1. Unijunction Bipolar Transistor (UJT) 3-16.2. Hetrojunction Bipolar Transistor (HBT) 3-16.3. Resonant tunneling Bipolar Transistor (RTBT)

3-17. 3-18. 3-19. 3-20. 3-21. 3-22.

Laboratory Testing of a BJT Computer Simulation & Modeling Parameters Summary Problems Chapter Assessment References

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Chapter 3

Microelectronic & Nanoelectronic Devices

Chapter 3

Bipolar Junction Transistors (BJT) 3-1. Chapter Overview and Learning Objectives A bipolar junction transistor (BJT) is a semiconductor element made up of two P-N junctions. In this chapter, we present the fundamental concepts about BJTs and their basic circuits. We briefly demonstrate how to use such electronic devices to amplify and switch signals in different configurations. Upon Completion of this Chapter, the student should: Understand the principle function of bipolar transistors. Be acquainted with the circuit configurations and biasing methods of the BJT, Identify the different current components and the current amplification factor of the BJT Draw and explain the input and output I-V characteristics of the BJT, Distinguish between, cut off, active, and saturation region operation of a BJT, Be acquainted with the BJT circuit models (Ebers-Moll, and GummelPoon models), Be acquainted with the small signal equivalent circuit (hybrid-pi and h-parameter models) of the BJT, Apply the appropriate circuit models correctly, Know the phenomena dominate the switching of a BJT, Draw and explain the turn-on & turn-off characteristics of a BJT, Identify the BJT quirks and physical limitations, Interpret manufacturer datasheets and ratings of BJTs, Differentiate between different packages of a BJT, Know how to test a BJT, using a simple avometer, Know other forms of bipolar transistor, such as heterjunction bipolar,r transistor (HBT), and how they operate.

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Microelectronic & Nanoelectronic Devices

Chapter 3

3-2. BJT Structure There exist two types of bipolar junction transistors according to whether the central area is of type N or P. The two types of transistors are represented on figure 3-1(a). As shown in figure, the tow types are NPN and PNP BJT’s. Their study is led strictly in the same way and the properties of the one apply to the other.

Figure 3-1. P-N-P and N-P-N bipolar transistors and their circuit symbols.

Note 3-1. History of the Bipolar Transistor The history of bipolar transistor started about fifty years ago, after the World War II, when William Shockley decided to build a triode-like semiconductor device, to replace vacuum tube triodes with solid-state devices. He secured funding and lab space, and went to work on the problem with Brattain and John Bardeen. The key to the development of the transistor was the further understanding of the process of the electron mobility in a semiconductor. It was realized that if there was some way to control the flow of electrons from the emitter to the collector of the newly discovered diode, one could build an amplifier. The Bell team made many attempts to build such a system with various tools, but generally failed. Setups where the contacts were close enough were invariably as fragile as the original cat's whisker detectors had been. Their work led them first to the point-contact transistor. The following figure shows the schematic of the first point-contact transistor. They made it from strips of gold foil on a plastic triangle, pushed down into contact with slab of germanium. In 1948, Bells Lab unveiled the transistor. 134 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 3

They decided to name it transistor instead of Point-contact solid state amplifier. John Pierce invented the name, combining trans-resistance with the ending common to devices.

Later, Shockley made the bipolar Junction transistor (sandwich). This transistor was more practical and easier to fabricate. The bipolar junction transistor was the first solid-state amplifier element and started the solidstate electronics revolution. 135 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 3

3-3. Theory of Operation of the BJT Figure 3-2 shows a schematic structure of a P-N-P bipolar junction transistor. As shown, the BJT consists of two back-to-back P-N junctions, who share a thin common base (termed B). Contacts are made to all three regions, including the emitter (termed E) and collector (termed C). The device is called bipolar since its operation involves both types of charge carriers; electrons and holes. Note that the emitter current, IE, is equal to the sum of the collector current, IC, and the base current, IB, that’s (IE = IC + IB). Actually, a small part of the emitter current recombines in the base region so that IC = F IE +Is, where F is called the forward current gain (typically 0.99) and Is is the reverse saturation current of the collector junction.

Fig. 3-2. Schematic structure of a P-N-P bipolar junction transistor.

3-4. BJT Circuit Configurations The current-voltage (I-V) characteristics of the bipolar transistors consist of the relations between the currents and input voltages of the transistor. According to the adopted circuit configuration, the I-V characteristics will be different. There exist three configurations for the bipolar transistors, namely: 1- Common-base (C-B) configuration, 2- Common-emitter (C-E) configuration, and 3- Common collector (C-C or emitter follower) configuration. The following figure depicts the first two configurations. 136 Prof. Dr. Muhammad El-SABA

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Fig. 3-3. Principal circuit configurations of a bipolar junction transistor

3-5. BJT Operating Modes The BJT has 4 possible operation modes, as shown in figure 3-4 and the following table. While the forward-active mode of operation is the most useful bias mode when using a bipolar junction transistor as an amplifier, the other bias modes are useful when using the device as a switch. In the reverse-active mode, we reverse the function of the emitter and the collector. We reverse bias the base-emitter junction and forward bias the base-collector junction, or VBE < 0 and VBC > 0. In this mode we replace the emitter parameters by the collector parameters.

Fig. 3-4. Different operation modes of a BJT. Table 3-1. BJT operation modes.

B-E Junction

B-C Junction Forward

Reverse

Forward

Saturation (ON)

Reverse

Reverse-Active (Bad Amplifier)

Forward-Active (Amplifier) Cut-off

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Microelectronic & Nanoelectronic Devices

Chapter 3

3-6. BJT Currents Figure 3-5 depicts the current components of a P-N-P transistor. As shown in figure, the emitter base junction is forward biased by VEB and the collector-base junction is reverse biased by VCB. The majority carriers in the emitter (holes) are injected by the aid of the forward bias into the base region, Then, the injected holes are diffused inside the N-base and part of them reaches the collector boundary where they are extracted (collected) by the aid of the base-collector reverse bias. The total emitter current is the sum of the hole diffusion current, IE,n, the electron diffusion current, IE,p and the base-emitter depletion layer recombination current, Ir,d. (3-1)

Fig. 3-5. Current components of a P-N-P bipolar junction transistor.

The total collector current is the electron diffusion current, IE,n, minus the base recombination current, Ir,B. (3-2) The base current is the sum of the hole diffusion current, IE,p, the base recombination current, Ir,B and the base-emitter depletion layer recombination current, Ir,d. (3-3) 138 Prof. Dr. Muhammad El-SABA

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The transport factor, , is defined as the ratio of the collector and emitter current: (3-4) Using Kirchoff's Current Law (KCL), we find that the base current equals the difference between the emitter and collector current. The common emitter current gain, , is defined as the ratio of the collector and base current as follows: (3-5) This explains how a bipolar junction transistor can provide current amplification. If the collector current is almost equal to the emitter current, the transport factor, , approaches one. The current gain, , can therefore become much larger than one. To facilitate further analysis, we now rewrite the transport factor, , as the product of the emitter efficiency, E, the base transport factor, T, and the depletion layer recombination factor, r.

= E Tr.

(3-6)

The emitter efficiency, E, is defined as the ratio of the electron current in the emitter, IE,n, to the sum of the electron and hole current diffusing across the base-emitter junction, IE,n + IE,p.



(3-7a)

Assuming constant doping concentrations in emitter and base (NE, NB) and constants diffusion coefficients of minority carriers (Dp,E , Dn,B), the above relation may be related to the BJT physical parameters as follows:

E = 1/[1+(IE,p /IE,n) ] ≈ 1/[1+ (NBWB Dn,E)( NEWE Dp,B)] (3-7b)

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Microelectronic & Nanoelectronic Devices

Chapter 3

The base transport factor, T, equals the ratio of the current due to electrons injected in the collector, to the current due to electrons injected in the base. (3-8a) Again, assuming constant doping concentrations coefficients, the base transport factor may be given by:

and

T = IC,n /IE,n = sech(WB /Lp,B ) ≈ 1- ½ (WB / Lp,B )2

diffusion (3-8b)

where Ln,B = √(Dp,B p) is the mean free length of minority carriers (electrons) in the P-base of an NPN BJT, Dp,B is their diffusion coefficient and p is their lifetime. Recombination in the depletion-region of the base-emitter junction further reduces the current gain, as it increases the emitter current without increasing the collector current. The depletion layer recombination factor, r, equals the ratio of the current due to electron and hole diffusion across the base-emitter junction to the total emitter current:

r = (IE - I r,d) / IE = 1 – ( Ir,d / IE)

(3-9)

This parameter is voltage-dependent, because the recombination current in the emitter-base depletion region depends on the junction voltage (VEB). However, for simplicity, we may neglect recombination in the E-B depletion region and consider r ≈1. Example 3-1 Consider a PNP BJT with emitter doping of 1018 cm-3 and base doping of 1017 cm-3. The quasi-neutral region width in the emitter is 1 m and 0.2 m in the base. Take n = 1000 cm2/V.s and p = 300 cm2/V.s. The minority carrier lifetime in the base is 10ns. The BJT when it is biased in the forward active mode. Calculate the following parameters of the BJT: (i) the emitter efficiency, (ii) the base transport factor, and (iii) the current gain Assume there is no recombination in the depletion region. 140 Prof. Dr. Muhammad El-SABA

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Solution The emitter efficiency of a PNP BJT is given by E = IE,p / (IE,p + IE,n), and may be approximated as follows:

Substituting the emitter and base doping concentrations (NE, NB) and widths (wE, wB) as well as their diffusion constants (Dn,B, Dp,E), results inE =0.995. Similarly, the base transport factor T ≈ 1- ½ (WB / Lp,B)2, which may be approximated as:

If we neglect the recombination in the E-B depletion region (r =1), then the common-base current gain = E T = 0.993 and the common emitter current gain  is given by:

The above current components can be calculated and related to the BJT physical parameters, by substituting the minority carrier distributions and the electrical potential into the semiconductor current equations, in the different regions of the transistor, at different bias conditions. The minority carrier distributions, themselves, can be obtained by solving the semiconductor continuity equations, using the appropriate boundary conditions. Usually, we make use of the regional approach, that’s to divide the BJT into quasi-neutral regions and space charge regions (around metallurgical junctions). Thus, the electrical potential () can be obtained by solving the Poisson equation inside the space charge regions (SCR). The energy band diagram across an NPN BJT in the forward mode is shown in figure 3-6(a). This distribution, can be obtained from the electrical potential (E = -e), which can be obtained by solving the Poisson equation, in space-charge regions. 141 Prof. Dr. Muhammad El-SABA

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Fig. 3-6(a). Energy band diagram across an NPN BJT in the forward active mode.

Note that the electrical potential and hence the energy bands are flat in quasi-neutral regions (QNR), as shown in figure 3-6(b). 142 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

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Fig. 3-6(b). Energy band diagram across an NPN BJT in the forward active mode.

After solving Poisson's equation in the space-charge regions, we solve the semiconductor continuity equations in the quasi-neutral regions of the emitter, the base and the collector to get the minority carrier distributions (n,p). The distributions of minority carriers, together with the electrostatic potential, can be then utilized to determine the BJT current as functions of the applied bias voltages and other transistor physical parameters. An approximate solution of the continuity equations in one-dimension can be obtained by assuming the following conditions: Low level injection (injected carriers in the base: nB = nB-nBo 0. 4) Assume that BJT is in active linear region. Let IE ≈ IC = β.I B . Calculate VC E from CE-KVL. 4a) If VC E > Vγ, then BJT is in active-linear region. You are done. 4b) If VC E < Vγ, then BJT is not in active-linear region. It is in saturation. Let VC E = Vsat and compute IC from CE-KVL. You should find that I C < β I B. You are done. Example 3-3: Calculate the quiescent point of the following BJT circuit. Take β = 100.

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Solution BE-KVL: 4 = 40× 103IB +VBE CE-KVL: 12 = 103 IC +VC E , Assume BJT is in cut-OFF. Set IB = 0 in BE-KVL: BE-KVL: 4 = 40× 103IB + VBE  VBE= 4 > Vγ ( 0 .7 V ) , So BJT is not in cut OFF and BJT is ON. Set VBE = 0.7V and use BE-KVL to find IB. BE-KVL: 4= 40× 103IB +VBE  IB = 4−0.7Then 40,000 IB = 82.5µA Assume BJT in active linear mode, Find IC = β I B and use CE-KVL to find VC E : IC= β IB= 100 IB= 8 .25 mA CE-KVL: 12 = 1, 000 IC + VC E  VC E = 12 − 8.25 = 3.75 V As VC E = 3.75 > Vγ, the BJT is indeed in active-linear and we have: VBE = 0.7 V, IB = 82.5µA, IE ≈ IC = 8.25 mA, and VC E = 3.75 V. Example 3-4: Calculate the quiescent point parameters of the following BJT circuit. Take β = 100.

Solution BE-KVL: 4 = 40× 103 IB + VBE + 103 IE CE-KVL: 12 = 1, 000 IC + VC E + 1, 000 IE Assume BJT is in cut-OFF. Set IB = 0 and IE = IC = 0 in BE-KVL: BE-KVL: 4 = 40× 103 IB +VBE + 103 IE  VBE = 4 > 0.7 V So BJT is not in cut OFF and VBE = 0.7 V and iB > 0. Here, we cannot find iB right away from BE-KVL as it also contains IE. Assume BJT is in active linear, IE ≈ IC = β I B: BE-KVL: 4 = 40× 103IB + VBE + 103βI B 156 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 3

4− 0.7 = (40×103 + 103×100) IB. Then IB=24µ IE ≈ iC = β IB = 2 .4 mA CE-KVL: 12 = 1000 IC + VC E + 1000 IE. VCE = 12− 4.8 = 7.2 V As VC E = 7.2> V γ , the BJT is indeed in active-linear and we have: VBE = 0.7 V, IB = 24µA, IE ≈ IC= 2 .4 mA, and VC E = 7 .2 V. Example 3-5 For the example above, find the load like equation and the Q-point of the BJT graphically: Solution The operating point of a BJT can be found graphically using the concept of a load line. For BJTs, the load line is the relationship between IC and VC E that is imposed on BJT by the external circuit. The intersection of the load line with the BJT characteristics represent a pair of IC and VC E values which satisfy both conditions and, therefore, is the operating point of the BJT (often called the Q point for Quiescent point). The equation of a load line for a BJT should include only IC and VC E (no other unknowns). This equation is usually found by writing a KVL around a loop with VC E . KVL: 12 = 1000 IC + VC E +1000 IE But IE = IC_+ IB = 1.01 IC Then the load line equation is 2010 IC + VC E = 12 The load line, the IC-VC E characteristics of a BJT, and the Q-point are all shown below.

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3-10. Small Signal Models of a BJT At small signals the transistor characteristics can be considered linear around a specific quiescent point (Q-point). Therefore, the transistor can be replaced by an equivalent network (usually 2-port network), whose parameters are related to the BJT physical characteristics, such as the input resistance and beta factor (current gain). 3-10.1. Hybrid- Model Figure 3-12 depicts a small signal equivalent circuit for a bipolar junction transistor. This model is called the hybrid- model of a BJT. It consists of input impedance (rbé), an output impedance (rce) and a voltage controlled current source described by the transconductance (gm).

Fig. 3-12. BJT equivalent circuit at low frequency.

The above model is only valid at low frequencies, because it does not take the BJT inter-electrodes capacitances. Figure 3-13 shows a highfrequency version of the hybrid- model. This model is sometimes called the Giacoletto model. Note the existence of the BJT parasitic capacitors, Cb’c and Cb’e. The so called cutoff frequency, of the BJT, is given by:

fT = F / [2 rb’s (Cb’e + Cb’c)]

(3-20)

For the 2N2222A transistor with Q-point (IC =10mA, VCE =10V), we have: F =225, gm = 0.385S, rb’e = F /gm = 585, rbb’= 19, Cb’c = 8pF, Cb’e = 196pF, rb’c =1.5M, rce = 22.5 k, fT =300 MHz. 158 Prof. Dr. Muhammad El-SABA

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Fig. 3-13. BJT equivalent circuit at high frequency (Giacoletto model)

3-10-2. Hybrid-Parameters Model Any linear two-port network can be described by the so-called hybridparameter model. It consists of input impedance (h11) an output conductance (h22) and a current controlled current source described by the current amplification factor (h21) and voltage controlled voltage source described by (h12), as shown in the following figure. By the aid of the hybrid parameters model we can describe the input voltages (v1) and output current (i2) of the network in terms of the input current (i1) and output voltage (v2), as follows:

v1 = h11 i1 + h12 v2

(3-21)

i2 = h21 i1 + h22 v2

(3-21)

Fig. 3-14. Hybrid parameter model of a linear two-port network.

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We can make use of such hybrid parameter model to describe the BJT behavior for small signals, where the transistor characteristics can be considered linear around a certain quiescent point (DC bias). For instance, figure 3-15 depicts the hybrid circuit model of BJT in its common emitter (C-E) configuration. It consists of input impedance (hie), an output conductance (hoe) and a current controlled current source described by the current amplification factor (hfe) and voltage controlled voltage source described by (hre).

vbe = hie ib + hre vce

(3-22a)

ic = hfe ib + h1 vce

(3-22a)

Fig. 3-15. Hybrid parameter model of a common emitter BJT .

The hybrid parameters may be related to the Giacoletto (hybrid-) model parameters, as follows:

hfe = rbé gm

(3-23a)

hre = rbé / (rbé + rbc)  rbé / rbc

(3-23a)

hoe = 1/ rce + 1 / (rb’c + rbé) + hre rbé  1/ rce

(3-23a)

These parameters can be also related to the other conventional 2-port network parameters, such as the impedance z-parameters and the admittance y-parameters.

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3-11. BJT as an Amplifier (AC Analysis) When the BJT is operating in the active region, (i.e., when the baseemitter junction is forward biased with VBE > V) while the base collector junction is reverse biased), then IB > 0 and IC = F IB and it can amplify small input signals. 3-11.1. Active Mode Biasing Schemes The following figures show the basic biasing schemes of a BJT in the forward active mode (as an amplifier), in its three possible configurations. The corresponding real circuits are also shown besides.

C-B Basic Bias circuit

C-B Practical Amplifier Circuit

Fig. 3-16.Application of the BJT as an amplifier, in common-base (C-B) configuration

C-E Basic Bias circuit

C-E Practical Amplifier Circuit

Fig. 3-17. Application of the BJT as an amplifier, in common-base (C-E) configuration

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C-C (Emitter follower) Basic Bias circuit

Chapter 3

C-C Practical Amplifier Circuit

Fig. 3-18. Application of the BJT as an amplifier, in common-collector (C-C) or emitter follower configuration

3-11.2. Calculation of the AC Voltage Gain Consider the common-emitter circuit in figure 3-20, where the base bias Vbb is supplemented with a small signal alternating source vb(t). In this case the total base current is composed of a quiescent value (say IB2) and a superimposed alternating value ib(t). We denote the total base current as the sum iB(t) =IB+ ib(t). Also, the total collector current is iC(t) =IC+ic(t). Similarly, the total collector voltage is vCE(t)=VCE+ vce(t). Figure 3-20 depicts the variation of the output voltage vo(t) = vCE(t) as a result of the variation of iB(t) from IB2 up to IB3 and down to IB1. As shown, the output voltage swing is much greater than the input voltage swing, and the AC voltage gain is given by:

Av = vo / vb= VCE/(VBE +RBIB) = RcIC/[(rbe+RB)IB] ≈ - FRc/(rbe+RB)]

(3-24)

Here we neglect the output resistance of the transistor (rce), which may be much greater than the load resistance RC. We may also consider RB much greater than the BJT input resistance, rbe, which is typically about 10 We can use one of the simple AC models of the BJT, such as the hparameters model shown in figure 3-15 , to derive the AC voltage gain in a much easier way. Note that the trans-conductance of the BJT (gm) is

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related to the forward beta factor such that F = gmrb’e. Note also that gm can be obtained from the DC analysis (gm=VT/IC ≈1/40IC at 300K).

Fig. 3-20. BJT operation as an amplifier.

Also, the current source (gm vb’e) is equal to F ib, which describes the amplification factor of the BJT. The input resistance in the C-E configuration is given by rbe = rb’e + rbb’. The base spreading resistance rbb’ is sometimes neglected so that vb’e ≈ vbe. Note also that all DC sources (VBB and VCC) are grounded in the AC equivalent circuit of the amplifier. 3-11.3. AC Beta Factor It should be also noted that the beta factor (F) mentioned so far is only constant (F = gm rb’e) at low frequencies (up to several MHz). For this reason it is sometimes called the DC beta factor. Actually, the beta factor is frequency dependent, as shown in figure 3-21. The frequency dependence of the forward beta factor (F), may be described by the following equation:

F = Fo / [1+ j2 rb’e Cb’e]

(3-23)

While the unity gain frequency, fT, is an important figure of merit of a bipolar transistor, another even more important figure of merit is the 163 Prof. Dr. Muhammad El-SABA

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maximum oscillation frequency, fMAX. This figure of merit predicts the unity power gain frequency and as a result indicates the maximum frequency at which useful power gain can be expected from a device.

Fig. 3-21. Current amplification factor versus frequency.

The maximum oscillation frequency, fMAX, is linked to the transit frequency, fT, and is obtained from:

fMAX = [ fT / (2 rbe Cb’c )] 1/2

(3-24)

where rbe = rb’e + rbb’ is the total base resistance and Cb’ç is the basecollector capscitsnce. 3-11.4. Examples The following examples demonstrate the complete analysis of BJT circuits and the calculation of its voltage gain. For simplicity, we denote the forward beta factor as β, and consider it as constant. Example 3-6. Consider the following BJT circuit. Calculate the quiescent point and the voltage gain Av = (vo/vin). Take β = 100. 164 Prof. Dr. Muhammad El-SABA

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Solution Using the superposition principle, the analysis may be divided into DC analysis and AC analysis, as shown in the following figure.

DC Analysis We start with the DC analysis to check if the BJT is in active mode or not BE-KVL: 4 = 40× 103 IB + VBE + 103 IE CE-KVL: 12 = 1, 000 IC + VC E + 1, 000 IE Assume BJT is in cut-OFF. Set IB = 0 and IE = IC = 0 in BE-KVL: BE-KVL: 4 = 40× 103 IB +VBE + 103 IE  VBE = 4 > 0.7 V So BJT is not in cut OFF and VBE = 0.7 V and iB > 0. Here, we cannot find iB right away from BE-KVL as it also contains IE. Assume BJT is in active linear, IE ≈ IC = β I B: BE-KVL: 4 = 40× 103IB + VBE + 103βI B 4− 0.7 = (40×103 + 103×100) IB. Then IB=24µ IE ≈ iC = β IB = 2 .4 mA CE-KVL: 12 = 1000 IC + VC E + 1000 IE. VCE = 12− 4.8 = 7.2 V 165 Prof. Dr. Muhammad El-SABA

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As VC E = 7.2> V γ , the BJT is indeed in active-linear and we have: VBE = 0.7 V, IB = 24µA, IE ≈ IC= 2 .4 mA, and VC E = 7 .2 V. AC Analysis After confirming that the BJT is in active mode, we proceed with the AC Analysis. Here we short all the DC battery sources and replace the BJT with a suitable small signal model (e.g., the h-parameter model).

For simplicity, we may consider hfe =  and neglect hre and hoe and (unless they are given) and then redraw the equivalent circuit as follows

Now we calculate the voltage gain: Av = (vo/vin) = -ic Rc = - ib Rc. The base current can be calculated from the E-B KVL ib = vin /[RB+hie+(+1)RB]. Substituting ib in the above equation results in Av = - Rc/[RB+hie+(+1)RB] Note that can be calculated from the DC analysis hie ≈ Vt/IE =1k If (+1)RB>>RB+hie, then the AC voltage gain may be approximated as: Av = - Rc/[(+1)RB] ≈ - Rc/ RB which is a well know formula for the common-emitter amplifier. 3-12. BJT as a Switch 166 Prof. Dr. Muhammad El-SABA

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When the BJT leaves the active region, it enters one of two extreme cases (cutoff or saturation), as shown in Fig. 3-22. When the input voltage is reduced to zero Volt (actually, anything under the cut-in voltage; VBE ≈ 0.6V in Si BJTs), there will be no forward bias to the emitter-base junction, and the transistor does not conduct. Therefore enters cutoff and no current flows through the collector resistor (IC ≈ 0) and hence the collector output voltage is VCC. Alternatively, when the applied base voltage is sufficiently high, the collector-emitter voltage reaches its minimum value (VCEsat) and the collector current reaches its maximum value ICsat = (VCC -VCEsat)/RC.

Fig. 3-22. BJT equivalent circuit in cutoff and saturation states.

Note that, if the base current is further increased (from the base drive circuit), the collector current cannot exceed this maximum collector current (ICmax). In fact, the BJT, in saturation is no longer an amplifier and the condition of saturation is sometimes written in the following form:

IB ≥ ICmax /

or

 IB ≥ (VCC – VCESAT) / RC

(3-25)

Consider the BJT switching circuit in figure 3-23. We will only be applying one of two voltages to the input 0 V (logic 0) or VCC (logic 1). We will assume an ordinary N-P-N transistor, with a reasonable current gain, an emitter-base forward voltage of 0.8V, and a collector-emitter saturation voltage of about 0.1V. The base resistor is assumed 470 and the collector resistor is 640. The BJT operates as follows.

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Fig. 3-23. BJT switching circuit and characteristics in the saturation and cutoff

Fig. 3-24. BJT simple switching circuit

When the input voltage is zero volt (actually, anything under 0.6V), there will be no forward bias to the emitter-base junction, and the transistor does not conduct. Therefore no current flows through the collector resistor, and the output voltage is VCC. Hence, logic 0 input results in logic 1 output. The amount of forward drop that switches a silicon NPN BJT is almost 0.8V, and referred to as VBESAT. So, when Vi ≥ VBEsat = 0.8V then the base current becomes:

IB = IBsat = (Vi – VBESAT) / RB

(3-26)

For those who like the mathematics, we assume a similar output circuit connected to this input, as shown in figure 3-20. Thus, we have a voltage of 5 - 0.8 = 4.2V applied across a series combination of a 640 output 168 Prof. Dr. Muhammad El-SABA

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resistor and a 470 input resistor. This gives us a base forward current of:

IB2 = IBsat= (5-0.8)/ (RB + RC) =4.2V/1110 = 3.78 mA (3-27) Then IC2 will continue to increase until it reaches its saturation value:

IC2 = ICsat = (Vcc – VCEsat ) / Rc

(3-28)

Also, Vo drops to the saturation value VCEsat=0.1V. The time it takes for the collector current Ic to increase from 0 to 0.1 Icsat is called the delay time (td).

Fig. 3-25. BJT switching ON circuit, via another switching OFF BJT.

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3-13. BJT Switching Times The time it takes for IC to increase from 0.1 Icsat to 0.9 Icsat is called the rise time (tr). The turn-ON time (tON) is the sum of both the delay time td and the rise time tr, and given by:

t ON

  1  t d  t r   B .ln  IC  1    F .I B 

     

(3-29)

where B is the base minority carriers lifetime. When the BJT is deeply driven into saturation then IB continues to increase while IC is saturated at ICsat, such that:

ICsat / (F IB) ≤ 1

(3-30)

Alternatively, when the transistor is switched OFF and Vi < VBE(about 0.6V for Si BJT’s) then the transistor will still conduct in the reverse direction for a while, until the storage charge in the base disappears.

IB = (Vi - VBE) / RB.

(3-31)

The time it takes for IC to decrease from ICsat to 0.9 ICsat is called the storage time (ts).

I Csat   I   B2   F  ts   s   I  I Csat   B1   F  

(3-32)

where s is the storage lifetime. After the storage charge vanishes, then the base current goes to zero and the transistor is open.

IB = 0 , IC = 0 , Vo = VCE ≈ VCC.

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(3-33)

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The time it takes for Ic to decrease from 0.9 Icsat to 0.1 Icsat is called the fall time (tf). The switching time (time it takes for Ic to decrease from Icsat to 0) is called the turn-OFF time (tOFF) and is given by:

tOFF = ts + tf

(3-34)

The propagation delay of the BJT inverter is the sum of (tON + tOFF). Figure 3-21 depicts the BJT switching waveforms and switching times. One can distinguish the following switching times: 1- td delay time: it is the time necessary to charge the line capacity of the Emitter junction bases so that the first electrons injected into the base typically reach the collector. For transistor 2N2219, td = 10ns. 2- tr rise time: it is the time which puts the collector current to pass from 0.1 ICsat to 0.9 ICsat. For 2N2219 at IC =150mA; IB = 15mA, tr=25ns. 3- ts storage time: It is time necessary to evacuate the load stored in the base. For 2N 2219 with IC =150 mA; IB = 15mA, we have ts = 200ns. 4- tf fall time: The time it takes for Ic to decrease from 0.9 Icsat to 0.1 Icsat Actually the storage time may be divided into 2 times: ts1 (where IB = constant and IC = constant) is the time which the transistor spends to pass from the mode of super-saturation to the active mode. ts2 (where IC deceases wherease IB = constant) is time necessary to evacuate the stored load charge in extreme cases of saturation. In order to decrease the time of storage time ts it is necessary to avoid supersaturating the transistor. For that, one can place a diode between collector and bases in the way indicated by figure.3-18. This diode is called anti-saturation diode. It is generally a Schottky barrier diode (SBD) and the transistor thus made up is called Schottky transistor. With such diodes the collector-emitter voltage will be always reverse biased by at least, the following difference:

VCE = VBE – VSD = 0.7 – 0.45 = 0.25V.

(3-35)

where VSD is the nominal forward drop of a Schottky diodes at 300K. More details about Schottky diodes will be presented in Chapter 4. 171 Prof. Dr. Muhammad El-SABA

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Fig. 3-26. BJT Switching times and waveforms

Fig. 3-27. Schottky transistor structure and circuit symbol

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3-14. Physical Limitations of the BJT Like all electronic devices, the bipolar transistor can function only within well defined limits of voltage and currents. Data sheets usually have a full set of charts, showing the various device parameters and limitations as a function of voltage, current and frequency. Without a thorough knowledge of the device limits, the device may cease to work and may even breakdown. In this section we discuss the physical limitations that should be taken into account, in order to ensure a reliable operation of the transistor. The basic limitations are grouped in the following categories: Voltage limitations (Breakdown voltages, and Early effect), Current limitations (Fall of beta factor current gain and Kirk effect), Power limitations (safe operating area and thermal derating). 3.14.1. Voltage Limitations (Breakdown Voltage) The avalanche breakdown of the transistor junctions is an important effect, which arises at high voltages. Particularly, the reverse bias of the collector junction, may lead to a high electric field, which leads to an avalanche multiplication, by impact ionization. Figure 3-28 shows the avalanche breakdown on the BJT output characteristics (Ic-Vce), at high collector voltages. In common emitter configuration, when one increases the base-emitter voltage VBE, the field around the E-B junction increases and an avalanche multiplication mechanism occurs. Data sheets of transistors define a certain value of VCE (termed VCEBO and sometimes as BVCEO), above which the transistor breaks down, when the base terminal is open. This voltage is represented on the figure 3-28.

Fig. 3-28. Effect of high voltage on the BJT output (Ic-Vce) characteristics

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Example 3-7. Determine the open-emitter breakdown voltage (BVCB0) for a power bipolar NPN transistor with the following parameters. The N+ emitter has a doping concentration NE=2x1019 cm-3 and thickness WE= 10um. The Pbase has a doping concentration NB=2x1017 cm-3 and thickness WB =10um. The N-collector drift region has a doping ND=2x1014 cm-3 and thickness WD=40um. Confirm that the left depletion region has not penetrated the entire base region. Solution: Considering base doping to be much higher than the collector doping, the electric field profile (x) in the collector can be sketched as follows:

The value of the critical electric field for breakdown in Si is given by:

C (Si) = 4010 ND1.8 The critical electric field for breakdown of the N-drift region doping concentration of 2x1014 cm-3 is then 2.46 x105 V/cm. The punch-through breakdown voltage for the P-base/N-drift region junction is: BVCBO= C WD- ½ eNDWD2/s Using the values of depletion region width WD and uniform doping ND = 2x1014 cm-3 yield an open-emitter breakdown voltage (BVCB0) of 737V. Example 3-8. A BJT has a common emitter current gain of 50 and open-emitter breakdown voltage of 1000V. Determine its open-base breakdown voltage. Solution The open-base breakdown voltage (BVCBO) is related to the open-emitter breakdown voltage (BVCEO) and the common emitter current gain by: BVCEO = BVCBO /(1+Fo)1/n where n 6 for Si. Substituting yields BVCBO of 519V. 174 Prof. Dr. Muhammad El-SABA

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3-14.2. Early Effect When the voltages applied to the base-emitter and base-collector junctions are changed, the depletion layer widths and the quasi-neutral regions vary as well. This causes the collector current to vary with the collector-emitter voltage as illustrated in Fig. 3-29. A variation of the base-collector voltage results in a variation of the quasi-neutral width in the base. The gradient of the minority-carrier density in the base therefore changes, yielding an increased collector current as the collector-base current is increased. This effect is referred to as the Early effect.

Fig. 3-29. Effect of high voltage on minority carrier distribution in the base.

The Early effect is observed as an increase in the collector current with increasing collector-emitter voltage as illustrated in figure 3-24. The Early voltage, VA, is obtained by drawing a line tangential to the transistor I-V characteristic at the point of interest. The Early voltage equals the horizontal distance between the point chosen on the I-V characteristics and the intersection between the tangential line and the horizontal axis. It is indicated on the figure by the horizontal arrow. The change of the collector current when changing the collector-emitter voltage is primarily due to the variation of the base-collector voltage, since the base-emitter junction is forward biased. The collector current depends on the basecollector voltage since the base-collector depletion layer width varies, which also causes the quasi-neutral width, in the base to vary. This variation can be calculated from the transistor characteristics, as follows: 175 Prof. Dr. Muhammad El-SABA

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dI C dI I dWB  C  C . dVCE dVCB WB dVCE

Chapter 3

(3-36a)

This variation can be expressed by the Early voltage, VA, which calculates the voltage variation that would result in zero collector current.

VA 

IC dI C / dVCE

(3-36b)

We can also prove that the Early voltage VA is equal to the base charge, QB, divided by the base-collector junction capacitance CBC = s/(xp + xn), where xp and xn are the extensions of Base-Collector depletion region width, on both sides of the base-collector junction.

VA 

QB eN BWB  C BC  s /( x p  xn )

(3-37a)

Which can be put in the following form:

(3-37b) with KE = 8 for Si devices. The Early voltage can also be related to the BJT output resistance, rc, as follows: rc 

dVCE V A  dI C IC

(3-38)

In addition to the Early effect, there is a less pronounced effect due to the variation of the base-emitter voltage, which changes the ideality factor of the collector current. However, the effect at the base-emitter junction is much smaller since the base-emitter junction capacitance is larger and the base-emitter voltage variation is very limited since the junction is forward biased. This effect leads to a variation in the ideality factor of the B-E junction, which is given by:



V C 1 dVBE .  1  t . BE Vt d (ln I C ) V A C BC 176

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(3-39a)

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The collector current is therefore given by:

IC = ICs [ exp (VBE /Vt ) -1]

(3-39b)

where the ICs is the collector reverse saturation current.

Fig. 3-30. Effect of high voltage on minority carrier distribution in the base.

Example 3-9 What is the Early voltage for the bipolar transistor described in the above examples? Solution: The Early voltage is given by:

where KE is a constant and ND is the collector (drift region) doping concentration, NAB is the base doping, WB is the base width. Using the parameters with KE = 8 yields an Early voltage of 3.1 x10 7 V. 3.14.3. Current Limitations (Maximum Current) The emitter area determines the maximum current capability of the device. The emitter current ratings depend on the emitter area and bonding wire size. Therefore, excessive collector currents may damage the transistor. So, when designing a specific BJT, we should take care if the load such that the maximum current allowed is not exceeded. 177 Prof. Dr. Muhammad El-SABA

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3.14.4. Variation of the Current Gain with Collector Current In all the precedent discussion, we considered the DC current gain of common emitter transistor (F) as constant. Actually, this value decreases at very high collector currents, because of the high injection level (base conductivity modulation). Also, the beta factor at small currents is not constant because of the base recombination current, which limits the current gain at small emitter (collector) currents.

Fig. 3-31. Variation of the DC current amplification factor (F) with collector current

The forward current gain (F) at high current levels can be expressed as:

F (JC ) 

 Fo

1  ( J C / JW )

(3-40a)

where BFO is the low injection level current gain (sometimes termed BLL) and JW is called the Webster current density1, which is given by:

JW = e DnB NB/WB

(3-41b)

Here, DnB is the diffusion constant of minority carriers in the base, NAB is the doping concentration (assumed constant) and WB is the base width. The high-level injection (HLI) means the increase of the level of injected minority carriers in the base (electrons in NPN transistor) above the base concentration. That's when nB = nB - nBo > NB., as shown in the following figure. The HLI affects the characteristics of BJT and cause the fall-off of the beta factor at high collector currents. 1

The Webster current is sometimes referred to as the corner current and termed as IKF in BJT models.

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Fig. 3-32. Carrier distributions in the base of an NPN BJT at low-level injection (LLI) and high-level injection (HLI).

3-14.5. Kirk Effect The Kirk effect is the apparent base-width increase in a BJT at high collector current densities. The base widening into the collector drift region of a BJT is well known to be the cause of the falloff of the current gain and cutoff frequency at high collector current densities. For an NPN silicon bipolar transistor with a uniformly doped drift region, the Kirk effect was found to begin when the collector current density reaches a critical value, called the Kirk current density. The Kirk current density can be expressed in terms of the device physical parameters and the applied collector bias voltage:

(3-42)

where ND is the doping concentration in the collector drift region, vsat is the carrier saturation velocity, VC is the applied voltage and WN is the collector drift length. 3.14.6. Maximum Power In order to avoid a too significant heating with the collector, the power dissipated with the collector must remain lower than a maximum value (Pmax) such that: 179 Prof. Dr. Muhammad El-SABA

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The power limiting area is thus a hyperbole in the plan (Ic, Vce). In particular the operating point Q of the transistor must be inside the zone of reliable operation, as shown in Fig. 3-33.

Fig. 3-33. Physical limitations and safe operating area of a BJT

3.14.7. Safe Operating Area (SOA) of a BJT In the design phase, all are physical limitations are important, but the most important of all are the thermal derating and safe operating area (SOA). There is a great deal you need to know to be able to make proper use of the charts of these parameters. Fig. 3-28 shows the practical SOA curve for a switching transistor (MJL4381A). In such a case, it is not only important to determine the maximum rating values of current and voltages, but also the switching periods, along which these values can be applied. As shown in figure, repetitive peak currents of up to 30A are only permissible for less than 10ms, with collector voltages up to 30V, when the junction temperature is 25°. This represents a peak power of 300W (the device rating is 230W). Therefore, the transistor will be stressed and these conditions must not be allowed to continue beyond the time specified (10ms). 180 Prof. Dr. Muhammad El-SABA

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For longer stress periods (e.g., for 1 sec), the SOA shrinks and the device limitations should be reduced. For instance, for 1 second, the maximum rated current of 15A may only be drawn at collector-emitter voltages below 15V. This region is limited by the maximum rated current of the transistor, and will never allow continuous operation at maximum power because of the thermal derating. Remember that all peak currents and power dissipations in the above chart are for a junction temperature of 25°. Actually, no transistor can maintain high temperature for long time in real life. Therefore there is a thermal resistance between the die and case, and further thermal resistance between case and heatsink.

Fig. 3-34. SOA of a bipolar transistor, for different stress times, at 25C.

Thus, the devices must be derated by 1.84° C/W above 25°, as shown in figure 3-35. The thermal resistance from junction to ambient air (via the case, and heatsink) can be expected to be around 1.5-2° C/W (for a big heatsink), so all dissipation limits quoted can be expected to be as little as 1/2 of those shown in the specifications. 3.14.8. Thermal Derating Under ideal conditions, a transistor's power dissipation rating refers to the maximum average power that the device can handle, with the junction temperature at 25° C. 181 Prof. Dr. Muhammad El-SABA

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At any temperature above 25°, the power is derated (reduced) linearly, until it reaches zero at around 150° C. Actually, the maximum power dissipation PD that a semiconductor device circuit can tolerate at a given ambient temperature TA is given by:

PD 

TJ  TA

 JA



TJ  TA  JC  CA

(3-44)

where Tj is the maximum allowed junction temperature (about 125 °C for Si and more for large gap semiconductors), JA is the thermal resistance between junction and ambient, JC is the thermal resistance between junction and case and CA is the thermal resistance between case and ambient. The thermal resistance is measured in °C/Watt. The following figure depicts the power dissipation derating of a semiconductor device versus case temperature (Tc).

Fig. 3-35. Power dissipation derating of a bipolar transistor versus temperature.

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Fig. 3-36. Mounting of a heat sink on a power BJT

Example 3-9. Design an NPN transistor that has a current gain  = 500 at VCB = 0. Assume NDE =1022cm-3 and WE = 0.1um for the emitter and take Dp = 2 cm2/s and Dn = 17cm2/s. The corresponding bandgap narrowing (BGN) in the emitter side is Eg = 89.3meV. Therefore, the effective intrinsic concentration in the emitter side is nie = 5.57 ni. Solution: The transistor design is an iteration process. We start here with a first order approximation. The assumptions that are made will have to be refined in the next iteration.

We will take small doping in the base so as to obtain this high value of gain. As a result BGN in base can be neglected. This gives NAWB=5.5x1011. We have several choices here for base doping and the resulting base thickness. Let us take NA=5.5x1016 and WB= 0.11um This is the effective base width. Let us calculate the metallurgical base width. For this we will have to calculate the depletion regions within the base due to emitter-base and collector-base junctions. For the emitter base junction we assume a forward bias of 0.7 volts and built-in voltage of 0.95 Volts. Most of the depletion region will lie in the base so that

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Similarly, the depletion width due to collector junction can be calculated:

The metallurgical base width will be The punchthrough voltage for such a lightly doped and narrow-base can be calculated using the expression

This is a very small voltage meaning that transistor can only be operated close to zero collector-base voltage. The early voltage is also very small. Thus a large current gain is obtained only at the expense of very small punch-through and Early voltages.

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3-15. BJT Fabrication Technology The first bipolar junction transistors were fabricated from a bar of germanium with two closely spaced alloyed contacts. This approach was soon abandoned and replaced by a double diffusion process, where the base and emitter region are formed by diffusion of impurities. A lowdoped collector region is epitaxially grown on the buried collector contact layer and isolation is done with a diffusion of opposite type. Figures 3-30 and 31 show a cross section of a diffused epitaxial bipolar transistor and its fabrication steps.

Fig. 3-37. Profile of a diffused epitaxial BJT.

Fig. 3-38. Fabrication steps of a diffused epitaxial BJT.

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The following figure 3-39 shows the main processes involved in integrated bipolar technology. Note the presence of buried epitaxial n+ region to reduce the collector resistance.

(i) Buried layer

(v) Emitter diffusion & Collector contact

(ii) Epitaxial layer

(vi) Contacts

(iii) Insulation regions

(vii) Metallization

(iv) Base diffusion

3-dimensional view of a npn transistor

Fig. 3-39. Sequence of major processes involved in monolithic bipolar technology.

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The BJT's described above were non-self-aligned structures, typical of transistors used in 1970's. Since then, so many improvements have been introduced in the BJT technology. For instance, the so-called poly-emitter and the self-aligned BJT technologies have resulted in faster BJT's, for high-speed digital and RF circuits. Through use of self-aligned techniques, both the extrinsic base resistance, as well as extrinsic base capacitance can be sharply reduced resulting in overall improvement in delay. The self-aligned structures are described below, as shown in figure 3-40.

Self-aligned BJT

Double-poly self-aligned BJT

Fig. 3-39. Structure of modern modern bipolar transistors.

The oxide spacer layer shown in the self-aligned structure is very narrow so that the base contact is very close to the intrinsic base region as compared to the non-self-aligned structure shown in the first Figure. The use of poly silicon facilitates formation of the spacer to isolate emitter and base contacts and also improves the current gain. Note that the base contact is formed on the P+Poly which makes the contact with the extrinsic base region.The following figure depicts the cross section of a modern RF-bipolar transistor.

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Fig. 3-40. Profile of an RF BJT.

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3-16. Other BJT Structures There exist several variant structures of the BJT, which provide additional degrees of freedom, and allow higher operation frequency and faster switching speeds. For instance, the heterojunction bipolar transistor (HBT) is an improvement of the BJT that can handle signals of very high frequencies up to hundreds GHz. 3-16.1. Unijunction Transistor (UJT) The basic structure of a uni-junction transistor (UJT) and its equivalent circuit are shown in figure 3-40. It is essentially a bar of N-type semiconductor material into which P-type material has been diffused somewhere along its length.

Fig. 3-40. Structure and equivalent circuit of a unijunction transistor (UJT). A simple bias circuit is also shown at the right-hand side.

Fig. 3-41. I-V characteristics of a UJT.

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As shown in figure 3-41, the UJT emitter current versus voltage characteristic have a peak of emitter voltage at a certain emitter current IP. Beyond the peak point, current increases as voltage decreases within a negative resistance region. The voltage reaches a minimum at the valley point and the saturation resistance RB1 is low at this valley point. For instance, IP and IV, for a 2n2647, are 2µA and 4mA, respectively. Also, VP is the voltage drop across RB1 plus a 0.7V diode forward drop. The valley voltage VV is about 10% of the bias VBB. The UJT was especially designed to trigger thyristors and this is where its main application lies. The following figures depict the application of a UJT as an R-C oscillator or as a trigger circuit for a thyristor. As we’ll see in a following Chapter, the thyristor is a power switching device, which can be controlled through its gate by timely-controlled pulses. It should be noted that the so-called Programmable UJT (PUT) is a four-layer structure, which belongs to the thyristor family, but its I-V characteristics are similar to those of the UJT.

Fig. 3-42. Application of a UJT as an oscillator.

Fig. 3-43. Application of a UJT to provide time delay for a thyristor

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Fig. 3-44. Comparison between the structure and symbols of the UJT and the PUT

3-16.2. Hetrojunction Bipolar Transistor (HBT) Heterojunction bipolar transistors (HBT) is an improvement of the bipolar junction transistor (BJT) that can handle signals of very high frequencies up to several hundred GHz. HBT’s are common in modern ultrafast and RF systems. HBT’s are composed of at least two different semiconductors. As a result, the energy bandgap as well as all other material properties can be different in the emitter, base and collector. This allows high doping to be used in the base, creating higher electron mobility while maintaining high gain. The analysis of the device starts with the calculation of the DC current gain. To this end we recall the equations for the electron and hole current in the base-emitter junction, namely: (3-45a)

(3-45b)

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where the intrinsic carrier density in the emitter, ni,E, and base, ni,B, are different (because of the different materials), is indicated explicitly by the additional subscripts.

Fig. 3-45. Cross Section of GaAs/GaInP HBT

The emitter efficiency of the transistor is still calculated from the electron current relative to total emitter current and equals: (3-46)

If we now assume that the effective density of states for electrons and holes are the same in the emitter and base, we find that the maximum current gain from the definition:



(3-47a)

such that the DC current gain  of an HBT is approximately given by or (3-47b) where Eg is the difference between the bandgap energy in the emitter and the bandgap energy in the base. The current gain depends exponentially on this difference in bandgap energy. 192 Prof. Dr. Muhammad El-SABA

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As a result one can obtain a very large current gain in a heterojunction bipolar transistor, even if the base doping density, NB, is larger that the emitter doping, NE. Therefore, the emitter of a heterojunction bipolar transistor has a wider bandgap than its base. This difference should be around 0.2V - 0.4V for optimum performance. A smaller value gives a small improvement. A larger difference causes the gain to be strongly temperature dependent, and creates a distinct spike in the energy diagram, which in turn limits the current. The advantages of HBTs are not restricted to its DC performance. The HBT devices can also be improved dramatically by using an appropriate heterojunction material system. In order to illustrate this point we now recall the equations for the transit frequency, fT, and the maximum oscillation frequency, fMAX

fT = 1/ (2 )

(3-48)

where the total transit time is given by the sum of emitter, base and collector transit times:

x VT WB2    E   B   C  Cbe   d , BC IE 2 DnB 2vsat

Fig. 3-46. I-V characteristics of an HBT

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(3-49)

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Also, the maximum operating frequency of the device is given by: f Max 

fT 2 .rbb ' .Cbc

(3-50)

Here rbb’ is the base spreading resistance and Cbc is parasitic transition capacitance at the B-C junction. Since a heterojunction transistor can have large current gain, even if the base doping density is higher than the emitter doping density, the base can be much thinner even for the same punch-through voltage. As a result one can reduce the base transit time without increasing the emitter charging time, while maintaining the same emitter current density. The transit frequency can be further improved by using materials with a higher mobility for the base layer and higher saturation velocity for the collector layer. An HBT can be further improved by grading the composition of the base layer such that the energy of the material is gradually reduced throughout the base. The grading causes an electric field, which in turn reduces the base transit time: (3-51a) with

(3-51b)

where Eg,MAX and Eg,MIN are the maximum and minimum energy bandgap at the edges of the base region (at x’ = 0, x’ = xB). A linear variation may be assumed in between. δ The improved transit time immediately increases fT. The higher base doping also provides a lower base resistance and a further improvement of fMAX. As in the case of a BJT, the collector doping can be adjusted to trade off a lower collector transit time for a lower base-collector capacitance. The fundamental restriction of heterojunction structures is the mismatch of lattice constants of different materials. 194 Prof. Dr. Muhammad El-SABA

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Fig. 3-47. The AC model of an HBT. Note the intrinsic model is shaded and the external packaging and stray parasitics are also indicated in the outside.

3-16.3. Resonant Tunneling Bipolar Transistor (RTBT) The resonant tunneling bipolar transistors (RTBT) have many advantages such as their high current handling capability and high current gain. The following figure depicts the structure of an InGaP/GaAs RTBT, with super lattice emitter. This device is usually grown by low-pressure metal organic chemical vapor deposition (LP-MOCVD) system on an N+-GaAs substrate. The vertical integration of RTBT and three terminal transistor structures reduces the signal delay and power dissipation. As compared to the AlGaAs/GaAs material system, the InGaP/GaAs system is more suitable for super-lattice applications since the normal InGaP/GaAs and inverted GaAs/InGaP interfaces are both smooth on the atomic scale. The following figure illustrates the typical I-V characteristics of the RTBT. Experimentally, the studied device exhibits excellent transistor characteristics including the high current gain, high breakdown voltage, low saturation voltage, and low offset voltage.

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Fig. 3-48. RTBT structure and circuit symbol.

Fig. 3-49. RTBT I-V characteristics.

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3-17. Laboratory Testing of a BJT As BJT’s are composed of two P-N junctions, their laboratory test involve the checking of both the base-emitter (BE) and collector-base (CB) junctions, in both sides, as shown in the following figure. We may use here the ohmmeter check, which should show a low resistance in the forward direction of each junction and a high resistance in the reverse direction. Meter readings should be opposite, of course, for an N-P-N transistor, with both P-N junctions connected the other way. You may distinguish the emitter, the base and the collector terminals, using conventional packaging arrangment, shown below in figure 3-50.

Fig. 3-50. Testing of a BJT, using a simple millimeter (Ohmmeter). The pinassignment of some famous BJT packages are shown below.

However, some multimeters are equipped with diode check, which can be used to check the forward drop of each diode. Better than this, some multimeters, have an “hfe” check, for testing bipolar transistors and 197 Prof. Dr. Muhammad El-SABA

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giving the current amplification factor (). If your meter has a designated diode check function, use that rather than the resistance range, and the meter will display the actual forward voltage of the P-N junction and not just whether or not it conducts current. You may also check the voltage gain of a simple BJT amplifier, using a multimeter, as shown in the following figure. Fortunately, some digital multimeters are equipped with oscilloscope screens, and can plot the voltage waveforms. You may check that the AC voltage gain of the shown amplifier is given by: Av = vout/vinput = - Rout/Rin, where Rout is the resistor in series with the collector (the speaker resistance, 8 ) and Rin is the resistor connected in series with the base (1k). Note that AC output voltage, vout, is equal to the AC collector-emitter voltage, vce.

Fig. 3-51. Testing of a BJT amplifier, using a millimeter, with oscilloscope.

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3-18. Computer Simulation & Modeling Parameters The PSPICE model of a BJT is depicted, together with its parameters, in Appendix B at the end of this Book. The BJT statement begins with a diode element name which must begin with “Q” plus optional characters. Example diode element names include: d1, d2, da, db. Two node numbers specify the connection of the anode and cathode, respectively, to other components. The node numbers are followed by a model name, referring to a subsequent “.model” statement. The model statement line begins with “.model,” followed by the model name matching one or more diode statements. Next, a “d” indicates a diode is being modeled. The remainder of the model statement is a list of optional diode parameters of the form ParameterName=ParameterValue. None are used in Example below. Example2 has some parameters defined. The detailed list of BJT parameters is shown in Appendix D. General form: Q < collector node> [substrate node] [area value] .MODEL NPN [model parameters] .MODEL PNP [model parameters] Example 3-7: Q1 1 2 3 mod1 .MODEL mod1 NPN Example 3-6: Q2 1 2 3 Qa2N222 .MODEL Qa2N222 PNP (BF=100 VJE=0.7V IS=1nA CJE=1pF)

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3-19. Summary In 1947 Bardeen and Brattain built the point contact transistor. They made it from strips of gold foil on a plastic triangle, pushed down into contact with slab of germanium. In 1948, Bells Lab unveiled the transistor. They decided to name it transistor instead of Point-contact solid state amplifier. John Pierce invented the name, combining transresistance. Later, Shockley made the Junction transistor (sandwich). This transistor was more practical and easier to fabricate. The bipolar junction transistor was the first solid-state amplifier element and started the solidstate electronics revolution. During the 1950’s, Sony received a license from Bell Labs to build transistors. They used these transistors to build battery-powered radio receivers. In United States they initially used the transistors primarily for computers and military uses. The following figures show the photographs of some early transistors

The following figures show one of the biasing schemes of the bipolar junction transistor (BJT) and how it can be used as an amplifier.

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The following figure depicts the internal current components of a BJT.

The following equations depict the BJT currents in all modes of operation:  v I C  I S exp  BE   VT

IB 

 v   exp  BC   VT

I S   vBE exp   F   VT

 v I R  I S exp  BE   VT

 I S     R

  vBC exp    VT

  I S   vBC   1  exp   R      VT

 v   exp  BC   VT

    1  

    1  

 I S   v BE   exp   F    VT

    1  

where F and R are the forward and reverse mode current gains. The above relations are based on the following assumptions when deriving ideal current-voltage characteristics of a BJT      

Low level injection Uniform doping in each region with abrupt junctions One-dimensional current flow Negligible bandgap narrowing in the emitter Negligible recombination-generation in space charge regions Negligible electric fields outside of space charge regions. 201

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For a given value of IB, the output characteristics curve of a BJT is the relationship between IC and VC E that is set by BJT internals. Figure3-8 depicts the output characteristics (IC versus VCE) at different values of the base current (IB).

The operating point (Q) is determined by the intersection of the load line with one of this family of curves. The limits of the saturation region are VBE > VBEsat, and IB = IBsat . Also, the cutoff region is limited by VBE < V and IB = 0.

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Like all electronic devices, the bipolar transistor can function only within well-defined limits of voltage and currents. Data sheets usually have a full set of charts, showing the various device parameters and limitations as a function of voltage, current and frequency. Without a thorough knowledge of the device limits, the device may cease to work and may even breakdown. In this section we discuss the physical limitations that should be taken into account, in order to ensure a reliable operation of the transistor. The basic limitations are grouped in the following categories: Current limitations (Fall of beta factor current gain and Kirk effect), Voltage limitations (Breakdown voltages, and Early effect), Power limitations (safe operating area and thermal derating). At high collector currents, the level of injected minority carriers in the base (electrons in NPN transistor) increases above the base concentration and cause the fall-off of the beta factor. The high injection levels also affects the I-V characteristics of the BJT as shown in the following figure.

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3-20. Problems 3-1) What are the majority current carriers in (a) the P-N-P transistor and (b) the N-P-N transistor? 1. (a) Holes (b) holes 2. (a) Holes (b) electrons 3. (a) Elements (b) holes 4. (a) Electrons (b) electrons 3-2) In a BJT, what percent of the total current flows through the emitter lead? 1. 100% 2. 98% 3. 60% 4. 5% 3-3) What term is used to indicate current gain in a common-emitter configuration, of a bipolar transistor? 1. Alpha 2. Beta 3. Gamma 4. X-ray 3-4) For normal operation of a bipolar transistor, what is the bias of the (a) emitter-base junction and (b) base-collector junction? 1. (a) Forward (b) reverse 2. (a) Forward (b) forward 3. (a) Reverse (b) forward 4. (a) Reverse (b) reverse 3-5) Consider an NPN transistor. The N-type emitter has a concentration NE and width WE, the base is P-type with concentration NB and width WB, and the collector with concentration NC and width WC. i) Express the density of holes in the emitter at equilibrium (pEo) and the density of electrons in the base at equilibrium (nBo) as functions of NE and NB ii) Using Boltzmann relation, show that potential barrier at the emitter base (E-B) junction is given by: VEB = VE – VB = (kBT/e) ln (NE.NB/ni2) iii) Calculate VEB if NE = 5.1019 cm-3, NB = 1018 cm-3, ni = 1.45.1010 cm-3 204 Prof. Dr. Muhammad El-SABA

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iv) If we applied a forward bias VBE > 0, the carrier concentration will change in base and emitter. Show that the carrier concentrations at the edges of emitter and base will become: pE(0) = pEo exp(eVBE/kBT), and nB(0) = nBo exp(eVBE/kBT) v) Apply the definition of diffusion current and hence derive an expression for the current of electrons in base (JnB) and the current of holes in emitter (JpE). vi) As a first order approximation, assume the definition of the current gain = (JnB / JpE), and hence prove that:  = (NE WE/NB WB).(DnB/DpE) vii) Calculate  if: WE = 0.8m, DpE =1.3 cm2/s, WB =0.8 m, DnB =15 cm2/s viii) Using the above BJT structure, show that in forward active mode we have: IC = IS exp (eVBE/kBT) with IS = e AE (DnB ni2 / NB WB ) ix) Calculate IS if NB = 1018 cm-3, ni = 1.45 1010 cm-3, DnB = 15 cm2/s, AE = 100m2.

3-6) Consider the current mirror circuit shown in figure below (right), which has two identical BJT’s. i) Prove that IC2 is given by: IC =  I / (+2) ii) If  is given by the value you obtained in problem 3-5, calculate R such that I = 1 mA. 205 Prof. Dr. Muhammad El-SABA

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3-7) In integrated circuits, it is not desirable to have large resistors, because they occupy a large area on the chip. In order to reduce the value of the resistance R, in the above current mirror circuit of problem 3-6, the circuit is slightly modified as shown above (right). This circuit is called the Widlar current mirror. i) ii) iii)

Neglecting IB1 and IB2, express VBE1 and VBE2 in terms of I and IC2 Prove that RE is given by : RE = (kBT/eIC2) ln (I/IC2) Calculte RE such that I = 1 mA and IC2= 1A.

3-8) What method for checking transistors is cumbersome when more than one transistor is bad in a circuit? 1. Ohmmeter 2. Transistor checker 3. Voltage check 4. Substitution 3-9) Calculae the DC quiescent point (IB, IC and VCE) of the following common collector (Emitter follower) amplifier. Consider  = 100. Derive an expression for the AC voltage gain Av = Vout/Vin, when C1 and C2 are very large (short circuit).

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3-10) Write down a SPICE program to simulate the following common collector amplifier (Emitter follower) and check the input/output waveforms at the indicated points. Check that the voltage gain is almost unity.

3-11) Laboratory Assignment In this practical assignment, you will characterize the current-voltage characteristics of an npn BJT. To do this, you can use the MIT Microelectronics WebLab at http://ilab.mit.edu/. The BJT is labeled npn BJT (2N3904). This exercise involves three phases: (i) characterization of the devices, large and small signal parameter extraction, (ii) using the measurements to choose bias voltages for a common collector amplifier to meet amplifier specifications, and (iii) using the measurements to determine small signal parameters (h-parameters or pi-parameters) at the bias point. 207 Prof. Dr. Muhammad El-SABA

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3-21. Chapter Assessment Photocopy the following two pages, read the assessments carefully and answer on the page. Carry out the required measurements, and comment if there exist a discrepancy between the measured and calculated values. Don't forget to write your name and ID. Assessment #3-1.

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3-22. References [1] William. Shockley, Electrons and Holes, Van Nostrand, Princeton, N.J, 1950. [2] J. J. Ebers and J. L. Moll. “Large Signal Behavior of Junction Transistors,” Proceedings I.R.E. vol. 42, p. 1761, 1954. [3] Walter H. Brattain, "Genesis of the Transistor." The Physics Teacher, pp. 109-114, March, 1968. [4] H. K. Gummel and H. C. Poon. “An Integral Charge-Control Relation for Bipolar Transistors,” Bell Syst. Technical Journal. vol. 49, p. 115, 1970. [5] William Shockley, “How we Built the Transistor", New Scientist, December 1972. [6] S. Millman, Editor, The Early History of the Transistor. "A History of Engineering and Science in the Bell System", Physical Sciences,19251980. [7] S. M. Sze, Semiconductor Devices: Physics and Technology, John Wiley Inc., 1st Edition, 1985. [8] P. Antognetti, and G. Massobrio Semiconductor Device Modeling with SPICE, 2nd ed., McGraw Hill, NY, 3rd ED, 1993. [9] C. McAndrew, AT&T/Motorola; J. Seitchik, Texas Instruments; D. Bowers, Analog Devices; M. Dunn, Hewlett Packard; M. Foisy, Motorola; I. Getreu, Analogy; M. McSwain, MetaSoftware; S. Moinian, AT&T Bell Laboratories; J. Parker, National Semiconductor; P. van Wijnen, Intel/Philips; L. Wagner, IBM, VBIC95: An Improved Vertical, IC Bipolar Transistor Model. [10] D. Neamen, A. Irvin, Semiconductor Physics & Devices, Chicago, 1997 [11] S. M. Sze, Semiconductor Devices. Physics and Technology. John Wiley Inc., 2d edition, 2002. [11] Jongchan Kang, Youngoo Yang, Sungwoo Kim, and Bumman Kim, “A Heterojunction Bipolar Transistor Large-signal Model Focused on the Saturation Region,” 32nd European Microwave Conference Digest, vol. 3, pp. 147-150, Sep., 2002. [12] A. P. Sutton, Electronic Structure of Materials, Clarendon Press, Oxford, 2004.

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Metal-Semiconductor (M-S) Contacts Contents 4-1. 4-2.

Chapter Overview and Learning Objectives Introduction to M-S Junction 4-2.1. Workfunction of a Metal 4-2.2. Thermo-ionic Emission Current of a Metal (Richardson’s Law) 4-2.3. Electron Affinity in a Semiconductor

4-3.

Metal-n-type Semiconductor Contact

4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 4-10. 4-11. 4-12. 4-13. 4-14. 4-15.

Metal-p-type Semiconductor Contact Ohmic MS Contact Tunnel MS Contact Annealed & Alloyed (Silicide) Contacts Small Signal Model of the Schottky Barrier Diode Capacitance of MS Structure Measurement of MS Contact Barrier Height Switching Performance of the SBD MS Contact Applications Summary Problems References

4-3.1. Case 1: m > s (Schottky Barrier contact) 4-3.2. Case 2: m < s (Ohmic Barrier)

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Metal-Semiconductor (M-S) Contacts 4-1. Chapter Overview and Learning Objectives Metal-semiconductor contacts are obvious components of any semiconductor device or integrated circuit. In this chapter, we summarize the fundamental concepts about Metal-Semiconductor (M-S) contacts and their basic characteristics. We show how to employ such junctions to implement Shottkey barrier diodes (SBD) and Ohmic contacts, in electronic devices and integrated circuits. Upon Completion of this Chapter, the student should: 1. Be acquainted with the principle types of M-S contacts. 2. Understaand the physical operation of SBD’s 3. Identify the I-V characteristics of the Schottky barrier diodes and their advantages in power and RF applications 4. Be aware of the switching performance of SBD’s 5. Understand the conditions necessary for making Ohmic contacts.

4-2. Introduction to M-S Junctions The M-S contacts cannot be assumed to have as low resistance as that of two connected metals. In fact, a large mismatch between the Fermi energy of the metal and semiconductor may result in a high-resistance or rectifying contact. A proper choice of materials can provide a low resistance Ohmic contact. However for a lot of semiconductors there is no appropriate metal available. Instead, one can create a tunnel contact. Such contact consists of a thin barrier – obtained by heavily-doping the semiconductor – through which carriers can readily tunnel. Contact formation is also affected by thin interfacial layers and is typically finished off with a final anneal or alloy formation after the initial deposition of the metal. In the following section we review some important definitions concerning metals and semi-conductors. We then describe the different types of M-S contacts.

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4-2.1. Workfunction of a Metal The workfunction of a metal is defined as the work exerted to liberate an electron from that metal. The following figure illustrates the definition of the metal workfunction (em), as the energy difference between Fermi energy level of electrons (EFm) inside the semiconductor and the vacuum (free electron) energy level (Eo).

em =

Eo -

EFm

(4-1)

Fig. 4-1. Illustration of the metal workfunction definition.

The following table shows the workfunctions of some metals of interest. Table. 4-1. Workfunctions of some metals of interest

Low workfunction Metals High workfunction Metals Na K Fe Al Au Cu Workfunction (eV) 2.3 2.2 1.8 4.3 4.8 4.4 Metal

4-2.2. Thermionic Emission Current of a Metal (Richardson Law) If a sufficient voltage is applied across a metal filament, then electrons are heated up and can emit from the surface of metal. Eventually, these electrons may be attracted and collected by a positive anode. The intensity of such thermo-ionic current may be calculated as follows. Assuming the electrons obey the quasi-free electron model inside a metal, then the thermo-ionic current in a given direction (say the x-direction) is given by:

Jnx = -e  vgx(knx) f(knx) g(knx) dknx The total 3-dimensional current is therefore 214 Prof. Dr. Muhammad El-SABA

(4-2a)

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Chapter 4

Jn = -e    vg(kn) f(kn) g(kn) dkn dkn dkn

(4-2b)

where vg(kn) is the group velocity of electrons and g(kn) is the density of electron states in the k-space

g(kn) = 2/(2)3 , as

g(knx) = g(kny) = g(knz) = 2/(2) (4-2c)

Also, f(kn) is the electron distribution function in the k-space (assumed as Fermi-Dirac distribution)

f(kn) = (2mn kBT/ħ2) .exp [- ( E - EF )/kBT]

(4-2d)

where En is the electron energy, which is eventually related to the wave vector kn by the parabolic relation:

En = (ħkn)2 / 2mn = (ħ2 /2mn).( knx2+ kny2 + knz2)

(4-3a)

The group velocity is related to the wave vector by the relation:

vgn(kn) = ∂En / ∂kn = ħ2kn /mn

(4-3b)

Also, we have following condition, for electron emission

En = ħ2kn2 /2mn = ½ mn vgn2 > EFm + em

(4-3c)

Such that the electrons are emitted with a minimum velocity, which is given by:

vgn (min) = √ 2 (EFm + em)/mn

(4-4)

Substituting all the above relations and integrating, yields:

Jn = - R T2 exp [- (em/ kBT)]

(4-5a)

where the constant R is called the Richardson constant

R = 4  (e mo kB2/h3) = 1.6 106 [A / cm2 K2]

215 Prof. Dr. Muhammad El-SABA

(4-5b)

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Chapter 4

4-2.3. Electron Affinity of a Semiconductor It is well known that non-degenerate semiconductors and isolators have no free electrons (under the Fermi level), like metals. The work exerted to liberate an electron in the bottom of conduction band of a semiconductor is called the electron affinity (es):

es =

(4-6a)

EO - EC

Fig. 4-2. Illustration of the electron affinity definition.

A workfunction of a semiconductor can be also defined as follows:

e s =

Eo -

(4-6b)

EF

Table. 4-2. Electron affinity of some semiconductors of interest

Semiconductor Affinity (eV)

Si 4.01

Gi 4.13

GaAs 4.07

InP 4.38

4-3. Metal-n-type Semiconductor Contact We have pointed out so far that the Fermi level of any two solids in contact must be equal in thermal equilibrium. As a result, whenever a metal and a semiconductor are in contact, there exists a potential barrier between the two materials that prevents most charge carriers (electrons or holes) from passing from one material to another. Only a small number of carriers will have enough energy to get over the barrier and cross to the other material. When a bias is applied across the MS junction, it may have one of two cases: it may make the barrier appear lower from the semiconductor side, or it may make it appear higher. In order illustrate the different cases of an MS contact, assume a metal of workfunction m is brought into contact with an n-type semiconductor with electron affinity s and workfunction s. 216 Prof. Dr. Muhammad El-SABA

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Chapter 4

4-3.1. Case1: n-type Semiconductor with m> s (Schottky barrier diode) In the first case we assume that m > s. The following figure depicts energy band diagram of the two materials before and after contact. In this case, the MS junction forms a positive barrier (ms = m - s > 0), called Schottky (or Mott) barrier. The barrier height across the metalsemiconductor junction at thermal equilibrium is

eBo= em - es= e(m -s ) + (Ec–EF) = eVbi +(Ec–EF) (4-7a) where Vbi=m-s=ms is called metal-semiconductor built-in voltage. Also the emref (EC-EF) is related to the doping concentration as follows:

(EC –EF) = kBT ln(NC /Nd )

(4-7b)

When a bias Va is applied across the MS contact, this barrier is lowered or raised, according to the polarity of the bias. Actually, the barrier height is further modified because of the eventual flow of electrons and image forces, as shown in figure 4-3. Therefore, the effective barrier height is:

B = Bo - B ,

(4-7c)

Note 4-1. Barrier Lowering, and Image Forces The MS barrier is reduced under applied bias due to the image force of the carrier, as illustrated in figure 4-3. The image force results from the electrostatic attraction of the carrier at a distance x from the electrode–semiconductor interface leading to a charge build-up at the electrode interface that gives the same potential as an equal and opposite charge a distance −x from the electrode, the image charge. The attractive image force is then given by the following expression:

The resulting potential energy is

The the Schottky barrier lowering, e φB is given by the condition dU/dx = 0, such that:

The value of ε is12ε0 in Si and 13ε0 in GaAs, increasing the importance of the barrier-lowering term. This contribution must be included for any device model to be successful

217

Prof. Dr. Muhammad El-SABA

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Fig. 4-3. Energy band diagram for the interface between a metal and semiconductor. The effective barrier is lowered when an electric field is applied to the surface. The lowering is due to the combined effects of the field and image force.

The barrier lowering B, in the case of a metal-semiconductor (n-type) contact, is given by:

B = [ (e3Nd/83).(Vbi - Va )] 1/4

(4-7d)

The above relation may be obtained by integrating the Poisson equation, around the MS contact, taking into account the electrostatic image force of electrons. Figure 4-4 depicts the energy band diagram of a metal-semiconductor contact at thermal equilibrium and with applied forward bias. Usually, the Schottky barrier is a large barrier height (ms = m - s >> 0) and low doping concentration. When a forward bias is applied across this barrier, such that the metal is positive and the semiconductor is negative, the energy barrier is lowered by the amount of applied bias and current passes, as shown in Fig. 4-4(c). There exist 4 possible conduction mechanisms across such a barrier: 1- Thermoionic emission (TE), over the barrier 2- Tunneling through the barrier either by field emission (FE) or by thermoionic field emission (TFE) 3- Minority carrier injection in the quasi neutral region 4- Recombination in the depletion region. 218 Prof. Dr. Muhammad El-SABA

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Fig. 4-4(a). Energy band diagram of a metal-semiconductor (n-type) contact, with m > s. at thermal equilibrium

Fig. 4-4(b). Energy band diagram of a metal-semiconductor (n-type) contact, with m > s. with applied bias (Va).

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Fig. 4-4(c). Illustration of the barrier height lowering effect

However, the current transport across ordinary (thick) Schottky barriers, is mainly due to majority carriers, by thermo-ionic emission. The number of emitted majority carriers (electrons in n-type semiconductors) over the barrier (Vbi-Va) may be given by the Maxwellian distribution:

nth = no exp [-e(Vbi - Va) / kBT),

(4-8a)

where the no is the number of majority carriers (electrons) near thermal equilibrium.

no = NC exp [-e(C – EF) / kBT]

(4-8b)

Here NC is the effective density of states in the conduction band of the ntype semiconductor. The thermo-ionic emission current may be then expressed using the kinetic theory of gases :

| JmS | = e vn nth = ¼ e nth = C1 nth

(4-8c)

where vn = ¼ is the average velocity of emitted electrons, vth is the thermal velocity of electrons and C1 = ¼ e. Therefore, we can write:

| JmS | = | JmS |V=0 = C1 nth = C1 NC exp (-e B / kBT) (4-9a) and

|JSm | = C1 NC exp [- e (B – Va) / kBT ] 220 Prof. Dr. Muhammad El-SABA

(4-9b)

Microelectronic & Nanoelectronic Devices

Chapter 4

The total thermoionic current across a Schottky barrier junction is then given by the sum:

J = JSm - JmS

= Js [ exp (- e Va / kBT) -1 ]

(4-9c)

Here, Js = C1 NC exp (-e B / kBT), is the reverse saturation current, which may be put in the following form

Js = R* T2 exp (- eB / kBT)

(4-9d)

where R* = R (mn*/mo) is the effective Richardson constant. For n-type Si, we have R*= 250 [A/cm2K2] and for n-type GaAs we have R*= 8.1 [A/cm2K2]. In contrary, when a reverse bias is applied across such a contact, the energy barrier height increases, and a small leakage current due to emission of metal electrons (Js) passes in the reverse direction. As Js is very small compared to J, this type of MS contact is a rectifying contact, and called Schottky Barrier Diode (SBD). The diffusion of minority carriers and recombination current across the SBD, can be derived on the basis of semiconductor current equations. Alternatively, the I-V characteristics of the SBD can be derived starting from the so-called “diffusion theory”. According to the diffusion theory, the current across an n-type Schottky diode is given by:

J = Js’ [ exp (- e Va / kBT) -1 ]

(4-10a)

with

Js‘= (e2DnNC/Vt).[2e(Vbi – Va).Nd /s]½ .exp (-eB / kBT) (4-10b) Generally speaking, the practical I-V characteristics of the SBD (shown in figure 4-4) can be expressed as follows:

J = Js [ exp ( - Va /  Vt) - 1 ]

(4-11)

Where  is called the ideality factor. For, Al-Si (n-type) Schottky barrier diodes, we have  = 1.066. The practical structure of Si and GaAs SBD’s are shown in Fig. 4-5. 221 Prof. Dr. Muhammad El-SABA

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Fig. 4-5 I-V characteristics of Al-Si Schottky-barrier diode (SBD).

Fig. 4-6 Structure of Si , GaAs and SiC Shottkey barrier diodes (SBD).

222 Prof. Dr. Muhammad El-SABA

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Chapter 4

4-3.2. Case 2: n-type Semiconductor with m < s. When a metal and an n-type semiconductor are joined and Φm < ΦS, electrons will flow from the Fermi energy level in the metal into the semiconductor conduction band to lower their energy. This will cause the chemical potential of the semiconductor to move up into equilibrium with that of the metal. It will also deform the semiconductor bands, so that they curve upwards away from the metal. This situation is depicted in the animation below. Use the tabs to navigate through the animation. This type of contact yields a linear relationship between the voltage applied and the current that flows across the junction. It is therefore called an Ohmic contact, because it obeys Ohm's law. This type of contact is also described as metallization, and is used to supply electric current into semiconductor devices.

Fig. 4-7. Energy band diagram of a metal-semiconductor (n-type) contact, with m < s.

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Chapter 4

4-4. Metal-p-type Semiconductor Contact When a metal and an p-type semiconductor are joined and m < s, electrons will flow from the conduction band of the semiconductor into the metal conduction band to lower their energy. This will cause the chemical potential of the semiconductor to move down with that of the metal. It will also deform the semiconductor bands, so that they curve downwards to the metal. This situation is depicted in the Fig. 4-8. Table 4-3, summarizes all the types of MS contacts.

Fig. 4-8. Energy band diagram of a metal-semiconductor (p-type) contact, with m < s.

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Chapter 4

Table 4-3. Types of a metal-semiconductor contacts.

4-5. Ohmic Contacts A metal-semiconductor junction results in an Ohmic contact if the energy barrier at the junction has zero or negative height (ms ≤ 0). In such case, the carriers are free to flow in or out of the semiconductor so that there is a minimal resistance across the contact. For an n-type semiconductor, this means that the workfunction of the metal must be close to or smaller than the electron affinity of the semiconductor. For a p-type semiconductor, it requires that the workfunction of the metal must be close to or larger than the sum of the electron affinity and the bandgap energy. Since the workfunction of most metals is less than 5V and a typical electron affinity is about 4V, it can be problematic to find a metal that provides an Ohmic contact to wide bandgap semiconductors such as GaN or SiC.

Fig. 4-9. Current-voltage characteristics of MS contacts.

225 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 4

4-6. Tunnel MS Contacts An alternate and more practical contact is a tunnel contact. Such contacts do have a positive barrier (ms > 0) at the metal-semiconductor interface, but also have a high enough doping in the semiconductor that there is only a thin potential barrier separating the metal from the semiconductor. If the width of the depletion region at the metal-semiconductor interface is very thin, on the order of 3nm or less, carriers can readily tunnel across such thin barrier. The required doping density for such contact greater than 1019 cm-3.

Fig. 4-10. Tunneling across a thin Schottky barrier of MS contact.

When tunneling is dominant, the MS contact is almost Ohmic. The tunneling currents can be calculated using the WKB approximation or the Fowler–Nordheim formula. In the latter case, the electron tunneling current density is given by:

(4-12) 226 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 4

with a similar expression for the hole tunneling current density Jptun. In this case, the following relation gives the contact resistance:

 V  Rc      J V 0

 2 B exp    

m*  s ND

   

(4-12)

where B is the M-S barrier height, Nd is the semiconductor doping concentration and other symbols have their usual meaning. Figure 4-11 depicts the contact specific resistance Rc of various metals on n-type and p-type silicon as a function of the doping concentration.

Fig. 4-11. Contact specific resistance of some metals on n-type and p-type Si versus doping concentration. Solid lines are calculated from the model of Swirhun.

227 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 4

For Al-Si contact we have eB =0.7eV for n-type Si and eB =0.6 eV for p-type Si. Therefore, aluminum can also make Ohmic contact with heavily doped n-type Si. In this case the MS current is dominated by the tunneling current component and the Ohmic resistance Rc becomes so small as given by:  4.4 x10 10B Rc  10 -5 exp  ND 

  

 cm 2

(4-13)

Table 4-4. Some Silicides and the barrier height of their silicon contact

Silicide eB (eV)

PtSi 0.89

PdSi 0.74

Ni Si 0.66

TiSi2 0.6

TaSi2 0.59

4-7. Annealed and Alloyed Contacts (Silicides) The fabrication of Ohmic contacts frequently includes a high temperature step so that the deposited metals can either alloy with the semiconductor or the high-temperature anneal reduces the unintentional barrier at the interface. In the case of silicon, one can simply deposit a metal such as aluminum or any other metal and obtain a reasonable Ohmic contact. However a subsequent anneal of Si/Al at 475°C in a reducing ambient such as (20:1 N2/H2) will further improve the contact resistivity. The temperature is chosen below the eutectic temperature of the Si/metal eutectic composition. Such silicon-metal alloys are called Silicides, and their contact with silicon have a small barrier height (B), as shown in the following table. Annealing at higher temperature causes the formation of Si/Al alloys, which may cause pits in the silicon. This effect is referred to as spiking and when penetrating through an underlying P-N junction would dramatically affect the quality of the junction as can be observed in the high leakage current or reduced breakdown voltage. Contacts to compound semiconductors require some more attention. Selecting a material with the right workfunction might still not result in the expected Ohmic contact. This is due to pinning (bending) of the Fermi energy at the interface due to surface states. In order to further improve MS tunnel contacts one adds dopants such as Ge in the case of an n-type contact and Sn in the case of a p-type contact to the metal. An anneal around 400°C for about tens minutes causes the dopants to alloy with the semiconductor, thereby forming a thin high-doped region as desired for a tunnel contact. 228 Prof. Dr. Muhammad El-SABA

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Recently, the copper have been used in semiconductor technology to form interconnects between devices, as shown in figure 4-12. Copper offers higher performance than aluminum because of its lower resistivity (1.67 Cm). Copper layers can also be made thinner and hence reduce interconnects delay. Copper contacts can be applied by electroplating or via the so-called Damascene process, as shown in Fig. 4-13.

Fig. 4-12. Damascene process main steps

229 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Fig. 4-13. Photograph of copper contacts.

230 Prof. Dr. Muhammad El-SABA

Chapter 4

Microelectronic & Nanoelectronic Devices

Chapter 4

4-8. Small Signal Model of the Schottky Barrier Diode The Schottky barrier diode (SBD) is a majority carrier device. Unlike a pn diode, in forward bias no minority carrier injection occurs. Thus there is no diffusion capacitance and the device response can be very fast. The following figure depicts the small signal equivalent model of the SBD, in series with a resistor and inductor. The depletion capacitance (Cd) of the SBD is given by: (4-14a)

And the diode resistance Rd is given by: (4-14b)

Fig. 4-12. Equivalent circuit of a Schottky barrier diode, including series resistor and inductor as well as parallel packaging capacitance.

4-9. Capacitance of MS Contacts The Schottky barrier diode capacitance can be calculated, at a certain applied bias as follows. We start by solving the Poisson equation, to determine the potential and field distribution, at a certain applied bias voltage. Then, from the definition of capacitance (C = dQ/dV) we can calculate the MS contact capacitance. The charge density in the semiconductor side (s) is assumed homogenous, and extended over a limited depletion region width of W, such that s = e.Nd W. By integrating the Poisson equation:

2 V = - ζ = s / we get the electric potential: 231 Prof. Dr. Muhammad El-SABA

(4-13a)

Microelectronic & Nanoelectronic Devices

Chapter 4

V(x) =(Va–Vbi)+ (eNd/).(W-x)=(Va–Vbi)- xζm(eNd/2)x2 (4-13b) and electric field

ζ(x) = (eNd/). (W - x) = ζm - (eNd/).x

(4-13c)

where the constants of integration V(0) = Va – Vbi and the maximum electric field ζ(0) = ζm = (eNd/).W.

Fig. 4-13. Charge density, electric field and potential across a Schottky barrier contact.

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The applied bias (Va) is related to the depletion region width by the following relation:

Vbi – Va = ½ ζm W = ½ (eNd/).W2

(4-14)

The total charge inside the depletion region, is then given by: Qs = eNdW = eNd [2 (Vbi –Va)/ eNd]½ = [2eNd(Vbi – Va)]½

(4-15)

If we take the mobile charges (n) into account, the above relation becomes: Qs = [2eNd(Vbi – Vt - Va)]½

(4-15)

where Vt = kBT/e is the thermal voltage. Therefore, C = | ∂Qs / ∂Va | = [ eNd(Vbi – Vt – Va)] = ( /W) ½

(4-16)

Or in a more convenient form:

1/C2 = (Vbi – Vt – Va ) / e Nd

(4-17)

4-10. Measurement of the Barrier Height of MS Contacts The barrier height (B) and background doping concentration (Nd), of a metal-semiconductor contact can be determined from the C(V) characteristics, as shown in Fig. 4-14. For instance, referring to the this figure, we have: slope = d(1/C2) dVa = - 2 / e Nd

(4-18a)

Intercept = (Vbi – Vt ) / e Nd

(4-18b)

IF the slope = - 4.4 x 1015 (cm2/F)2/V], then the doping concentration is given by:

Nd = - 2 / e [ d(1/C2) dVa] = - 2 / (e slope) = 2.7 x1015 cm-3 From the intercept, we have Vbi = 0.24 V. Therefore, one can determine barrier height as follows. 233 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 4

The barrier height lowering can be first calculated from equation (4-7d). However, this equation should be also modified, if we take the density mobile carriers (n) in the MS depletion region, into account:

B = [ (e3Nd/8o3).(Vbi - Vt - Va )]1/4

(4-19)

Thus, at Va = 0, the barrier height lowering is given by:

B = [( e2 Nd / 82 3)(Vbi - Vt )]¼ = 0.017 V Also, the emref of the Fermi level (EC - EF)/e = Vt ln (Nd/NC) = 0.24 V. Then the total barrier height is given by:

B = Bo - B =ms + Vt ln (Nd/NC) - B = 0.42+0.24-0.0173= 0.66V.

Fig. 4-14. Capacitance of a Schottky barrier contact versus applied bias.

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The following figure shows the measured barrier height of some metals with n-type Si and GaAs contacts.

Fig. 4-15. Measured barrier height of a metal Si and metal GaAs (n-type) contacts.

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4-11. Switching Performance of the SBD The transient response of the SBD is better than that of the usual P-N junction diodes. This is because the SBD is a majority carrier device, which has no minority carrier storage. Therefore, the carrier storage time (ts) of the SBD is zero, as shown in figure 4-16.

Fig. 4-16. Switching characteristics of a Schottky barrier diode.

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4-12. Applications of MS Contacts In conclusion, of all the above discussion, it is interesting to summarize, what MS contacts are good for? The important applications of MS contacts include, but not restricted to: Ohmic contacts, which are essential components of any electronic device to carry current into and out of the semiconductor device. Determining of doping profiles, through the measurement of the MS contact capacitance versus applied bias C(V). Shunt diodes, to reduce switching transients in bipolar transistor logic Microwave diodes, which is taking advantage of the negligible minority carrier injection. Switching speed is much higher than N-N junctions The gate of MESFETs, which are a sort field effect devices. Ultraviolet detectors.

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4 –13. Summary We have pointed out so far that the Fermi level of any two solids in contact must be equal in thermal equilibrium. As a result, wwhenever a metal and a semiconductor are in contact, there exists a potential barrier between the two materials that prevents most charge carriers (electrons or holes) from passing from one material to another. Only a small number of carriers will have enough energy to get over the barrier and cross to the other material. When a bias is applied across the MS junction, it may have one of two cases: it may make the barrier appear lower from the semiconductor side, or it may make it appear higher. The result of this is a Schottky (rectifying) Barrier contact, where the junction conducts in one direction, but not the other. Almost all metal-semiconductor junctions will exhibit some of this rectifying behavior. The following figure depicts the energy band diagram of metal-semiconductors at equilibrium.

Schottky Contacts make good diodes, and can even be used to make a kind of transistor, but for getting signals into and out of a semiconductor device, we generally want a contact that is Ohmic. Ohmic contacts conduct the same for both polarities. The following figure shows a photograph of some of the early metal-semiconductor (CuO) rectifiers, which are usually called Schottky barrier diodes (SBD)

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There are two ways to make a metal-semiconductor contact look ohmic enough to get signals into and out of a semiconductor (or doing the opposite makes a good Schottky contact).  Lower the barrier height: The barrier height is a property of the materials we use. We try to use materials whose barrier height is small. Annealing can create an alloy between the semiconductor and the metal at the junction, which can also lower the barrier height.  Make the barrier very narrow: The probability of tunneling becomes high for extremely thin barriers (in the tens of nanometers). We make the barrier very narrow by doping it very heavily (> 1019 atoms/cm3). 239 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 4

Comparison between Schottky barrier diode and conventional PN junction diodes:

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4–14. Problems

4-1) Using the work functions listed in the summary, predict which metal-semiconductor junctions are expected to be Ohmic contacts. Use the ideal interface model. 4-2) Find the barrier height, built-in voltage, maximum field, and the depletion layer width at equilibrium for W-Si (n-type) contact. Given: m = 4.55eV for W; (Si) = 4.01eV; Si doping = 1016 cm3. Draw the band diagram at equilibrium. 4-3) What is the basic structure of a Schottky diode? What are its most important parasitics? 4-4) How do Schottky diodes switch? What sets their time response? 4-5) What does one have to do for a metal-semiconductor junction to become an ohmic contact? 4-6) Draw the energy band diagram and determine the contact potential for the following metal/semiconductor systems using the ideal Schottky diode theory.

Of these which will have rectifying and which will have ohmic characteristics. 4-7) Determine the work-function of a metal, which when deposited on an N-type semiconductor with

would form a contact with zero contact potential. 4-8) Draw the qualitative energy band diagram of the Schottky barrier for the following system:

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4-9) Determine the magnitude of doping required such that the voltage drop in the lightly doped N-region is 0.6 Volts. Assume that Schottky barrier height is 0.7 Volts

4-10) Determine the Schottky barrier height required so that the turn-on voltage of the diode is 0.45 Volts for a forward current of 1 A. Assume that the Richardson’s constant is and the area of the diode is 4-11) Schottky barrier diodes are commonly used as gates in field effect transistors (FETs). The gate leakage current under reverse bias conditions is an important consideration in these FETs. For a gate dimension of , determine the minimum barrier height required to obtain a leakage current < 10pA. Assume that Richardson’s constant is . 4-12) Calculate the reverse leakage current of a Schottky diode for reverse voltages of –1, -5, -25, -50Volts with and without taking Schottky barrier lowering into account. Assume that the Richardson’s constant is and the area of the diode is 4-13) Schottky barrier diodes are frequently used as a Photodetector. Suppose an electron-hole pair is generated within the depletion region of the diode as a result of absorption of a photon. 242 Prof. Dr. Muhammad El-SABA

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(a) Indicate the direction of flow of the photo-generated carriers. (b) What will be the direction of current flow? (c) In which mode, forward bias or reverse bias should the diode be operated to obtain maximum sensitivity. 4-14) Explain what will happen if the photon is absorbed outside the depletion region. Hint: Consider diffusion and recombination of photogenerated minority carriers. 4-15) The depletion capacitance measured for a Schottky barrier diode with area = at different reverse bias voltages is given below: Capacitance (F/cm2) 3.43 2.2 2.65

Bias (V) 0 -1 -2

(a) Determine the doping of N region (b) Determine the barrier height (c) Determine the depletion width at zero bias 4-16) Obtain the small signal model for a Schottky diode on Silicon biased at a current of 1mA. Assume that the Richardson’s constant is:

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4-15. References: [1] S. M. Sze, Semiconductor Devices. Physics and Technology. J. Wiley Inc. 2002, 2d edition. [2] S. M. Sze, Semiconductor Devices. Physics and Technology. J. Wiley Inc. 1985, 1st edition. [3] A. P. Strutton, Electronic Structure of Materials, Clarendon Press, Oxford, 2004.

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Junction Field Effect Transistor (JFET) Contents: 5-1. 5-2. 5-3. 5-4. 5-5. 5-6.

Chapter Overview and Learning Objectives JFET Structure JFET Operation & I-V Characteristics JFET Small Signal Model JFET Amplifiers Other FET Structures 5-6.1. MESFET 5-6.2. MODFET (HEMT) 5-7. FET Noise Model 5-8. FET Testing 5-9. Summary 5-10. Problems 5-11. Assessment 5-12. References

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Chapter 5

Junction Field Effect Transistor (JFET) 5-1. Chapter Overview and Learning Objectives The field effect transistor (FET) is a three terminal device which is capable of both amplification and switching. Field effect transistors include the Junction FET (JFET), Metal-Semiconductor FET (MESFET) and Metal-Oxide-Semiconductor FET (MOSFET). All field effect transistors are majority carrier devices. This means that current is conducted by the majority carriers of these devices. The JFET and MESFET are depletion mode devices whereas the MOSFET can operate in depletion mode or in enhancement mode. Depletion mode devices are controlled by depleting the charge carriers in their conduction channels. In this chapter, we present the fundamental concepts about JFETs and their basic circuits. We briefly demonstrate how to use such electronic devices to amplify and switch signals in different configurations. Upon Completion of this Chapter, the student should: Understand the principle function of Field effect transistors. Be acquitted with the circuit configurations and biasing methods of the JFET, Identify the different current components and the current amplification factor of the JFET Identify the input and output I-V characteristics of the JFET Be acquainted with the JFET circuit models Apply the appropriate circuit models correctly. Identify the JFET quirks and physical limitations Know other forms of field effect transistor, such as high electron mobility transistor (HEMT), and how they operate.

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5-2. JFET Structure Like all field-effect devices, the JFET has two basic types, namely: nchannel and p-channel JFET. For an n-channel FET, the device is constructed from a bar of n-type semiconductor, doped with areas of a ptype material as shown in figure 5-1. Between the source and the drain, the n-type material acts as a resistor. The current flow (from drain to source) consists of majority carriers (electrons for n-type material).

Fig. 5-1. JFET structure (symmetric)

5-3. JFET Characteristics The junction field effect transistor (JFET) is different from the common bipolar junction transistor (BJT) in many aspects. Unlike BJT’s, the input diode junction of a JFET is reverse biased, and hence it has a very high input impedance. Having high input impedance minimizes the device loading effect on the signal source. The control element of the JFET comes from depletion of charge carriers in the n-channel. When the gate is made more negative, it depletes more majority carriers. This reduces the drain current (ID) for a given value of source-to-drain voltage (VDS). However, for a given value of gate voltage (VGS), the JFET current is very nearly constant (saturated) over a wide range of source-to-drain voltages.

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Fig. 5-2. JFET principle of operation.

The typical current-voltage characteristics of n-channel JFET are shown in Figure 5-3. The three primary regions shown on the graph are the linear region, the saturated region, and the breakdown region. The linear region is that region where the drain to source voltage is less than the drain saturation voltage. It can be seen that the voltage current relationship is a linear function. At the point where the drain to source voltage reaches the drain saturation voltage, the saturated region begins. The curves illustrate that increasing the gate reverse voltage reduces the drain current as well as the drain saturation voltage. This shows the manner in which the drain current is modulated when modulating the gate voltage. The general relation describing the channel current of a JFET is as follows: ID = b [VDS.Vp½ – 2/3 (VDS+Vbi – VGS)3/2 + 2/3(Vbi – VGS)3/2]

(5-1a)

where b = 2 n (W/L).(2e Nd )½ and Vbi is the junction built-in voltage

Vbi = Vt ln (Nd.Na / ni2)

(5-1b)

Here W is the channel width, L is the channel length , μn is the electron mobility, Nd is the channel doping concentration and VP is the pinch-off voltage. 249 Prof. Dr. Muhammad El-SABA

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The pinch-off voltage (VP) is the gate voltage at which the drain current reaches zero, as shown in Fig. 5-3.

Vp= (eNd / 2 ) a2

(5-1c)

Fig. 5-3. JFET modes of operation.

The above I-V characteristics may be simplified in two distinct regions as shown in Fig. 5-4. 1- In the saturation region (where | VDS - VGS | > VP )

ID = IDSS [1+ (VGS /Vp ) ] 2

(5-2a)

IDSS = (2a) (W/L).(e Nd n).VdS

(5-2b)

where

2- In the linear region (where | VdS - VgS | < Vp )

ID = (2a) (W/L).(e Nd n). [1-√ (VGS /Vp) ] VDS

(5-3a)

ID = 2 (IDSS /Vp2).[VGS - Vp – ½ VDS ] VDS

(5-3b)

or

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Fig. 5-4. JFET output characteristics.

The following figure the transfer characteristics (ID versus VGS) of the nchannel JFET. The transfer characteristic for the JTET is useful for visualizing the gain of the device and identifying the linear region. The gain is proportional to the slope of the transfer curve. The current value IDSS represents the value when the gate is shorted to ground, the maximum current for the device. This value is a part of the data sheet supplied by the manufacturer of any JFET. It worth notice that the tangent line representing the gain in the linear region intersects with the zero current line at about half the pinch voltage (VP/2). Note that the trans-conductance of the JFET (gm) in the saturation region is given by:

gm = ∂Id / ∂Vgs = 2( Ip /Vp )

(5-4)

where we put Vgs = Vbi in saturation and hence

Ip = IDSS / [1- Vbi/Vp ]= 2e2 W n Nd2 a3 /3 L

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(5-5)

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Fig. 5-5. JFET output and transfer characteristics.

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5-4. JFET Small Signal Model One can use one of the simple AC models of the JFET, such as the one shown in figure 5-6(a) or the equivalent h-parameters model, to derive the AC voltage gain in an easy way. Figure 5-6(b) depicts the JFET AC model at high frequencies. Note the existence of the JFET parasitic capacitors, Cgs and Cgd.

Fig. 5-6(a). JFET equivalent circuit at low frequency.

Fig. 5-6(b). JFET equivalent circuit at high frequency.

The so called transition frequency, of the FET, is given by:

fT = gm / [2 (Cgs+Cgd)]

(5-6)

Cgs = Cgo/(1 – VGS/Vbi)½

(5-7a)

Cgd = Cgo/(1 – VGD/Vbi)½

(5-7b)

Cgo = ½ W.L (e  Nd /2 Vbi)½

(5-7c)

with

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Example 5-1: Consider a Si n-channel JFET, with Nd =3x1016 cm-3, Na = 1019 cm-3, a = 0.5m, L = 5m, W = 100m and n = 1350 cm2/Vs. Calculate fT. Vp = e Nd a2 /2  = 5.65 V Ip = 2e2 W n Nd2 a3 /3 L = 73.2 mA Vbi = (kBT/e) ln (Na.Nd/ni2) = 0.87V IDS = Ip (1-Vbi/Vp) = 62 mA gm = 2 Ip / Vp = 25.9 mS Cgo = ½ W.L (e  Nd /2 Vbi)½ = 140 pF fT = gm / [2 (Cgs+Cgd)] = gm / [2 Cgo] = 16.8 GHz. 5.5. JFET Amplifiers In much the same way as BJT’s, JFET’s can be mounted in three configurations, namely: 123-

Common gate (C-G) configuration, Common source (C-S) configuration, and Common drain (C-D or source follower ) configuration.

Fig. 5-5. JFET circuit configurations.

Figure 5-5 depicts the circuit configurations, for a n-channel JFET’s. Also, Fig. 5-6 depicts the JFET small signal equivalent circuit, in common source configuration. The AC voltage gain of such a circuit is given by:

Av = Vo / V= - gm ( RL // rd ) 254 Prof. Dr. Muhammad El-SABA

(5-8)

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where gm is the JFET transconductance (gm=DS/VGS) and rd is the output resistance of the JFET (rd =VDS/IDS). For an n-channel JFET in the linear mode rd is defined as follows:

rd = VDS / ID = Ron / [1- √(Vbi-VGS)/Vp ]

(5-9)

where Ron = Vp /3Ip is called the ON resistance of the JFET. The most frequently encountered configuration for a JFET amplifier is the common source circuit. The source is common to the input and output as shown in the diagram.

Fig. 5-6. JFET in common-source configuration

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5-6. Other FET Structures There exist several variations of field effect transistors. However, all field-effect transistors are distinguished by the method of insulation between channel and gate. Field effect transistors include, but not restricted to:  JFET (Junction Field-Effect Transistor) uses a reverse biased p-n junction to separate the gate from the body.  MESFET (Metal–Semiconductor Field-Effect Transistor) substitutes the p-n junction of the JFET with a Schottky barrier; used in GaAs and other III-V semiconductor materials.  HEMT (High Electron Mobility Transistor), which makes use of bandgap engineering in a ternary semiconductor like AlGaAs. HEMT is also called an HFET (heterostructure FET). The fully depleted wideband-gap material forms the isolation between gate and body.  MODFET (Modulation-Doped Field Effect Transistor) uses a quantum well structure formed by graded doping of the active region.  MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor) utilizes an insulator (typically SiO2) between the gate and the body. 5-6.1. MESFET Metal Epitaxial Semiconductor Field Effect Transistor (MESFET) is quite similar to a JFET in construction and terminology. MESFET consists of a conducting channel positioned between a source and drain contact region, as shown in the figure 5-7. The difference is that instead of using a P-N junction for a gate, a Schottky (metal-semiconductor) junction is used. The MESFET differs from the insulated gate FET (IGFET or MOSFET) in that there is no insulator under the gate over the active region. This implies that the MESFET gate should, be reverse biased such that one does not have a forward conducting metal semiconductor (Schottky) diode. While this restriction inhibits certain circuit possibilities, MESFET devices work reasonably if kept within the design limits. Generally the narrower the gate-modulated channel the better the frequency handling capabilities. MESFETs are usually constructed in compound semiconductor technologies such as GaAs, InP, or SiC, rather than silicon.

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The use of GaAs rather than silicon MESFETs provides two significant advantages: first of all the electron mobility is more than 5 times larger, while the saturation velocity is about twice that of Si. Second it is possible to fabricate semi-insulating (non-doped) GaAs substrates, which eliminates the problem of absorbing microwave power in the substrate. MESFETs can be operated up to approximately 30 GHz, and are commonly used for microwave frequency communications and radar.

Fig. 5-7(a). Idealized structure of a GaAs MESFET

The equivalent circuit of a MESFET is quite similar to that of the FET. The following figure depicts the equivalent circuit model of a MESFET at microwave frequencies.

Fig. 5-7(b). equivalent circuit model of a MESFET

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5-6.2. MODFET & HEMT The modulation-doped field effect transistor (MODFET) is a type of heterojunction field-effect transistor, also known as the High Electron Mobility Transistor (HEMT). Like other FETs, MODFETs are used in integrated circuits as digital switches. MODFETs can also be used as amplifiers for large amounts of current. Figure 5-8 depicts an AlGaAs MODFET and its carrier and field distribution. The high carrier mobility and switching speed of MODFETs come from the following. The wide bandgap element is doped with donor atoms; thus it has excess electrons in its conduction band. These electrons diffuse to the adjacent narrow bandgap material. The motion of electrons cause a change in potential and electric field between materials. The electric field will push electrons back to the conduction band of the wide bandgap element. The diffusion process continues until electron diffusion and drift balance each other, creating a junction. The fact that the charge carriers are majority carriers yields high switching speeds, and the fact that the low bandgap semiconductor is undoped means high mobility.

Fig.5-8(a). Idealized structure of an AlGaAs modulation doped FET (MODFET)

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Fig.5-8(b). Electric charge density and electric field across an AlGaAs MODFET

An important aspect of a HEMT is that the band discontinuities across the conduction and valence bands can be modified separately. This allows the type of carriers in and out of the device to be controlled. Figure 5-9 shows the structure of a SiGe HEMT. As HEMTs require electrons to be the main carriers, a graded doping can be applied in one of the materials making the conduction band discontinuity smaller, and keeping the valence band discontinuity the same. This diffusion of carriers leads to the accumulation of electrons along the boundary of the two regions inside the narrow band gap material. The accumulation of electrons leads to a very high current in these devices. The accumulated electrons are also known as two dimension electron gas (2 DEG). Note that most of MESFETs (and other FET structures) use a top layer of low resistance metal on the gate, so that the FET profile looks like a mushroom in cross section 259 Prof. Dr. Muhammad El-SABA

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Fig. 5-9. Detailed structure of a SiGe HEMT

5-7. FET Noise A prime application of MESFETs has been in low-noise amplification. Therefore is important to derive a simple analytic expression for calculating the minimum noise figure of a FET. Since the noise figure of a FET is affected by both bias point and generator impedance, the minimum noise figure, NFmin, defined here is an absolute minimum noise figure obtained by adjusting both bias and generator impedance. According to Fukui, the minimum noise figure of a FET (NFmin) is empirically given by: (5-10) where the factor KF 2.5 to 3.0 for FETs and KF 1.5 to 2.0 for HEMTs. The factor KF is a gross simplification of the drain-current noise contribution to the overall noise. However, using the relationship of the equivalent circuit elements, the expression can be further simplified:

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(5-11)

5-8. JFET Testing Testing a JFET with a multimeter might seem an easy task, because it has only one PN junction to test: either measured between gate and source, or between gate and drain. When a JFET is checked as a diode (gate-tochannel junction) multi-meter should indicate low resistance between gate and source with one polarity and very high resistance between gate and source with meter polarity reversed. If the meter indicates high resistance with both the polarities, it means that the gate junction is open. On the other hand, if meter indicates low resistance with both polarities, it means that the gate junction is shorted.

Fig. 5-10(a). Testing a JFET with a multimeter

Testing continuity through the drain-source channel is another matter, though. Remember from the last section how a stored charge across the capacitance of the gate-channel PN junction could hold the JFET in a pinched-off state without any external voltage being applied across it? This can occur even when you're holding the JFET in your hand to test it! Consequently, any meter reading of continuity through that channel will be unpredictable, since you don't necessarily know if a charge is being stored by the gate-channel junction. 261 Prof. Dr. Muhammad El-SABA

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Of course, if you know beforehand which terminals on the device are the gate, source, and drain, you may connect a jumper wire between gate and source to eliminate any stored charge and then proceed to test sourcedrain continuity with no problem.

Fig. 5-10(a). Testing a JFET with a multimeter

However, if you don't know which terminals are which, the unpredictability of the source-drain connection may confuse your determination of terminal identity. A good strategy to follow when testing a JFET is to insert the pins of the transistor into anti-static foam (material used to ship and store electronic components) just prior to testing. The conductivity of the foam will make a resistive connection between all terminals of the transistor when it is inserted. This connection will ensure that all residual voltage built up across the gate-channel PN junction will be neutralized. Since the JFET channel is a single, uninterrupted piece of semiconductor material, there is usually no difference between the source and drain terminals. A resistance check from source to drain should yield the same value as a check from drain to source. This resistance should be low (a few hundred ohms) when the gate-source PN junction voltage is zero. By applying a reverse-bias voltage between gate and source, pinchoff of the channel should appear by an increased resistance reading on the meter. 262 Prof. Dr. Muhammad El-SABA

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5-9. Summary All field-effect transistors are unipolar rather than bipolar devices. That is, the main current through them is comprised either of electrons through an N-type semiconductor or holes through a P-type semiconductor. The previous discussion of the JFET illustrates that: 1- The junction field effect transistor in its simplest form is essentially a voltage controlled resistor. The resistive element is usually a bar of silicon. For an N-channel JFET this bar is an N-type material sandwiched between two layers of P-type material. 2- The JFET operates as a depletion mode device, and, 3. The JFET performs as a voltage controlled current amplifier. The JFET is preferred in many circuit applications due to its high input impedance because it is a reverse biased PN junction. Its operation is that of the flow of majority carriers only and therefore acts as a resistive switch. It also is inherently less noisy than bipolar devices and can be used in low signal level applications.

The junction field effect transistor (JFET) is different from the common bipolar junction transistor (BJT) in many aspects. Unlike BJT’s, the input diode junction of a JFET is reverse biased, and hence it has a very high input impedance. In this chapter, we summarize some fundamental concepts about junction field effect transistors (JFET). Having high input impedance minimizes the device loading effect on the signal source. 263 Prof. Dr. Muhammad El-SABA

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The following figure depicts the operation of the JFET at different bias conditions.

To calculate drain current (ID) for any given gate-source voltage (VGS), there is a simple equation that may be used. It reflects the nonlinear behavior of the dynamic (ID-VGS) characteristics of a JFET:

There exist several variations of field effect transistors. However, all field-effect transistors are distinguished by the method of insulation between channel and gate. Field effect transistors include, but not restricted to:  JFET (Junction Field-Effect Transistor) uses a reverse biased p-n junction to separate the gate from the body.  MESFET (Metal–Semiconductor Field-Effect Transistor) substitutes the p-n junction of the JFET with a Schottky barrier; used in GaAs and other III-V semiconductor materials.  HEMT (High Electron Mobility Transistor), which makes use of bandgap engineering in a ternary semiconductor like AlGaAs. HEMT is also called an HFET (heterostructure FET). The fully depleted wideband-gap material forms the isolation between gate and body.  MODFET (Modulation-Doped Field Effect Transistor) uses a quantum well structure formed by graded doping of the active region.  MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor) utilizes an insulator (typically SiO2) between the gate and the body. 264 Prof. Dr. Muhammad El-SABA

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5-10. Problems 5-1) What is the basic structure of a JFET? What are its most important parasitics? 5-2) What are key technological constraints in the design and fabrication of JFET? 5-3) Consider the JFET circuit in left-hand side of the figure below. The FET has VP = −3 V, IDSS = 9 mA. Find the values of all resistors so that Vgs = 5 V, Id = 4 mA, and Vds = 11 V. Assume a 0.05 mA current in the voltage divider. If an AC source, vin, is connected to the gate, and the amplified output, vout, is taken from the drain, prove that the AC voltage gain is given by: Av = vo/vin = - gm RD / (1 + gmRS)

5-4) Repeat the above problem for the differential amplifier in the right side figure. 5-5) How do JFET switch? What sets their time response? 5-6) Calculate the ON resistance and the transition frequency of an nchannel Si JFET, given that Nd =3x1016 cm-3, Na = 1019 cm-3, a = 0.5m, L = 5m, W = 100m and n = 1350 cm2/Vs. 265 Prof. Dr. Muhammad El-SABA

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5-7) The field-effect transistor (FET) combines what desired characteristic of the vacuum tube with the other advantages of a BJT? 1. Low output impedance 2. High output impedance 3. Low input impedance 4. High input impedance 5-8) What does the FET use to control the electrostatic field within the BJT? 1. Current 2. Voltage 3. Low input impedance 4. High input impedance 5-9) The JFET gate element corresponds very closely in operation with (a) what part of a BJT and (b) what part of a vacuum tube? 1. (a) Emitter (b) cathode 2. (a) Base (b) grid 3. (a) Base (b) cathode 4. (a) Collector (b) plate 5-10) If a P-type material is used to construct the gate of a JFET, what material should be used to construct the remaining part of the JFET? 1. N-type 2. P-type 3. Mica type 4. Junction type 5-11) When reverse bias is applied to the gate of a JFET, what happens to (a) source-to-drain resistance of the device and (b) current flow? 1. (a) Decreases (b) decreases 2. (a) Decreases (b) increases 3. (a) Increases (b) decreases 4. (a) Increases (b) increases 5-12) What is the "pinch off" voltage of an FET? 1. The voltage required for the FET to conduct 2. The voltage required to overcome the FET reverse bias 3. The voltage required to reduce drain current to zero 4. The voltage required to reduce gate voltage to zero

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5-11. Chapter Assessment Photocopy the following page, read the assessment carefully and answer on the page. Carry out the required measurement, and comment if there exist a discrepancy between the measured and calculated values. Don't forget to write your name and ID.

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5-12. References: [1] P. H. Ladbrooke, MMIC Design: GaAs FETs and HEMTs, Artech House, MA, 1989. [2] J. Millman, and C. Halkias, Integrated Electronics Analog and Digital Circuits and Systems, McGraw-Hill Book Company, New York, 1972 [3] A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley And Son, New York, 1967. [4] H. Fukui, “Design of Microwave GaAs MESFETs for Broad-Band Low-Noise Amplifiers,” IEEE Trans. Microwave Theory and Tech., Vol. MTT-29, No. 10, pp. 176–183, 1979. [5] S. M. Sze, Semiconductor Devices. Physics and Technology. J. Wiley Inc., 2d edition, 2002. [6] S. M. Sze, Semiconductor Devices. Physics and Technology. J. Wiley Inc., 1st edition, 1985. [7] R. Goyal, Editor, Monolithic Microwave Integrated Circuits: Technology and Design, , Artech House, MA, 1989.

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Metal-Oxide-Semiconductor (MOS) Structure & Charge-Coupled Devices Contents: 6-1. 6-2. 6-3. 6-4.

6-5.

6-6.

6-7. 6-8. 6-9.

Chapter Overview and Learning Objectives MOS Energy Band diagram MOS Flatband Voltage MOS Biasing Regimes 6-4.1. Accumulation Mode 6-4.2. Depletion Mode 6-4.3. Inversion Mode MOS Capacitance 6-5.1. Simple Model 6-5.2. Exact Analysis 6-5.3. Advanced Analysis & Quantum Effects Charge-Coupled Devices (CCD) 6-6.1. CCD Diffusion Time 6-6.2. CCD Camera Summary Problems References

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Metal-Oxide-Semiconductor (MOS) Structure & ChargeCoupled Devices 6-1. Chapter Overview and Learning Objectives MOS refers to Metal- Oxide- Semiconductor. The semiconductor is usually silicon. Other material systems have similar structures formed by Metal Insulator–Semiconductor (MIS). The MOS capacitor forms the basis of DRAM storage capacitors and may be simply a capacitance in an analog integrated circuit, like voltage-controlled oscillators (VCO). The MOS structure is also the main building block for the MOS field effect transistor (MOSFET). The substrate is normally grounded and the Gate electrode is usually biased with a voltage, VG, as shown in figure 6-1.

Fig. 6-1. MOS structure

Upon Completion of this Chapter, the student should: Understand the function of the MOS structure. Be acquitted with the biasing methods of the MOS capacitor, Identify the depletion, and inversion modes of the JFET Identify the C-V characteristics of the MOS structure

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6-2. Energy Band diagram of an MOS The following figure depicts the energy band diagram of an ideal MOS structure. Here EO is the vacuum energy level (of free electrons). The minimum energy an electron must have to free itself from the material is called work function. The workfunction of a metal is termed ΦM. This is the energy difference from the Fermi energy (average energy) of an electron in the metal to the vacuum energy level. The work function of the semiconductor is termed ΦS. This is the energy difference from the Fermi energy of an electron in the semiconductor to the vacuum energy level. Note that this energy depends on doping since EF depends on doping.  is the electron affinity of the semiconductor. This is the energy difference from the conduction band minimum in the semiconductor to the vacuum energy level. Note that this energy does not depend on doping. Note also that (EC - EF)FB = ΦS –  in the quasi-neutral region where the bands are not bent (in flat band condition).

Fig. 6-2. Ideal (flatband) MOS energy band structure (n-type semiconductor)

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The insulator is a very wide bandgap material, characterized by an electron affinity, i. In certain situations, of non ideal structures, there may exist some charges near the insulator-semiconductor interface. In such a case, the semiconductor can have an electric field near the insulator that forces the energy bands to bend near the insulatorsemiconductor interface, as shown in Fig. 6-3.

Fig. 6-3. Energy band diagram of a Non-ideal MOS, with band bending.

6-3. MOS Flatband Voltage The flatband energy diagram means that the energy band diagram of the semiconductor has no band bending, which implies that no charge exists in the semiconductor, as shown in figure 6-4. The flatband voltage is obtained when the applied gate voltage equals the workfunction difference between the gate metal and the semiconductor (VFB = MS = M - S). When there is a fixed charge in the oxide or at the oxide-silicon interface, the above expression for the flatband voltage should take them into account. Note that the workfunction of a semiconductor, S, requires some more thought since the Fermi energy varies with the doping type as well as with the doping concentration. This workfunction equals the sum of the electron affinity in the semiconductor, , the difference between the conduction band energy and the intrinsic energy divided by the electronic charge in addition to the bulk potential. This is expressed by the following equation:

MS = M M – – ½ Eg /e – Vt ln (Na / ni) 273 Prof. Dr. Muhammad El-SABA

(6-1)

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Fig. 6-4. Energy band diagram of a flatband MOS structure (Here Al-SiO2-Si).

For a MOS capacitor, which has an n-type substrate with doping density Nd, the workfunction difference equals:

MS =M -s = M – – ½ Eg /e + Vt ln (Nd / ni)

(6-2)

The flatband voltage of real MOS structures is further affected by the presence of charge in the oxide (ox) or at the oxide-semiconductor interface (Qi). In this case, the flatband voltage still corresponds to the voltage, which, when applied to the gate electrode, yields a flat energy band in the semiconductor:

(6-3)

The second term in the above equation is the voltage across the oxide due to the charge at the oxide-semiconductor interface (Qi) and the third term is due to the charge density (ox) inside the oxide (insulator) layer.

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6-4. MOS Biasing Regimes To understand the effect of different bias modes on the operation of the MOS capacitor we consider three distinct bias conditions. We assume here n-type semiconductor. In the first case, which is called the accumulation mode, the gate voltage is positive and below the flatband voltage (VFB > VG > 0). In the second case, which is called the depletion mode, the applied gate voltage is negative and between the flatband voltage and the threshold voltage (VT < VG 0. However, when VG < 0 the Fermi level of the metal side moves upward. In either of the two cases the energy band structure bends (down or up) at the semiconductor-oxide interface.

Fig. 6-5. Ideal MOS in accumulation node (n-type semiconductor with VG> 0).

Applying Poisson’s equation to the oxide, assuming there are no charges in the oxide, yields

d ζox /dx =  = 0  ζox = constant V =  ζox dx  V(x) is Linear with x

(6-5)

6-4.2. Depletion Regime When VG > 0 the metal Fermi-energy is lowered (E= -eV), the insulator has an electric field across it that terminates almost immediately in the near perfectly conducting metal, but terminates over a finite distance in the semiconductor of finite resistivity. The charge model indicates that negative charge must be created in the semiconductor near the interface. This charge is in the form of electrons. Since n = ni exp[(EF - Ei / kBT], the electron concentration in the semiconductor near interface increases. This is called accumulation. 276 Prof. Dr. Muhammad El-SABA

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We now derive the MOS parameters at threshold with the aid of figure 6-7. To simplify the analysis we make the following assumptions: 1) Assume that we can use the full depletion approximation, 2) Assume that the inversion layer charge is zero below the threshold voltage. Beyond the threshold voltage we assume that the inversion layer charge changes linearly with the applied gate voltage. The derivation starts by examining the charge per unit area in the depletion layer, Qd. As can be seen in Figure 6-7(a), this charge is given by:

Qd = - e Na xd

(6-6)

Where xd is the depletion layer width and Na is the acceptor density in the substrate. Integration of the charge density then yields the electric field distribution shown in figure 6-7(b). The electric field in the semiconductor at the interface, ζs, and the field in the oxide equal, ζox:

ζs = - e Na xd /s and ζox = - e Na xd /ox

(6-7)

The electric field changes abruptly at the oxide-semiconductor interface due to the difference in the dielectric constant. At Si/SiO2 interface the field in the oxide is about three times larger since the dielectric constant of the oxide (ox = 3.9 0) is about one third that of silicon (s = 11.9 0). The electric field in the semiconductor changes linearly due to the constant doping density and is zero at the edge of the depletion region, based on the full depletion approximation. The potential shown in Figure 6.3 (c) is obtained by integrating the electric field. The potential at the surface, s, equals:

s = e Na xd2 / 2s

(6-8)

The calculated field and potential is only valid in depletion. In accumulation, there is no depletion region and the full depletion approximation does not apply. In inversion, there is an additional charge in the inversion layer, Qinv. This charge increases as the gate voltage is increased. However, this charge is only significant once the electron density at the surface exceeds the hole density in the substrate, Na. 277 Prof. Dr. Muhammad El-SABA

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Fig. 6-6. nMOS in depletion regime and onset of inversion (VG =VT).

Fig. 6-7. pMOS in depletion regime. (a) Charge density, (b) electric field, (c) potential and (d) energy band diagram

We therefore define the threshold voltage as the gate voltage for which the electron density at the surface equals Na. This corresponds to the situation where the total potential across the surface is twice the bulk potential, F. 278 Prof. Dr. Muhammad El-SABA

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F = Vt ln (Na /ni)

Chapter 6 (6-9)

The depletion layer in depletion is therefore restricted to this potential range:

xd = (2ss/eNa), for 0 ≤ s ≤ 2F

(6-10)

For a surface potential larger than twice the bulk potential, the inversion layer charge increases exponentially with the surface potential. Consequently, an increased gate voltage yields an increased voltage across the oxide while the surface potential remains almost constant. We will therefore assume that the surface potential and the depletion layer width at threshold equal those in inversion. The corresponding expressions for the depletion layer charge at threshold, Qd,T, and the depletion layer width at threshold, xd,T, are: QdT = - e Na xdT

(6-11a)

xdT = √[2s(2F)/eNa]

(6-11b)

Beyond threshold, the total charge in the semiconductor has to balance the charge on the gate electrode, QM, or: QM = - (Qd + Qinv)

(6-12)

where we define the charge in the inversion layer as a quantity, which needs to determined but should be consistent with our basic assumption. This leads to the following expression for the gate voltage, VG: VG = VFB + F + QM /Cox = VFB + F + (QM + Qinv) /Cox

(6-13)

In depletion, the inversion layer charge is zero so that the gate voltage becomes: VG = VFB + F +√(2esNas) /Cox for 0 ≤s ≤ 2 F

(6-14)

while in inversion this expression becomes: VG = VFB + 2F +√(4esNaF) /Cox - Qinv/ Cox

(6-15)

The third term in (6-15) states our basic assumption, namely that any change in gate voltage beyond the threshold requires a change of the 279 Prof. Dr. Muhammad El-SABA

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inversion layer charge. From equation (6-15), we can write the threshold voltage as follows: VT = VFB + 2F +√(4esNaF) /Cox

(6-16)

The threshold voltage dependence on the doping density is illustrated with figure 6-8 for both n-type and p-type MOS structures with an aluminum gate.

Fig. 6-8. Threshold voltage of nMOS (with n-type semiconductor) and pMOS (with p-type semiconductor) structures.

6-4.3. Inversion Regime The following figure depicts the Charge distribution and energy bands of MOS structure in inversion mode for n-type semiconductor (VG < VT) and p-type semiconductor (VG > VT). The basis assumption of the MOS model is that the inversion layer charge is proportional to the applied voltage. In addition, the inversion layer charge is zero at and below the threshold voltage. Thus, for a p-type substrate, we have: Qinv = Cox (VG -VT) for VG > VT Qinv = 0

(6-17)

for VG < VT

The linear proportionality can be explained by the fact that a gate voltage variation causes a charge variation in the inversion layer. The proportionality constant between the charge and the applied voltage is therefore expected to be the gate oxide capacitance. 280 Prof. Dr. Muhammad El-SABA

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Fig. 6-9. Charge distribution and energy bands of MOS structure in inversion mode for n-type semiconductor (VG < VT ) and p-type semiconductor (VG > VT)

The above assumption implies that the inversion layer charge is located exactly at the oxide-semiconductor interface. Because of the energy band gap of the semiconductor separating the electrons from the holes, the electrons can only exist if the p-type semiconductor is first depleted. The threshold voltage (VT) is the gate voltage at which the electron inversionlayer starts at the surface of the semiconductor. Example 6-2: Calculate the P-base doping concentration (assuming it is uniformly doped) of an n-channel silicon MOSFET structure to obtain a threshold voltage of 2V. The gate oxide thickness is 500A. The fixed charge in the gate oxide is 2 x 1011 cm-2. Assume N+ polysilicon with a doping concentration of 1020 cm-3 is used as the gate electrode. 281 Prof. Dr. Muhammad El-SABA

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Solution: The threshold voltage is given by: VT = VFB + 2F - Qox /Cox = VFB + 2Vt ln (Nd/ni) +√(4esNaF) /Cox where we neglected the is the total effective charge in the oxide QOX. In addition, the work-function difference between heavily doped N+ polysilicon and P-silicon must be taken into account. A threshold voltage of 2V is achieved at a doping concentration of 1.16 x 10 17 cm-3. The contribution from the fixed oxide charge is -0.469V. The shift due to the N+ polysilicon gate electrode is -0.968. 6-5. MOS Capacitance The capacitance-voltage (C-V) measurements of MOS capacitors provide a wealth of information about the structure, which is of direct interest when one evaluates a certain MOS process. Since the MOS structure is simple to fabricate, the technique is widely used. To understand capacitance-voltage measurements one must first be familiar with the frequency dependence of the measurement. This frequency dependence occurs primarily in inversion since a certain time is needed to generate the minority carriers in the inversion layer. Thermal equilibrium is therefore not immediately obtained. The low frequency or quasi-static measurement maintains thermal equilibrium at all times. This capacitance is the ratio of the change in charge to the change in gate voltage, measured while the capacitor is in equilibrium. A typical measurement is performed with an electrometer, which measures the charge added per unit time as one slowly varies the applied gate voltage. The high frequency capacitance is obtained from a small-signal capacitance measurement at high frequency. The bias voltage on the gate is varied slowly to obtain the capacitance versus voltage. Under such conditions, one finds that the charge in the inversion layer does not change from the equilibrium value at the applied dc voltage. The high frequency capacitance therefore reflects only the charge variation in the depletion layer and the (small) movement of the inversion layer charge. In this section, we first derive the simple capacitance model, which is based on the full depletion approximation and our basic assumption. The comparison with the exact low frequency capacitance will reveal that the largest error occurs at the flatband voltage. We therefore derive the exact flatband capacitance using the linearized Poisson's equation. Then we discuss the non-ideal effects in MOS capacitors. 282 Prof. Dr. Muhammad El-SABA

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6-5.1. Simple Model The capacitance of an MOS capacitor is obtained using the same assumptions, we supposed so far. The MOS structure is treated as a series connection of two capacitors: the capacitance of the oxide Cox and the capacitance of the semiconductor Cs, which may be in depletion or accumulation or inversion, according to the value of VG.

C(VG) = [1/Cox + 1/ Cs ] -1

(6-18)

Fig. 6-10(a). Schematic model of the equivalent capacitance of a MOS capacitor.

In accumulation, there is no depletion layer. The remaining capacitor is the oxide capacitance, so that the capacitance equals:

CLF = CHF = Cox,

for VG ≤ VFB

(6-19)

In depletion, the MOS capacitance is obtained from the series connection of the oxide capacitance and the capacitance of the depletion layer, or:

CLF = CHF = (1/Cox + xd /s )-1

for VFB ≤ VG ≤ VT

(6-20a)

where xd is the variable depletion layer width which is calculated from:

xd = [ 2s s /e Nd]½

(6-20b)

In order to find the capacitance corresponding to a specific value of the gate voltage, we also need to use the relation between the potential across the depletion region and the gate voltage, which is given by: VG = VFB + s +√(2esNas) /Cox

for 0 VGS - VT. Therefore the drain current equals:

The trans-conductance is given by:

The output conductance is given by:

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Note 7-2. Derivation of the MOSFET I-V Characteristics 1-In the linear region where VGS >VT and 0< VDS < Vdsat Neglecting the diffusion current, and admitting the current in the ydirection only, we have the channel current density is given by:

where  is the lateral potential. The drain current is given by:

Integrating along the channel in the y-direction yields:

Now we need a relation between the inversion layer charge and the lateral potential . Neglect all but the mobile inversion charge. The charge in the semiconductor is a linear function of position y, such that.

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2-In the saturation region (for VDS > VDsat) we have

In this case the charge is zero (refer to figure 7-7) such that

 Substituting this in the expression of ID yields:

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Chapter 7

7-5. MOSFET Subthreshold Regime As the power supply voltage VDD is continuously reduced to minimize energy per operation, MOSFET‟s make the transition from superthreshold (super-VTH) operation in strong inversion with large gate overdrives, to near-VTH operation in weak inversion with very small overdrives, and finally into sub-threshold (sub-VTH) operation. The sub-threshold operation of a MOSFET differs from the normal superthreshold operation. In fact, the existence of the inversion layer above threshold is a basic assumption of the MOSFET analysis. Accordingly, when no inversion layer exists, no current will flow below threshold. However, the actual sub-threshold current is not actually zero but reduces exponentially below the threshold voltage as follows (for NMOS):

 V  VTN W  I on _ SUB  K n/  .(n  1).VT2 . exp  GS L  n.VT

 V .1  exp  DS   VT

  (7-7a) 

where n is the sub-threshold ideality factor : .

n 1

1  eN a    2C ox   F 

(7-7b)

The on-current of a MOSFET is defined as IDS, when VGS = VDS = VDD. It is important to highlight the implicit VTN dependence on L because Ion-sub becomes very sensitive to L due to the VTN term. VTN is also dependent on VDS via drain-induced barrier lowering (DIBL).

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7-6. MOSFET Small Signal Equivalent Circuit Model The small signal model shown below can be useful for extrapolating and interpolating the S-parameters as well as for use in circuit simulators that cannot handle S-parameters directly. The element values are derived by fitting the calculated S-parameters of the model to measured data. The bias points and bonding configuration are as described in the individual device data sheets. The MOSFET parasitic capacitances are bias dependent, as shown in the following figure.

Fig. 7-8. AC model of a MOSFET at high frequency. The intrinsic MOS model is shaded, and the external packaging and stray parasitics are indicated in the outside.

Fig. 7-9. Bias dependence of the MOSFET parasitic capacitances.

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7-7. -MOSFET as an Amplifier In much the same way as BJT‟s, MOSFET‟s can be mounted in three configurations, namely: 1- Common gate (C-G) configuration, 2- Common source (C-S) configuration, and 3- Common drain (C-D or source follower ) configuration. Figure 7-10 depicts the circuit configurations, for an N-channel MOSFET‟s. Also, figure 7-11 depicts the NMOS small signal equivalent circuit, in common source configuration. The AC voltage gain of such a circuit is given by:

Av = Vo / vg= - gm (RL//rd)

(7-8)

where gm is the MOSFET transconductance (gm=ds/Vgs) and rd is the output resistance of the MOSFET (rd =Vds/Ids). For an n-channel MOSFET in the linear mode rd is defined as follows:

rd = vds / ids = K’(W/L).(VGS - VTN)

(7-9)

Fig. 7-10. MOSFET circuit configurations.

Fig. 7-13(a). MOSFET small signal equivalent circuit at low frequency

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At high frequencies, the parasitic inter-electrode capacitances, between MOSFET layers, become significant and should be considered in the small-signal equivalent circuit. The following figure depicts the small signal model of a MOSFET, at high frequencies. Aside from the lowfrequency lumped elements, we can find gate-drain capacitance Cgd, gatesource capacitance Cgs. The extra elements include the gate resistance RG and drain resistance RD and the substrate resistance as well as the corresponding lead inductances RS. RD and RSUB.

Fig. 7-11(b). AC model of a MOSFET at high frequency. The intrinsic MOS model is shaded, and the external packaging and stray parasitics are indicated in the outside.

The MOSFET cutoff frequency or the unity current gain frequency (ft) is defined when the transistor current gain equals one. This frequency is given by:

ft ≈ gm /2Cg where Cg = Cgs + Cgd.

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(7-10)

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7-8. -MOSFET as a Switch Figure 7-12 depicts the switching circuit for a p-channel MOSFET as well as its switching waveforms and times. The maximum switching frequency fsw is determined by the total of delay and rise time td(ON) + tr for the turn-ON, and delay and fall time td(OFF) + tf for turn-OFF.

Fig. 7-12. MOSFET switching circuit and waveforms

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7-9. MOSFET Scaling The reduction of the MOSFET dimensions has been dramatic during the last three decades. Starting at a feature length of 10m in 1970‟s and reached below 0.1m in 2005. Proper scaling of MOSFET however requires not only a size reduction of the gate length L and width W. It also requires a reduction of all other dimensions including the oxide thickness. This also implies scaling of the substrate doping density. There are two common types for scaling: constant field scaling and constant voltage scaling. Constant field scaling yields the largest reduction in the power-delay product of a single transistor. However, it requires a reduction in the power supply voltage. Constant voltage scaling provides voltage compatibility with older circuit technologies. The disadvantage of constant voltage scaling is that the electric field increases as the minimum feature length is reduced. This leads to mobility degradation and increased leakage currents. The following figure depicts the ideal and real scaling parameters of a MOSFET. The scaling parameters of MOSFET devices are also listed in Table 7-2. It should be noted that the drain induced barrier lowering (DIBL) refers to the effect of the drain voltage on the output conductance and threshold voltage. This effect occurs in MOSFET devices when only the gate length is reduced without properly scaling the other dimensions.

Fig. 7-13. Illustration of the MOSFET Scaling parameters.

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Figure 7-14 depicts the effect of scaling down the channel length on the static I-V characteristics of an N-channel MOSFET. This effect is called the channel modulation effect and is modeled by adding the channel modulation parameter ()to the I-V characteristics in the saturation region, as indicated by equation (7-3).

Fig. 7-14. Effect of channel length modulation on the static I-V characteristics of an n-channel MOSFET Table 7-2. MOSFET scaling factors

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The reduction in device size causes several problems in MOS transistor design. They may be roughly divided into several groups: Problems due to an increased electric field strength: The oxide reliability; Time-dependent dielectric breakdown (TDDB) is strongly dependent on the oxide thickness, supply voltage and the technology process (the density distribution and the size of defects). The reliability problems caused by the hot-carrier effects in silicon: the avalanche multiplication, the avalanche breakdown and the hotcarrier injection into the oxide. The mobility reduction due to the high field at the interface; the transit time increases and the drain current decreases, causing a degradation of the driving capabilities of the devices and its speed. The reliability problems and the leakage current caused by the tunneling through the gate oxide Problems due to increased power dissipation. Increasing resistances of the contacts and the interconnection lines. The electro-migration in the contacts and the interconnection lines. The contacts and interconnectors must be low resistance and high reliable. The problems related to the distributions of potential and charge: The drain-induced-barrier-lowering (DIBL) effect; the turn-off characteristics degrade. The punch-through effect The parasitic bipolar-transistor action (between source, bulk and drain); the breakdown voltage (BVCEO) decreases because the diffusion length of minority carriers does not scale down Threshold voltage variations; sensitivity to the process parameters and the fluctuations in the dopant distribution Series resistances; There is a strong demand for the low-resistance shallow junctions. The polysilicon-gate depletion effect Statistical variations increase with reduction of dimensions. Moreover, with lowering supply voltages and reducing threshold voltages the leakage currents become increasingly important. In addition, the problems of isolation between adjacent devices and between the devices and the substrate, as well as the latchup phenomena in CMOS circuits.

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7-10. MOSFET Degradation & Hot Carrier Effects As MOSFET dimensions shrink to submicron and below, the limits of conventional MOS structures are becoming more pronounced due to strong short-channel and hot carrier effects, causing a significant degradation of device performance. The following table depicts the main mechanisms of hot carrier in MOSFET devices. Table 7.3. Mechanisms of degradation due to high electric field in MOSFETs.

Mechanism Light Emission Impact Ionization

Carrier Energy (E, eV) E > Eg =1.12eV 1.3 < E 3.2eV

Hot-Hole Injection

E > 4.8 eV

Effects Leakage current Latch-up, Snap-back, Leakage Threshold shift due trapping and trap generation

7-10.1. Hot-carrier Injection Currents Among the various known mechanisms one can cite 4 carrier injection (over the barrier) mechanisms, which are commonly encountered in MOSFET devices. drain avalanche hot carrier injection (DAHCI), channel hot electron injection (CHEI), substrate hot electron injection (SHI) and secondary generated hot electron injection (SGHEI) The channel hot electron injection (CHEI) occurs when the gate voltage is high enough and VG ≈VD. Channel carriers which are accelerated by lateral fields and transported from the source to the drain may be driven towards the gate oxide before they reach the drain. The drain avalanche hot carrier injection (DAHCI) occurs when a high drain voltage is applied in non-saturatation mode (VD>VG) which results in a high electric field near the drain, and hence accelerating channel carriers into the drain depletion region. The accelerated channel carriers collide with Si atoms valence electrons, creating electron-hole pairs by impact ionization. Some of the generated electron-hole pairs are again accelerated and may acquire sufficient energy to surmount the Si/SiO2 barrier. The hot carriers that surmount the gate oxide barrier can inject into the gate oxide where they may be trapped and cause a shift in the MOSFET threshold voltage. 322 Prof. Dr. Muhammad El-SABA

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The substrate hot electron injection (SHEI) occurs at high substrate bias, |VB| >> 0 and strong inversion, usually with both drain and source grounded. Under this condition, carriers of one type in the substrate are driven by the substrate field toward the Si-SiO2 interface. Carriers can be generated by external optical or thermal excitation. As carriers move toward the substrate-oxide interface, they gain further kinetic energy from the high field in surface depletion region. They eventually overcome the surface energy barrier and get injected into the gate oxide, where some of them are trapped. The secondary generated hot electron injection (SGHEI) occurs under conditions similar to DAHCI, when VD>VG, which lead to impact ionization of hot carriers. However, SGHEI involves secondary carriers that are created by an earlier incident of impact ionization and driven under the influence of the substrate bias. This bias produces a field that drives hot carriers toward the surface region, where they gain more energy to overcome the gate oxide barrier. The so-called “channel-initiated secondary electron (CHISEL) is a variant of the SGHEI, which relies on ionization feedback and is activated by a negative substrate bias VB> 0)

SGHEI (VB > 0)

Fig. 7-15. Illustration of different hot carrier injection mechanisms in MOSFET Devices.

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The injection of hot-electrons into the gate-oxide has been usually modeled by the lucky-electron model, which was initially proposed by Shockley to model the impact ionization phenomenon. In fact, measurements of hot carrier emission probability by Ning et al. and Garrigues and Hillouin showed an exponential behavior, like the lucky electron model. According to the lucky electron model, the electron emission probability Pn is equal to the probability that an electron drifts, under the effect of electric field ζ, a distance greater than d without collision.

Pn(ζ) = Pno exp [ - d / n ]

(7-11)

where d = (B/eζ) is the minimum path an electron should travel to gain an energy equal to the barrier height and n is the mean value of the electron free path between collisions. According to Ning‟s measurement, Pno =2.9 and n=91Å at room temperature. According to Hu, the probability of emission of a channel electron through gate is a combination of the probabilities of the following events: the electron gains sufficient energy from the lateral field to overcome the interface barrier, the electron reaches the interface without suffering any collision, and the electron is not scattered back into the semiconductor in the imageforce potential well. On the basis of the lucky-electron model, it can be shown that the fraction of the channel carriers which are injected into the gate oxide is given by:

 B I inj  I sub exp    en //

  

(7-12a)

Here ζ// is the effective lateral electric field and B is the effective potential barrier of the Si/SiO2 interface, which is given by:

 B   Bo  a  ox  b ox2 / 3

(2-12b)

where Bo, a and b are constants, expressing the main barrier height and lowering effects due to image force and quantum tunneling. The last lowering term was added by Ning to account for the tunnel injection current when band bending is lower than the potential barrier. 324 Prof. Dr. Muhammad El-SABA

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For Si/SiO2 interface, we have: Bo =3.2eV, a=2.59x10-4 e(Vcm)½ and b=10-5 e(Vcm2)1/3 at 300K. Also, for ζox= 106V/cm, B =3.1eV. As the substrate current is generated due to impact ionization in the lateral electric field close to the drain, it is expected to be linearly proportional to the drain current. Therefore, it can be shown that the substrate current is given by: Ld

I sub  I ds   n dy

(7-13)

0

where Ids is the drain current, Ld is the length of the pinch-off region and n is the electron impact ionization coefficient in the velocity-saturated part of channel.

Fig. 7-16. Hot carrier injection and gate currents.

7-10.2. Gate Tunneling Currents In addition to the above indicated hot-carrier effects, one can add the gate-tunneling leakage current, as one of the degradation effects in small MOSFET devices. There exist a variety of tunneling processes that can be identified in semiconductor-insulator structures in general and MOS devices in particular. When we consider the shape of the energy barrier of such structures, we can distinguish the Fowler-Nordheim (FN) tunneling and the direct tunneling. 325 Prof. Dr. Muhammad El-SABA

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Fig. 7-17. Schematic of the tunneling current in a MOSFET device

The direct tunneling can take place at low gate voltages via thin oxides layers (less than 50Å) and has a weak dependence on the gate field. The FN tunneling is a field-assisted mechanism which is strongly dependent on the gate field and dominates in modern MOS structures. The gate tunneling current density may be given by the following formula: 

J G   g c ( E n ).u n f n ( E n ).T ( E n ).dE n

(7-14)

0

where T(En) is the tunneling probability, gc(En) is the density of states in the conduction band, un┴ is the electron group velocity perpendicular to the semiconductor surface (un┴ ≈ ¼ un). The integration in the above equation starts from the semiconductor conduction band edge, as a reference. For trapezoidal barrier of upper height B and lower hight (o B - eVox), where Vox is the potential voltage across the insulator gate, the tunneling probability is usually expressed using the WKB approximation as follows:  4 2mox  B  En 3 / 2  T ( En )  exp   3e ox 

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(7-15a)

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In the upper triangular part of the barrier, where B > En > o and  4 2mox 3/ 2 3/ 2 T ( En )  exp  .  B  En    B  En  eVox   3e ox



 

(7-15b)

in the lower rectangular part of the barrier where En < o. Here ζox and mox are the electric field and effective mass of electrons at the insulator (for SiO2, mox =0.42m0).

Fig. 7-18. Tunneling coefficient across gate dielectric barrier (of thickness tox) in a MOS structure as a function of electron energy

In the case of the field-assisted Fowler-Nordheim mechanism, we consider the triangular part of the barrier. Assuming the energy distribution function as Maxwellian and the energy bands as parabolic, we get the following field-dependent gate current density:

JG = J0 .ζox2 exp [ζ0 / ζox]

(7-16a) 327

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where the Jo and ζ0 are constants, related to the energy barrier height B between the insulator and the injecting conductor as follows:

o 

4 2mox 3/ 2 . B  3e

(7-16b)

e2 Jo  . 16 2 ( mox / mo )..B

(7-16c)

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7-11. Advanced MOSFET Structures The explosion of digital technologies has pushed the advancement of MOSFET technologies faster than any other Si transistor. This has happened due to the MOSFET being the prime building block of CMOS digital logic circuits. The MOSFET has become increasingly smaller in the last two decades, today's MOSFETS used in ICs have a channel length of less than 100nm. MOSFETs which are smaller have two main advantages. The first is that smaller MOSFETs allow more current to pass since conceptually a MOSFET acts a variable resistor in the on state and a shorter resistor corresponds to less resistance and energy dissipated. Secondly, the gates are smaller which means the capacitance is lower, decreasing the amount of time in which it takes the capacitor to charge, thus increasing switching time and increasing processing power. Lastly, smaller MOSFETs result in more transistors per chip, thus either increasing the processing power per chip or reducing the cost per chip. Recently, the small size of MOSFETs has created operational problems as producing such tiny transistors is an enormous challenge, often limited by advances in semiconductor device fabrication. Also due the small size, the amount of voltage that can be applied has to be reduced to keep the device stable. Due to these reduced threshold voltages, when the transistor is turned off it will still conduct a small amount of current. This is due to a weak inversion layer which consumes power when the transistor is off, called the sub threshold leakage. Previously this was a non-issue with larger transistors, however in the smaller devices of today, the sub threshold leakage can result in 50% of the total power consumption of the transistor. Therefore, the extrapolation of the current designs for high frequency MOSFETs is necessary to process information at higher speeds. An alternative approach has been to attempt to find new devices. In fact, an extensive research has been devoted for the fabrication of new classes of MOSFET devices, which are capable of scrapping new horizons of applications. In the following subsections, we present the main developments, which have been carried out to improve the performance of MOSFET devices or to introduce new MOS devices, with new concepts. 7-11.1. CMOS Technology Complementary Metal-Oxide-Silicon (CMOS) circuits make use of both nMOS and pMOS transistors on the same substrate. Therefore, an n-type well is provided in the p-type substrate. This structure dissipates minimal power, only during switching times. 329 Prof. Dr. Muhammad El-SABA

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The gate oxide, poly-silicon gate and source-drain contact metal are typically shared between the pMOS and nMOS technology, while the source-drain implants must be done separately. The following figure depicts a CMOS inverter and its layout diagram.

Fig. 7-19. Schematic of a CMOS inverter

CMOS circuits are advantageous because they allow virtually no current to input through and thus consume very little power. This is done by wiring every PMOSFET with a NMOSFET in a way such that whenever one is conducting, the other is not. This not only conserves energy but also helps to reduce heat dissipation which otherwise would cause the circuit to fail. 7-11.2. Poly-Silicon Gate Technology An early improvement of the MOS technology was obtained by using a poly-silicon gate (instead of metal gate), yielding a self-aligned structure which is both compact and better performance. In fact the Si/SiO2 interface has fewer defects and lower workfunction than M-S contact. In addition, the poly-silicon gate is used as a mask during the implantation so that the source and drain regions are self-aligned with respect to the gate. This self-alignment structure reduces the device size. It also eliminates the large overlap capacitance between gate and drain, while maintaining a continuous inversion layer between source and drain. A further improvement of this technique is the use of a low-doped drain (LDD) structure, as shown in the following figure. Here a first shallow implant is used to contact the inversion layer underneath the gate. The shallow implant causes only a small overlap between the gate and source/drain regions. After adding a sidewall to the gate a second deep implant is added to the first one. This deep implant has a low sheet resistance and adds a minimal series resistance. 330 Prof. Dr. Muhammad El-SABA

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Fig. 7-20. Schematic of self-aligned poly-silicon gate transistor with local oxidation isolation (LOCOS) isolation

The combination of the two implants therefore yields a minimal overlap capacitance and low access resistance. The use of a poly-Si gate has the disadvantage of increasing the sheet resistance of the gate. This leads to high delay time of long poly-Si lines. This delay can be reduced by using silicides (like WSi, TaSi) on top of poly-Si.

Fig. 7-21. Schematic illustration of a recent 90nm MOSFET structure, showing the n+ source/drain extensions (SDE) and p+ pockets (or halo extensions).

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The so-called deep-submicron MOS (DSM) devices have channel lengths smaller than 0.1 m. Such MOSFET‟s can operate at low voltage with high performance, in terms of gain and maximum frequency. Figure 7-21 depicts a 0.09m N-channel MOSFET (L=90 nm) in bulk silicon with super steep retrograde (SSR) channel doping, source/drain extension (SDE) and highly-controlled pockets or halo extension. The later additions help to suppress the short channel effects. The thin salicide (self-aligned silicide) layers such as TiSi or CoSi2, are usually deposited beneath the thin oxide, to prevent spiking into shallow junctions during metallization of contacts. 7-11.3. Silicon on Insulator (SOI) and SiGe on Insulator (SiGeOI) The conventional MOSFET structures, such as bulk MOS transistors, are approaching fundamental physical limits. Further increase in speed of integrated circuits is obtained by introducing the so-called silicon-oninsulator (SOI) technology. In SOI technology, all processes are worked on 1m thick mono-crystalline silicon layer, which is deposited on insulated substrate. Alternatively, the silicon-on-oxide (SOX) technology consists in implementing CMOS processes on buried oxide, as shown in figure 7-20. A buried oxide layer is formed in a bulk Si substrate by highdose oxygen implantation and high-temperature annealing.

Fig. 7-22. Schematic of SOI and SiGe on insulator MOSFET’s

Actually, SOI MOSFETs are some sort of quantum devices, because electrons are quantized into 2-dimensional electron gas (2DEG) by the gate electric field applied perpendicular to the Si/SiO2 interface. Figure 7-21 depicts the I-V characteristics of an SOI-NMOS at VGS =1V.

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As shown in figure 7-23, the so-called floating body effect lead to a pronounced kink in the I-V characteristics, as follows. At the onset of impact ionization, electron-hole pairs are created. The holes accumulate in the body and raise the effective body potential and the drain current increases.

Fig. 7-23. The I-V characteristics of an SOI MOSFET (at VGS=1V), showing, the kink effect. Note that this effect is tightly related to the impact ionization mechanism.

The following figure shows the cross section of single and dual-gate SOI transistors, where tof , tsi, and tob represent front-gate oxide, silicon film, and back-gate oxide thickness, respectively. tof is usually taken as the minimum oxide thickness for high performance. tob is usually larger than tof . When the silicon film is thicker than the maximum gate depletion width, SOI exhibits a floating body effect and is regarded as a partiallydepleted SOI MOSFET. If the silicon film is thin enough such that the entire film is depleted before the threshold condition is reached, the SOI device is referred as a fully-depleted SOI MOSFET. Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. The following Table shows the roadmap of DG-SOI MOS and its parameters

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Fig. 7-24. Single-gate and double-gate SOI MOSFETs

Table 7-4. Roadmap of MOSFET transistors Year (Technology Node) Gate Length (L), Gate-oxide thickness (tox), Channel Doping (Na), cm-3 Supply Voltage (VDD), Performance (fT),

2005 (100nm)

2008 (70nm)

2011 (50nm)

2014 (35nm)

65nm 1.5nm 6x1018 1.2V 2 GHz

45nm 1.2nm 9x1018 0.9V 2.5GHz

32nm 0.8nm 1.5x1019 0.6V 3GHz

22nm 0.6nm 2.5x1019 0.6V 3.6GHz

The strained Si and SiGe technologies have been used recently in CMOS fabrication to substantially improve performance. In fact, the strained Si technology has gained an industrial interest due to its better transport properties and compatibility with CMOS processes. 7-11.4. Multi-Gate and 3-D MOSFET Structures With the availability of DSM devices, the miniaturization of silicon further progresses into the nanometer range. Considerable interest has focused on MOSFET device structures in which current channels are fabricated on a 3D substrate, as shown below in figure 7-25. The multi-gate MOS reduce spread of Vd, gives lower threshold voltage, enables lower channel doping and lower effective field (and hence better channel mobility), which all give higher speed The following figure shows the electrostatic potential contours in a dual gate MOSFET. 334 Prof. Dr. Muhammad El-SABA

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Fig. 7-25. Multi-gate MOSFET’s. (a) planar dual-gate MOS, (b) vertical transverse channel MOS and (c) vertical longitudinal channel MOS (fin-type MOSFET)

Fig. 7-26. electrostatic potential contours in a dual gate MOSFET

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In addition to multi-gate planar FET, the future trends in MOSFET technology include the following points:  Advanced Channel Materials (such as Ge, SiGe and III-V materials),  Tunnel Transistors As shown in the following figure, the FinFET is actually a double gate device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering.

Fig. 7-27. Schematic of a FinFET (double-gate MOSFET).

7-11.5. Thin-Flm Transistors (TFT) The thin film transistor (TFT), is a MOSFET device that is used as a switch for each pixel in the active matrix LCDs technology. The TFTs are fabricated in a thin film of amorphous or polycrystalline Si material that is deposited on a glass substrate. The figure 7-30 depicts the technological steps for fabrication TFT‟s.

Fig. 7-28(a). Schematic simple gate, dual-gate N-channel TFT

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Fig. 7-28(b). Schematic of a CMOS TFT

7-11.6. Active-Matrix LCD The active matrix LCD‟s is one of the most interesting types of flat panel displays, nowadays. A TFT liquid crystal display is a device controlled by electric signals. The liquid crystal sits between two transparent layers of conductive Indium-tin-oxide (ITO) electrodes. Liquid crystal molecules are aligned in different directions by varying the voltage applied to the ITO electrodes. The direction of the LCD molecules directly affects the penetration level of the light source, which in turn creates the desired light and darkness in the image. Color is produced by the color filter substrate.

Fig. 7-29. TFT array and display structure

As we have pointed out earlier, the TFTs are fabricated in a thin film of amorphous or polycrystalline semiconductor material that is deposited on a glass substrate. The first thin film semiconductor material that was investigated for AM-LCD‟s was polycrystalline CdSe. 337 Prof. Dr. Muhammad El-SABA

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Amorphous silicon was proposed in the late seventies and proved to combine the advantages of both polycrystalline CdSe and amorphous silicon films.

Fig. 7-30. Thin film transistor technology.

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Fig. 7-31. LCD with TFT

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7-12. MOSFET Testing While checking MOSFET, the resistance measured between gate and drain should be infinitely high in either polarity. Low resistance means faulty device. A rather simple MOSFET tester is shown in figure 7-32(b), below. As shown in figure, the if the N-MOS under test is good, then the orange Led should glow.

Fig. 7-32(a). Simple MOSFET testing circuits

Fig. 7-32(b). MOSFET tester circuit

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7-13. Computer Simulation & Modeling Parameters To examine the parameters of MOSFETs, it is useful to have a sample datasheet in hand. The SPICE model of a MOSFET includes a variety of parasitic circuit elements and some process related parameters in addition to the elements previously discussed in this chapter. The syntax of a MOSFET incorporates the parameters a circuit designer can control: MOSFET syntax M + [L=][W=][AD=][AS=] + [PD=][PS=][NRD=][NRS=] + [NRG=][NRB=] where L is the gate length, W the gate width, AD the drain area, AS the source area. PD is the drain perimeter, PS is the source perimeter Example: M1 3 2 1 0 NMOS L=1u W=6u .MODEL NFET NMOS (LEVEL=2 L=1u W=1u VTO=-1.44 KP=8.64E6 NSUB=1E17 TOX=20n) where M1 is one specific transistor in the circuit, while the transistor model "NFET" uses the built-in model NFET to specify the process and technology related parameters of the MOSFET. A list of selected SPICE parameters is provided in the table below. Table 7.3:

SPICE parameters and corresponding equations

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7-14. Summary The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) may be divided into two major types. 1- Enhancement Mode MOSFET. It is called enhancement because conduction occurs only after the channel conductance is improved” or enhanced. 2- Depletion Mode MOSFET. The channel is pre-fabricated, during the device fabrication. Both enhancement mode and depletion mode MOSFETs may be nchannel or p-channel. The following figure depicts the circuit symbols of all MOSFET types.

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The MOSFET I-V characteristics have 3 distinct regions of operation, namely: 1- Cutoff mode, 2- Linear region and 3- Saturation region.

The trans-conductance (gm) of an enhancement MOSFET in the linear region is given by:

The output conductance (gd) of an enhancement MOSFET in the linear region is given by:

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The following table summarizes the main parameters and modes of operation of the enhancement MOSFETs.

The small signal model of the MOSFET is as simple as follows:

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7-15. Problems 7-1) The MOSFET has which of the following advantages over the JFET? 1. Less bias 2. Higher input impedance 3. Higher output impedance 4. All of the above 7-2) The MOSFET is normally constructed so that it operates in either the depletion mode or the enhancement mode. The depletion mode MOSFET (a) uses what type of bias and (b) has what type of doped channel to cause a depletion of current carriers in the channel? 1. (a) Reverse (b) lightly-doped 2. (a) Forward (b) lightly-doped 3. (a) Reverse (b) heavily-doped 4. (a) Forward (b) heavily-doped 7-3) The enhancement mode MOSFET (a) uses what type of bias and (b) has what type of doped channel to enhance the current carriers in the channel? 1. (a) Reverse (b) lightly-doped 2. (a) Forward (b) lightly-doped 3. (a) Reverse (b) heavily-doped 4. (a) Forward (b) heavily-doped 7-4) Consider the following I-V characteristic for an N-channel MOSFET with W = L = 100μm , measured at VGS = 2V and VDS = VGS :

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The following figure shows MOS capacitors fabricated on the same substrate as the N-MOSFETs, with the same N+ polysilicon gate material, gate oxide thickness, and substrate doping, and an area A= 2100 μm × 100 μm, with the following C-V characteristic:

(a) Find the oxide capacitance per unit area, Cox , and the threshold voltage, VTN , for the N-MOSFET (b) Derive an expression for the electron mobility, μn , in the MOSFET channel, in terms of the slope, gd , and the other parameters given above. (c) Sketch ID versus VDS, for VGS = 2V, VBS = 0V, for the N-MOSFET. Label the values of the saturation voltage, VDsat, and current, IDsat. Indicate the regimes of operation. (d) Calculate the electron velocity at the source end of channel, vy (y = 0) and at the drain end of the channel, vy (y = L), for VGS = 2V, VDS = 0.5V, and VBS = 0V . (e) The value of VBS is now changed to −3V. Calculate the new values for VDS sat and IDsat for VGS = 2V and VBS =−3V , assuming that the substrate doping is N= 1017 cm−3 . 7-5) A silicon MOSFET (nI = 1010 cm-3, s/e0 = 11.9 and ox/0 = 3.9) is scaled by reducing all dimensions by a factor of 2 and by increasing the doping density of the substrate by a factor of 4. Calculate the ratio of the following parameters of the scaled device relative to that of the original device: a. The transconductance gm at VGS - VT = 1V. b. The gate capacitance c. The threshold shift when increasing the reverse bias VBS of the sourcebulk diode from 1V to 3V. d. The breakdown voltage of the oxide. 346 Prof. Dr. Muhammad El-SABA

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7-6) Consider the MOSFET circuit shown in figure below. The MOSFET has VTN = 1V and Kn = 25 A/V2. Calculate the quiescent point (IDS, VDS) and the trans-conductance (gm) of the MOSFET. Take the modulation parameter  = 1V-1.

7-7) Calculate the AC voltage gain of the following MOSFET circuit. The AC output is taken from drain to ground (across R3). Repeat for the case when a source resistance of 1k is inserted in the same circuit. Hint: Draw the AC equivalent circuit. Replace the MOS with the appropriate small signal model and then calculate Av = (vds/vgs). 7-8) If the substrate of the MOSFET shown in problem 7-6 is connected to a 5V reverse bias (instead of being grounded), what would be the effect on the voltage gain?

7-9) Laboratory Assignment In this practical assignment, you will characterize the current-voltage characteristics of an N-channel MOSFET. In order to do this, you may use the virtual laboratory WebLab, from MIT Microelectronics. The WebLab server is available at http://ilab.mit.edu/. The N-channel MOSFETs is labeled “nMOSFET” (2N7000). This exercise involves three phases: (i) characterization of the devices, large and small signal parameter extraction, (ii) using the measurements to choose bias voltages for a common collector amplifier to meet amplifier specifications, and (iii) using the measurements to determine small signal model parameters. When you are done with good results, download the data to your PC for more analysis. Write a report which describes what the measured data should look like and gives a short overview of the relevant equations. 347 Prof. Dr. Muhammad El-SABA

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7-16. Chapter Assessment Photocopy the following page, read the assessment carefully and answer on the page. Carry out the required measurements, and comment if there exist a discrepancy between the measured and calculated values. Don't forget to write your name and ID.

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7-17. References: [1] S. M. Sze, Semiconductor Devices. Physics and Technology. J. Wiley Inc., 1st edition, 1985. [2] Jacob Millman, Christos C. Halkis, “Integrated Electronics, Analog and Digital circuit and systems”, Tata McGrow-Hill publishing Company Limited, New Delhi, 1991. [3] M. Bohr, “MOS Transistor: Scaling and Performance Trend”, Semiconductor International, pp.75-78, June, 1995. [4] Y. Taur and T. H, Ning, “Fundamentals of Modern VLSI Devices”, Cambridge University Press, 1998. [5] S. M. Sze, Semiconductor Devices. Physics and Technology. J. Wiley Inc., 2d edition, 2002. [6] A. P. Sutton, Electronic Structure of Materials, Clarendon Press, Oxford, 2004. [7] Semiconductor Industry Association, “International Technology Roadmap for Semiconductors”, ITRS 2009, 2010.

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Semiconductor Power Devices Contents: 8-1. 8-2.

Overview and Learning Objectives Bipolar Power Devices 8-2.1. Power PIN i. PIN operation & I-V Characteristics ii. PIN Switching Characteristics 8-2.2. Power BJT i. Safe Operating Area (SOA) ii. Emitter Current Crowding iii. Kirk Effect iv. Switching Times & Switching losses v. Packaging 8-2.3. Power Darlington Transistors 8-2.4. Thyristors i- Thyristor Structure & Operation ii- Thyristor I-V Characteristics iii- Thyristor Fabrication Techniques iv- Thyristor Packaging v- Thyristor Testing vi- Thyristor Application Circuits vii- Other Thyristor Devices 8-2.5. Diac and Triac 8-2.6. GTO iGTO Basics ii- GTO Structure iii- GTO Operation 351

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8-3.

8-4. 8-5. 8-6. 8-7.

8-8. 8-9. 8-10. 8-11.

iv- GTO Switching Circuits v- GTO Safe Operating 82.7. Integrated-Gate Thyristor (IGT) MOSFET Power Devices 8-3.1. DMOS 8-3.2. LDMOS 8-3.3. VMOS and UMOS 8-3.4. MCT 8-3.5. IGBT i. IGBT Structures ii. IGBT Operation iii. IGBT I-V Characteristics iv. IGBT Circuit Models v. IGBT Switching Characteristics vi. IGBT Ratings Switching Performance of Power Devices Protection of Power Devices Packaging & Thermal Considerations Applications of Power Devices 8-7.1. Rectification (AC-DC Conversion) 8-7.2. Inverters (DC-AC Conversion) 8-7.3. Converters (DC-DC Conversion) 8-7.4. Cycloconverters (AC-AC Conversion) Comparison of Power Devices & Vacuum Tubes Summary Problems References

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Semiconductor Power Devices 8-1. Overview and Learning Objectives Power semiconductor devices are the heart of power electronic circuits. They have widespread applications in three major consumer markets: automotive, entertainment (locomotive) and in power supplies and regulators of household appliance. Engineers working in power electronics need a basic knowledge of power devices, their operation, capabilities and limitations. In this chapter, we summarize the operation concepts and limitations of the major power semiconductor devices. On completion of this Chapter, the student will be able to 1. Distinguish between, cut off, active, and saturation region operation of a power device. 2. Draw the input and output characteristics of a power device and explain their nature. 3. List the salient constructional features of a power device and explain their importance. 4. Draw the output characteristics of a power device and explain the applicable operating limits under Forward and Reverse bias conditions. Know the phenomena dominate the switching of power devices, Draw and explain the turn-on & turn-off characteristics of power devices, Interpret manufacturer datasheets and ratings of a power device, Differentiate between different packages of power device, Know how to design and make use of power semiconductor devices in basic applications of power electronics (e.g., rectifiers, inverters, and converters). 353 Prof. Dr. Muhammad El-SABA

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As shown in the following figure, the power semiconductor devices can be divided into two main categories based on number of terminals: twoterminal devices and three-terminal devices.

Fig. 8-1(a). Basic types of semiconductor power devices

Power devices can be also classified into bipolar-based devices (like power BJT and thyristors), and MOSFET-based devices (like Power MOSFET and DMOS). In addition, there exist a category of power devices which combines a bipolar transistor with a MOSFET (like IGBT). However, the bipolar power devices are the traditional power devices because of their capability to provide high currents and high blocking voltages. In this chapter, we present the fundamentals of these devices, with emphasis on their power ratings (breakdown voltage maximum current, safe operating area, etc) and switching characteristics. 354 Prof. Dr. Muhammad El-SABA

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8-2. Bipolar Power Devices The bipolar-based power devices include power diodes, power bipolar transistors, Darlington transistors, thyristors, which are also called silicon-controlled rectifiers (SRC) and triacs, a complementary thyristor structure suitable to control AC power. These power devices, however, are required to carry up to several Kilo Amperes of current under forward bias condition and block up to several Kilo Volts under reverse biased condition. These extreme requirements call for important structural changes in power devices, which significantly affect their operating characteristics.

Fig. 8-1(b). Trends of power Devices

8-2.1. Power PIN Diode The PIN diode is the same as a PN diode but with the addition of an intrinsic layer between the P- and the N-layers. As we have seen so far in Chapter 2, of this book, this intrinsic layer provides a high breakdown voltage capability of the device. The power versions of the PN junction diode have broad applicability in power electronics. Besides the usual breakdown voltage and high current capabilities, the other main consideration in selecting a PIN diode is their switching characteristics in general and their reverse recovery time in particular. Therefore, we content ourselves in this section to discuss these parameters, which are specific for the power version of PIN diodes. 355 Prof. Dr. Muhammad El-SABA

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i. Power PIN Structure The following figure shows the structure of PIN diode, which may be made of silicon or silicon carbide (SiC). The P-N junction is formed by defusing a heavily doped P+ region into an epitaxial N-layer, which is deposited on a heavily-doped N+substrate.. This P-type region acts as the anode and the N+ as cathode. Impurity atom densities in the heavily doped cathode and anode are approximately of the same order of magnitude (1019) while that of the epitaxial layer (also called the drift region) is lower by several orders of magnitude (10 14). This drift region withstands the depletion region in reverse bias and is flooded with carriers in high forward bias.

Fig. 8-2(a). Structure of a power PIN diode and one of its packages.

The PIN diode is usually fabricated with silicon technology. However, recent successful devices have been fabricated from SiC. The SiC is an IV–IV semiconductor and possesses many outstanding properties, such as wide bandgap, high breakdown electric field strength (approximately one order of magnitude higher than Si), high thermal conductivity, high saturation drift velocity, high thermal stability. These properties are attractive for high-power, high-frequency, and high-temperature applications. In fact, the SiC has a high electric field strength, so that the layer thickness of the active region of SiC power devices can be made thinner (by a factor of 10) than that of Si devices with a similar breakdown voltage. In addition, the doping level in the SiC layer can be made higher, by two orders of magnitude than that in Si. 356 Prof. Dr. Muhammad El-SABA

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Owing to the thinner base and higher doping level, a greatly reduced onresistance (by two orders of magnitude) can be realized to SiC compared to Si devices. ii. PIN Operation & I-V Characteristics In the following analysis, we assume a one-dimensional PIN structure, with homogenous doping in its three regions and abrupt junctions. We adopt the regional approach and assume constant transport parameters (carrier mobility, diffusion constant, and lifetime), in each quasi-neutral regions. In steady state, the voltage across the PIN diode is the sum of the junction voltage plus the i-region drop.

VAK = VP + VM + VN

(8-1)

Fig. 8-2(b). Doping profile of a power PIN diode.

The voltage drop across junctions and the forward current can be obtained by solving the continuity equation inside the drift region, where excess carriers defuse and recombine. As we'll see in the next paragraph, the spatial distribution of excess carrier concentrations (n and p) in the drift region is almost flat and several orders of magnitude higher than the thermal equilibrium carrier density of this region.. A. PIN in Forward Bias If we neglect recombination currents, the continuity equation in the drift region can be reduced to the following diffusion equation: 357 Prof. Dr. Muhammad El-SABA

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(8-2a)

where Da = Dp Dn /(Dp+Dn ) is the ambipolar diffusion constant and La= √(Dah) is the ambipolar diffusion length of charge carriers (electrons and holes) and is their lifetime at high level injection. The solution of this equation has the form:

(8-2b) After applying the boundary conditions of current continuity at both the PIN junctions, we can find the constants C1 and C22, such that the electron and hole concentrations become:

(8-2c)

with

(8-2d)

The following figure depicts the carrier concentration in the quasi-neutral regions of the PIN diode. Note that if the width of the drift region is less than the diffusion length of carries, the spatial distribution of excess carrier density in the drift region will be fairly flat and several orders of magnitude higher than the thermal equilibrium carrier density of this region.

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Fig. 8-3(a). Distribution of charge carriers in a power PIN diode, in forward bias.

The voltage drop components (Vn, Vp and Vm) can be found from the charge carrier and electric field distributions, as follows: (8-3a)

(8-3b) After substituting the boundary values n(±d), we get:

(8-3c)

As for the i-region drop, it can be found from the electric field, as follows:

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(8-4a) After substitution, we get:

(8-4b) The total current (J) can be also calculated from the carrier distribution (from the drift and diffusion components) as follows:

(8-5a) with

(8-5b)

The next figure (8-4) depicts the forward I-V characteristics of the PIN diode. The effect of recombination and carrier scattering on the carrier distribution is depicted on the same figure. The following figure shows the forward I-V characteristics of a real silicon PIN diode at 25C.

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Fig. 8-3(b). Forward I-V characteristics of a PIN diode, according to the above analysis and taking the recombination and scattering effects into account.

Fig. 8-3(c). Forward I-V characteristics of a PIN diode.

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B. PIN Operation in Reverse Bias The applied reverse voltage is supported by the depletion layer formed at the P-N metallurgical junction. The depletion layer spans the entire drift region and is in contact with the cathode. However, due to very large doping density of the cathode, penetration of drift region inside cathode is negligible. Electric field strength inside the drift region of both these type of diodes at break down voltage is shown in figure 8-3. The DC blocking voltage (VB) is the maximum direct voltage that can be applied in the reverse direction across the device for indefinite period of time. Under reverse bias condition only a small leakage current (less than 100mA for a rated forward current in excess of 1kA) flows in the reverse direction.

Fig. 8-4. Electric field distribution across a power PIN diode.

Remember that the critical electric field for breakdown (C) in Si is given by:

C (Si) = 4010 ND1.8 From the geometry of the depletion region, the corresponding punchthrough breakdown voltage for the drift region is then:

VB = C WD - ½ eNDWD2/s

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Fig. 8-5. Variation of the reverse current a PIN diode with ambient temperature, at 25V reverse bias..

ii. PIN Switching Characteristics Power Diodes take finite time to make transition from reverse bias to forward bias condition (switch ON) and vice versa (switch OFF). Behavior of the diode current and voltage during these switching periods are important due to the following reasons. Severe overvoltage /overcurrent may happen during diode switching. Voltage and current exist simultaneously during switching operation of a diode. Therefore, every switching of the diode is associated with energy losses. At high switching frequencies this may contribute significantly to diode heating and eventual damage.

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(a)

Chapter 8

(b)

Fig. 8-6. Switching characteristics of a PIN diode. Both turn-on (Left) and Turn-off (right) voltages and current waveforms are shown..

PIN diodes are often used in circuits with di/dt limiting inductors. The rate of rise of the forward current through the diode during turn-on has significant effect on the forward voltage drop characteristics. A typical turn-on transient is shown in figure 8-5(a). This is a typical turn-on behavior of a power diode assuming controlled rate of decrease of the forward current. It is observed that the forward diode voltage during turnon may reach a high value (Vfr) compared to the steady slate value. In some power converter circuits, where a freewheeling diode is used across an asymmetrical blocking power switch this transient over voltage may be high enough to destroy the main power device. The so-called forward recovery voltage (Vfr) is given as a function of the forward di/dt in the manufacturer’s data sheet. Typical values lie within the range of 10-30V. Forward recovery time (tfr) is typically within 10us. Figure 8-5(b) shows a typical turn-off behavior of a power diode assuming controlled rate of decrease of the forward current As shown in the above figure, the switching characteristics of the PIN diode have the following features:  The diode current does not stop at zero, instead it grows in the negative direction to a peak reverse recovery current (Irr), which can be comparable to IF. 364 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 8

 In many power electronic circuits, this reverse current flows through the main power switch in addition to the load current. Therefore, this reverse recovery current has to be taken into account when selecting the switching device.  Voltage drop across the diode does not change appreciably from its steady state value till the diode current reaches reverse recovery level. In many power electric circuits this may create an effective short circuit across the supply. Also in high frequency switching circuits (like SMPS), if the time period td is comparable to switching cycle qualitative modification to the circuit behavior is possible.  Towards the end of the reverse recovery period if the reverse current falls too sharply, stray circuit inductance may cause dangerous over voltage (Vrr) across the device. It may be required to protect the diode using a snubber RC network. During the period ts large current and voltage exist simultaneously in the device. At high switching frequency this may result in considerable increase in the total power loss. Important parameters defining the turn off characteristics are, peak reverse recovery current (Irr), reverse recovery time (trr), reverse recovery charge (Qrr) and the dI/dt rate. The dI/dt rate (sometimes, called the snappiness factor S) depends mainly on the structure of the diode (drift region width, doping lever, carrier lifetime). Other parameters are interrelated and also depend on S. Manufacturers usually specify these parameters as functions of dIF/dt for different values of IF. Both Irr and Qrr increases with IF and dIF/dt while trr increases with IF and decreases with dIF/dt.

365 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Chapter 8

8-2.2. Power BJT High power bipolar transistors are conceptually similar to usual bipolar transistors, we presented in chapter 3. The main difference is that the active area of the device is higher, resulting in a much higher current handling capability. The following figure shows some of the famous packages of power BJT's. Power BJTs also have a thick and low-doped collector region with extremely low doping, down to 1013 cm-3, to obtain blocking voltages as large as 10kV. As a result, one finds that the structure needs to be redesigned to manage the power losses and to avoid the current crowding and Kirk effects.

Fig. 8-7. Photographs of some packages of power BJT's

i. Safe Operating Area of a Power BJT The following figure shows the typical output characteristics (IC versus VCE) of an NPN power BJT. A power BJT exhibits Cutoff, Active and Saturation regions in its output characteristics similar to a small-signal BJT. In fact output characteristics of a Power BJT in the Cutoff and Active regions are qualitatively identical to a signal level transistor. In the cut off region (IB ≤ 0) the collector current is almost zero. The maximum voltage between collector and emitter under this condition is termed maximum forward blocking voltage with open base (IB =0) and is denoted by VCEO. For all practical purpose this is the maximum voltage that can be applied in the forward direction across a power transistor. This blocking voltage can however be increased to a value VCBO by keeping the emitter terminal open. In this case IB [substrate node] [area value] Examples Q1 14 2 13 PNPNOM Q13 15 3 0 1 NPNSTRONG 1.5 Q7 VC 5 12 [SUB] LATPNP Model Form .MODEL NPN [model parameters] .MODEL PNP [model parameters] .MODEL LPNP [model parameters] Arguments and Options [substrate node] is optional, and if not specified, the default is the ground. [area value] is the relative device area and has a default value of 1. Description The bipolar transistor is modeled as an intrinsic transistor using ohmic resistances in series with the collector (RC/area), with the base (value varies with current, see Bipolar Transistor Equations), and with the emitter (RE/area).

639 Prof. Dr. Muhammad El-SABA

Microelectronic & Nanoelectronic Devices

Appendix

Table D-1. BJT model parameters PARAMETERS AF BF BR CJC CJE farad CJS (CCS) EG FC GAMMA IKF (IK) IKR IRB IS ISC (C4) ISE (C2) ISS ITF KF MJC (MC) MJE (ME) MJS (MS)

DESCRIPTION flicker noise exponent ideal maximum forward beta ideal maximum reverse beta base-collector zero-bias p-n capacitance base-emitter zero-bias p-n capacitance substrate zero-bias p-n capacitance bandgap voltage (barrier height) forward-bias depletion capacitor coefficient epitaxial region doping factor corner for forward-beta highcurrent roll-off corner for reverse-beta highcurrent roll-off current at which Rb falls halfway to transport saturation current base-collector leakage saturation current base-emitter leakage saturation current substrate p-n saturation current transit time dependency on Ic flicker noise coefficient base-collector p-n grading factor base-emitter p-n grading factor substrate p-n grading factor

640 Prof. Dr. Muhammad El-SABA

UNITS DEFAULT 1.0 100. 1.0 farad 0.0 0.0 farad

0.0

eV

1.11 0.5

amp

1E-11 infinite

amp

infinite

amp

infinite

amp amp

1E-16 0.0

amp

0.0

amp

0.0

amp

0.0 0.0 0.33 0.33 0.0

Microelectronic & Nanoelectronic Devices PARAMETERS NC NE NF NK NR NS PTF QCO RB RBM RC RCO RE TF TR TRB1 TRB2 TRC1 TRC2 TRE1 TRE2 TRM1 TRM2

DESCRIPTION base-collector leakage emission coefficient base-emitter leakage emission coefficient forward current emission coefficient high-current roll-off coefficient reverse current emission coefficient substrate p-n emission coefficient excess phase @ 1/(2·TF) epitaxial region charge factor zero-bias (maximum) base resistance minimum base resistance collector ohmic resistance epitaxial region resistance emitter ohmic resistance ideal forward transit time ideal reverse transit time RB temperature coefficient (linear) RB temperature coefficient (quadratic) RC temperature coefficient (linear) RC temperature coefficient (quadratic) RE temperature coefficient (linear) RE temperature coefficient (quadratic) RBM temperature coefficient (linear) RBM temperature coefficient (quadratic) 641

Prof. Dr. Muhammad El-SABA

Appendix UNITS

DEFAULT 2.0 1.5 1.0 0.5 1.0 1.0

degree 0.0 coulomb ohm

0.0

ohm ohm ohm ohm sec sec °C-1

RB 0.0 0.0 0.0 0.0 0.0 0.0

°C-2

0.0

°C-1

0.0

°C-2

0.0

°C-1

0.0

°C-2

0.0

°C-1

0.0

°C-2

0.0

Microelectronic & Nanoelectronic Devices PARAMETERS T_ABS T_MEASURED T_REL_GLOBAL T_REL_LOCAL VAF (VA) VAR (VB) VJC (PC) VJE (PE) VJS (PS) VO VTF XCJC XCJC2 XTB XTF XTI (PT)

DESCRIPTION absolute temperature measured temperature relative to current temperature relative to AKO model temperature forward Early voltage reverse Early voltage base-collector built-in potential base-emitter built-in potential substrate p-n built-in potential carrier mobility knee voltage transit time dependency on Vbc fraction of CJC connected internally to Rb fraction of CJC connected internally to Rb forward and reverse beta temperature coefficient transit time bias dependence coefficient IS temperature effect exponent

642 Prof. Dr. Muhammad El-SABA

Appendix UNITS °C °C °C

DEFAULT

°C volt volt volt

infinite infinite 0.75

volt

0.75

volt

0.75

volt volt

10.0 infinite 1.0 1.0 0.0 0.0 3.0

Microelectronic & Nanoelectronic Devices

Appendix

APPENDIX E : SPICE Model of MOSFET General Form: M + + [L=] [W=] + [AD=] [AS=] + [PD=] [PS=] + [NRD=] [NRS=] + [NRG=] [NRB=] + [M=] Examples M1 14 2 13 0 PNOM L=25u W=12u M13 15 3 0 0 PSTRONG M16 17 3 0 0 PSTRONG M=2 M28 0 2 100 100 NWEAK L=33u W=12u AD=288p AS=288p + PD=60u PS=60u NRD=14 NRS=24 NRG=10 Model Form .MODEL NMOS [model parameters] .MODEL PMOS [model parameters] Description The MOSFET is modeled as an intrinsic MOSFET using ohmic resistances in series with the drain, source, gate, and bulk (substrate). There is also a shunt resistance (RDS) in parallel with the drain-source channel The simulator provides six MOSFET device models, which differ in the formulation of the I-V characteristic. The LEVEL parameter selects between different models as follows. LEVEL=1 Shichman-Hodges model (see reference [1]) LEVEL=2 geometry-based, analytic model (see reference [2]) LEVEL=3 semi-empirical, short-channel model (see reference [2]) LEVEL=4 BSIM model (see reference [3]) LEVEL=5 (No longer supported.) LEVEL=6 BSIM3 model version 2.0 (see reference [7]) LEVEL=7 BSIM3 model version 3.0 (see reference [8])

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Microelectronic & Nanoelectronic Devices

Appendix

Table E-1. MOSFET model parameters Parameter AF CBD CBS CGBO CGDO CGSO CJ CJSW FC GDSNOI

Description flicker noise exponent zero-bias bulk-drain p-n capacitance zero-bias bulk-source p-n capacitance gate-bulk overlap capacitance/channel length gate-drain overlap capacitance/channel width gate-source overlap capacitance/channel width bulk p-n zero-bias bottom capacitance/area bulk p-n zero-bias sidewall capacitance/length bulk p-n forward-bias capacitance coefficient channel shot noise coefficient (use with NLEV=3) 644

Prof. Dr. Muhammad El-SABA

Unit farad

Default 1 0

farad

0

farad/meter

0

farad/meter

0

farad/meter

0

farad/meter2 0 farad/meter

0 0.5 1

Microelectronic & Nanoelectronic Devices Parameter IS JS JSSW KF L LEVEL MJ MJSW N NLEV PB PBSW RB RD RDS RG RS RSH TT

Description bulk p-n saturation current bulk p-n saturation current/area bulk p-n saturation sidewall current/length flicker noise coefficient channel length model index bulk p-n bottom grading coefficient bulk p-n sidewall grading coefficient bulk p-n emission coefficient noise equation selector bulk p-n bottom potential bulk p-n sidewall potential bulk ohmic resistance drain ohmic resistance drain-source shunt resistance gate ohmic resistance source ohmic resistance drain, source sheet resistance bulk p-n transit time

645 Prof. Dr. Muhammad El-SABA

Appendix Unit amp amp/meter2

Default 1E-14 0

amp/meter

0

meter

0 DEFL 1 0.5 0.33

volt volt ohm ohm ohm ohm ohm ohm/square sec

1 2 0.8 PB 0 0 infinite 0 0 0 0

Microelectronic & Nanoelectronic Devices

646 Prof. Dr. Muhammad El-SABA

Appendix

Microelectronic & Nanoelectronic Devices

Appendix

APPENDIX F : SPICE Model of IGBT General Form Z