Electrothermal Issues in 4H-SiC 600 V Schottky

Materials Science Forum Vols. 527-529 (2006) pp. 1151-1154 online at http://www.scientific.net © (2006) Trans Tech Publications, Switzerland

Electrothermal Issues in 4H-SiC 600 V Schottky Diodes in Forward Mode: Experimental Characterization, Numerical Simulations and Analytical Modeling Andrea Irace1,a, Vincenzo d’Alessandro1,b, Giovanni Breglio1,c, Paolo Spirito1,d, Andrea Bricconi2,e, Rossano Carta2,f, Diego Raffo2,g, and Luigi Merlin2,h 1

Department of Electronics and Telecommunications Engineering, University of Naples “Federico II”, via Claudio 21, 80125 Naples, Italy Tel: 0039-081-7683116 (3509; 3128; 3138). Fax: 0039-081-5934448. 2

IRCI-International Rectifier Corporation Italia, via Liguria 29, 10071 Borgaro T.se, Turin, Italy Tel: 0039-011-4510354. Fax: 0039-011-4510220. a

[email protected], b [email protected], c [email protected], d [email protected], [email protected], f [email protected], g [email protected], h [email protected]

e

Keywords: Schottky diodes, voltage surge, electrothermal simulations, thermal resistance

Abstract. The electrothermal behavior of 4H-SiC 600 V Schottky diodes operated in forward mode is analyzed through numerical and analytically-based simulations. It is shown that the unexpected occurrence of voltage surges systematically detected in state-of-the-art devices is a thermally-induced effect due to the compound contribution of a) the negative temperature coefficient of the forward current at high voltages and b) the relatively high package-to-ambient thermal resistance. As a main result, it is demonstrated that the proposed approaches are suitable to accurately predict the value of a “critical” current density beyond which voltage surges may arise. Introduction Due to their inherent features like high thermal conductivity, reduced switching losses, large breakdown voltages, and low volume/weight, SiC Schottky diodes are starting to be used in some applications, such as inverters/converters and motor drives [1,2]. However, despite the common belief of a relevant immunity to all kinds of breakdown phenomena, some last-generation 4H-SiC 600 V Schottky diodes have systematically shown a detrimental voltage surge effect when biased in forward mode with an assigned anode current not much larger than the nominal value. Fig. 1 shows the voltage drop measured by applying 6 ms-long current pulses of different amplitudes to a state-of-the-art device. As can be seen, the voltage surges arise at current levels exceeding a threshold value that amounts to about 11×102 A/cm2. In this case, the device failure is circumvented by the power supply limitation of the measurement circuitry. This contribution details a twofold approach devised to thoroughly analyze the above mechanism. The first one is based on the adoption of a commercial numerical simulator, whilst the second is centered on a newly-developed analytical device model. Both techniques are properly calibrated through comparison with experimental data obtained under isothermal (pulsed) conditions. Nonisothermal simulations clearly demonstrate the electrothermal nature of the voltage surges. Lastly, alternative technological solutions to minimize such effects are investigated through the supplementary aid of a 3-D thermal simulation tool. Numerical approach Although nowadays SiC devices are conquering a noteworthy space in the power electronics arena, most commercially available device simulators still are at an early stage in modeling the basic physical SiC parameters, while being perfectly tailored for Si devices. In this scenario, one adopted simulation

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approach lies in enhancing the potential of existing tools through calibration based on experimental results [3]. Following such a philosophy, we decided to resort to the widespread software ATLAS by Silvaco [4], which includes a SiC module. First, we have activated all the models describing the key physical quantities (i.e., intrinsic carrier concentration, band-gap, anisotropic carrier mobility and its temperature dependence, saturation velocity, impact-ionization, etc.) proposed in the recent literature on the basis of experimental data and/or Monte Carlo simulations (see e.g., [5-7]). The parameters of each model have been set in accordance to the values extracted in such works as a “first attempt” solution. Furthermore, the value of 5.4 eV for the metal workfunction was chosen to obtain the experimentally evaluated barrier height (i.e., 1.28 eV). Second, we have properly adjusted some parameter values by comparing the forward J–V characteristics obtained by ATLAS and those measured under isothermal conditions at various temperatures. Fig. 2 illustrates the favorable agreement achieved after the calibration process. Inspection of such a figure plainly shows that the positive temperature coefficient (PTC) of the forward current due to the thermionic emission effect is replaced by a negative temperature coefficient (NTC) at high current levels, where the series resistance of the N-drift layer dominates the overall behavior (see e.g., [8]). The low-current PTC region (grey inset of Fig. 2) is represented in Fig. 3, which reports isothermally measured J–V curves at various temperatures. 2

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Fig. 5. Analytical model (continuous lines) compared to experimental results (symbols): isothermal J-V characteristics in forward mode. Note that A=0.97 V, B=1.5×10-3 V/K, and µn(T)=µn(T0)(T/T0)-2.5.

Analytical modeling As an effective alternative to numerical simulations, we have developed a physically-based analytical model, which relates the ON voltage drop to the applied forward current at an assigned temperature. The temperature dependence of the relevant parameters involved has been determined via experimental characterization at low currents (@ 1 A/cm2 for the voltage drop, left axis of Fig. 4) and high currents (@ 4×102 A/cm2 for the ON resistance, right axis of Fig. 4). The model takes the following form: VON (T , J )= A - B ×D T + RON (T )× f (J ).

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Note that the function f(J) can be simply equated to Adiode·J for an acceptable description of the region just beyond the transition PTC–NTC (i.e., the range 4–7×102 A/cm2); conversely, a polynomial law is to be considered at high current levels, where the saturation of carrier velocity reduces the J–V slope. RON(T) is expressed as tepi/qNepiμn(T)Adiode. The comparison between experimental results (symbols) and model (solid lines) at various temperatures is illustrated in Fig. 5. Simulation results and discussion Once ATLAS and the electrothermal analytical model have been properly tuned on experimental isothermal data, the non-isothermal steady-state behavior of a device mounted in a TO247 package has been simulated through both the above strategies. The thermal resistance to be adopted as an input has been obtained from measurements, and equals 2.5 K/W. Such a value has been accounted for in ATLAS by properly choosing the distributed thermal resistance that can be exploited as a boundary condition for the thermal problem. In the analytically-based approach, the current-temperature feedback has been numerically included by means of the thermal equivalent of the Ohm’s law. Fig. 6 shows the model characteristic (solid line) along with the ATLAS curve (dashed). Some considerations are in order: i) the results obtained through the proposed procedures are in excellent agreement; ii) it is clarified that the voltage surge mechanisms are induced by thermal effects. Indeed, it is clear that, under non-isothermal conditions, the aforementioned NTC behavior leads to an undesired current “saturation” at about 11×102 A/cm2, thereby limiting the region where the diode can safely operate to this “critical” value. Hence, the voltage surges shown in Fig. 1 for J>11×102 A/cm2 are caused by the lack of a stable equilibrium point. Both simulation approaches can be also adopted for analyzing alternative technological strategies, whose target is the “critical” current increase via a RTH lowering. The “thermal scheme” of the tested

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Fig. 7. Schematic thermal representation of both the standard (a) and flipped (b) device.

diode is depicted in Fig. 7a, which shows that the heat generation region is located in the close proximity of the top surface of a 300 µm-thick 4H-SiC chip. The package contribution RTH,PKG to the overall thermal resistance RTH is actually an unknown. A possible solution that is being investigated for reducing RTH is represented by flipping the chip (see Fig. 7b), that is, mounting the anode in intimate contact with the package. In order to evaluate the resulting RTH, we have resorted to the following approach. First, we have drawn the complete 3-D structure corresponding to the scheme in Fig. 7a in FEMLAB [9] environment. Subsequently, we have assigned the literature value of 3.7×10-4 W/µmK to the thermal conductivity of the 4H-SiC chip, and we have calibrated the thermal properties of the package so as to obtain the experimental RTH=2.5 K/W via thermal simulation. Finally, we have simulated by FEMLAB the 3-D structure with the chip flipped. As a result, we have attained RTH=1.86 K/W, thus demonstrating that RTH,PKG actually dominates the electrothermal device behavior. Consequently, the thermal robustness improvement due to such a strategy is not significant, as evidenced by the simulated J–V characteristic under non-isothermal conditions with RTH=1.86 K/W (see Fig. 6). In particular, it is seen that the “critical” current increase amounts to only 12%. Summary In this paper, two simulation strategies for the analysis of 4H-SiC Schottky diodes have been proposed, namely an enhancement of a commercial 2-D device simulator and the development of an in-house tool based on an analytical model. It is demonstrated that undesirable voltage surges systematically occurring in current-controlled 600 V devices are due to a thermally-induced absence of stable equilibrium points. Such codes allow a fast and reliable diagnostic of the device behavior, and can be also adopted to predict the effectiveness of technological solutions directed toward the Safe Operating Area enlargement. References [1] C. E. Weitzel et al.: IEEE Trans. on Electron Devices, Vol. 43, 10, (1996), p. 1732. [2] D. T. Morisette et al.: IEEE Trans. on Electron Devices, Vol. 48, 2, (2001), p. 349. [3] M. C. Tarplee et al.: IEEE Trans. on Electron Devices, Vol. 48, 12, (2001), p. 2659. [4] ATLAS user’s manual, Silvaco International, (2002). [5] M. Lades and G. Wachutka: Proc. IEEE SISPAD, (1997), p. 169. [6] M. Roschke and F. Schwierz: IEEE Trans. on Electron Devices, Vol. 48, 7, (2001), p. 1442. [7] K. Bertilsson et al.: Solid-State Electronics, Vol. 48, (2004), p. 2103. [8] R. Raghunathan et al.: IEEE Electron Device Letters, Vol. 16, 6, (1995), p. 226. [9] FEMLAB reference manual, Comsol AB, (2003).