Embedded Systems Design - Eurosfaire

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Unit G3: Embedded Systems and Control .... design of embedded systems for complex and demanding ..... There are fundamental research problems that need .
Embedded Systems Design

••• Portfolio of FP7 projects Dir. G: Components and Systems Unit G3: Embedded Systems and Control

LEGAL NOTICE By the Commission of the European Union, Information Society & Media Directorate-General, Software & Service Architectures and Infrastructures Unit. Neither the European Commission nor any person acting on its behalf is responsible for the use which might be made of the information contained in the present publication. The European Commission is not responsible for the external web sites referred to in the present publication. The views expressed in this publication are those of the authors and do not necessarily reflect the official European Commission’s view on the subject.

More information on the European Union is available on the Internet (http://europa.eu). Cataloguing data can be found at the end of this publication. Luxembourg: Publications Office of the European Union, 2010 ISBN 978-92-79-16409-5 doi:10.2759/35125 © European Union, 2010 Reproduction is authorised provided the source is acknowledged. Printed in Belgium PRINTED ON RECYCLED PAPER

Embedded Systems Design

••• Portfolio of FP7 projects Dir. G: Components and Systems Unit G3: Embedded Systems and Control

Table of contents

ACTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ADAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ALL-TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ARCADIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ArtistDesign. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 COCONUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 COMBEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 COMPLEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 COSINE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DESTECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 EMBOCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ENOSYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ERA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 GALAXY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INTERESTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MADES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MADNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MEDEIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MNEMEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MOBY-DIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MOGENTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

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MULTICUBE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PREDATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PROARTIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ProSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Quasimodo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SATURN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TERESA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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Embedded Systems Design

This brochure contains an overview of our projects

STREPsSpecific Research Projects: ACTORS ALL-TIMES COCONUT COMBEST COMPLEX DESTECS EMBOCON ENOSYS ERA GALAXY MADES MADNESS MEDEIA MNEMEE MOBY-DIC MOGENTES MULTICUBE PREDATOR PROARTIS Quasimodo SATURN TERESA

Targeted

IPs- Integrated Projects: COMPLEX INTERESTED

For further information: European Commission - Information Society and Media DG Directorate G – Components and Systems Unit G3 – Embedded Systems and Control Office: BU31 05/03 B-1049 Brussels Email: [email protected] Tel: +32 2 296 64 07 Fax: +32 2 296 83 89 http://europa.eu/information_society

CSA- Coordination and Support Action: ADAMS ARCADIA COSINE2 ProSE

NoE- Network of Excellence: ArtistDesign

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Embedded Systems Design RESEARCH PROJECTS

ACTORS Adaptivity and Control of Resources in Embedded Systems KEYWORDS: Adaptivity, Resource Management, Reservation based scheduling, MPEG, Data flow modeling, Code generation, FPGA Main Objectives

At A Glance: ACTORS Adaptivity and Control of Resources in Embedded Systems

Project Coordinator/ Technical Manager: Name: Johan Eker Institution: Ericsson AB Email: [email protected] Project website: www.actors-project.eu Partners: Ericsson AB (Sweden) Scuola Superiore Sant’ Anna (Italy) Technische Universität Kaiserslautern (Germany) Evidence S.r.l. (Italy) Ecole Polytechnique Fédérale de Lausanne (Switzerland) Lund University (Sweden) AKAtech SA. Duration: 36 months Start: 2008.02.01 Total Cost: 3412454 € EC Contribution: 2479214€ Contract Number: INFSO-ICT- 216586

ACTORS addresses the challenging problem of efficient design of embedded systems for complex and demanding high-performance applications. The project approach is to raise the abstraction level of the project approach is to raise the abstraction level of the specifications and computing models, to include resource-constrained design exploration stages and real- time resource adaptation by developing the appropriate models and tools supporting the design from the specification down to the embedded implementation. Three main innovative technologies will be employed: high level dataflow specification and programming models for design space exploration, virtualization and feedback-based resource scheduling. The targeted execution platforms are Linux-based multiprocessor/multicore systems and FPGAs. Three design cases will be developed to validate and demonstrate the new approach: multimedia processing on cellular phone terminals, embedded control, and high-performance video systems. ACTORS focus on The ACTORS consortium is design of adaptive led by Ericsson. It contains and efficient realtwo SMEs (AKAtech and time applications Evidence) and four university for multicore beneficiaries (SSSA, TUKL, hardware using ULUND, and EPFL). data flow tools and Associated partner to the methodologies. project is Xilinx, US.

Key Issues The project is based on a set of main observations and ideas: x Embedded systems are vital to Europe's industry and society. In parallel with miniaturization and the necessity to handle severely resource-constrained implementation platforms, the functionality and complexity of large classes of embedded systems continue to increase making them from many respects comparable to ordinary desktop PCs. A mixture of different types of timing, application driven QoS constraints and the migration to the new generation of multi-core and SoC platforms make overall system architecture design, resource allocation and scheduling more important and challenging topics than ever before.

COOPERATION

European Commission Information Society and Media

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x

x

x

x

While the success of Si CMOS scaling has been the main driving force for performance progress of embedded systems in the last 30 years, it has at the same time practically restricted the way system specification SW development, HW design and all related tools and formalisms have evolved so far. No common formalism, language or design methodology is available to map concurrency and parallelism for embedded SW and HW from the specification level down through all the different levels of abstractions to final system design/implementation. A radical change in necessary in order to master the complexity of future generations of embedded systems and to utilize the possibilities of new multicore platforms. Parallelism and resource allocation must be included in the design flow from the very beginning. A unified approach is required that combines ideas from computer science, control systems, and electronic engineering. Execution efficiency as well development efficiency requires abstractions on a higher level than what is provided with C and threads/priorities. For a large class of embedded system applications including feedback control, signal processing and multimedia streaming and processing, dataflow models and dataflow languages, in particular actor languages have superior properties. Actors provides the proper foundation for implementation of efficient, component based, parallel and adaptive algorithms for both media applications in embedded consumer electronics and embedded control and signal processing applications. Virtualization techniques such as reservation-based scheduling is a very good way of providing temporal and spatial isolation between different functions and, hence improve dependability, predictability, composability, security and development productivity for embedded systems. Important research advances have been made in the area, which ACTORS will build upon, but much remains before this becomes industrial practice. Adaptivity to changes and uncertainties in resource requirements, objectives, external conditions and use cases is a necessity in large classes of embedded systems. This requires a unification of approaches from computer science and control. Adaptivity and virtualization is a natural match. Control techniques can be used globally to dynamically adapt the reservation budgets to changes, as well as locally, within each reservation to adjust the resource requirements.

CPU reservation #1

CPU reservation #2

CPU reservation #3

Resource Manager RBS Kernel

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Technical Approach The project consists of three fundamental components: x Data-flow programming using actors o Actor programming is suitable for applications that perform sequential operations on data (signal processing, control, media processing, etc), i.e. operate on streams. o Actors are implemented using the CAL Actor Language and the OpenDF compilation and simulation framework. CAL is part of coming MPEG RVC standard. o Actors provide a programming model that is well suited for building components that are parametric in resource requirements Æ enable adaptivity o The design of the CAL Actor Language allows for generation of efficient code. o Actors is the fundamental user level component x Feedback based resource management o Distribute resources based on execution conditions and application requirements o Will allow for dynamic, yet predictable, system behavior o Based on control theory x Reservation based scheduling o Provide a logical abstraction layer for distribution of system resources o Fundamental mechanism for distributing resources among applications o Extend and improve current implementation available in the main line Linux kernel

Expected Impact The project will show how to build flexible and efficient system using dataflow technologies. The resulting systems will be robust due to the underlying feedback based resource management. Project members work closely with the MPEG standardization body on tools and methodologies for data flow programming. The work on scheduling will be done with the explicit goal of acceptance of the open source community. All developed software will, as far as possible, be made available as free open source, and this includes compilers and runtimes for the CAL actor language. Our intention is to through a set of powerful use cases and a working, free tool-chain demonstrate the superiority of our approach.

Embedded Systems Design COORDINATION AND SUPPORT ACTION

ADAMS Action for the Dissemination and Adoption of the MARTE and related Standards for component based middleware The ADAMS project aims at promoting the usage of the MARTE standard for the development of real-time and embedded systems using both model and component design paradigms. KEYWORDS: UML, MARTE, MDE/MDD, real-time and embedded applications, component-based design. Main Objectives At A Glance: ADAMS Action for the Dissemination and Adoption of the MARTE and related Standards for component based middleware

Project Coordinator: Name: Dr. Sébastien Gérard Institution: CEA LIST Email: [email protected] Project website: www.adams-project.org Partners: Commissariat à l’Energie Atomique (France) THALES Group (France) Universidad de Cantabria (Spain) Volvo Technology Corporation (Sweden) Duration: 24 months Start: 2008-05-01 Total Cost: € 300000 EC Contribution: € 300000 Contract Number: Grant agreement n°224330

The recent adoption of the UML MARTE standard is a great success issued from an intensive work launched four years ago by THALES, CEA LIST and INRIA and supported by a large international and representative consortium including important tool editors (ARTISAN, IBM/Rational/ Telelogic/I-Logix, MathWorks, Mentor Graphics…), users (Alcatel-Lucent, France Telecom, Loocked-Martin, THALES…) and academics (CEA LIST, INRIA, SEI/Carnegie Mellon Univ., Univ. Cantabria, Univ. Carleton…). ADAMS will focus on In parallel we observe an promoting the usage intense activity in embedded of the OMG’s MARTE domains, in particular for standard for MDD in automotive and avionics, to both avionics and standardise and deploy automotive domains. component-based middleware technologies. These activities are by essence strongly linked to the modelling approaches, in particular regarding architecture descriptions and non-functional requirements. The two domains automotive and avionics have developed their own specification and execution platform standards (AADL, ARINC, AUTOSAR, EASTADL2, OSEK…) and are looking to integrate some other related approaches such as LwCCM or UML/SysML profiles with particular interests on nonfunctional property descriptions (this covers, namely, resource, timing, and safety requirements). Interfaces to these standards have already been proposed and defined in MARTE. However, the knowledge of MARTE in the embedded community, both on industry and on academia side, is not sufficient to ensure a good level of understanding of its capacities and its use. The objective of ADAMS is thus to trigger the knowledge dissemination by exploiting MARTE in industrial practice amongst others by restructuring or refining MARTE methods and tools based on feedback from practice.

COOPERATION

European Commission Information Society and Media

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Technical Approach Several projects have been and are being launched to enhance, evaluate, and demonstrate the benefits of MARTE and other standards. The analysis of the ADAMS partners is that the current entering point for ensuring successful deployment of the MARTE standard is a focussed effort to disseminate knowledge on MARTE and to coordinate feedback and update proposition on MARTE from the practice. This is why the instrument chosen to push the dissemination of MARTE was “Support Action”. By structuring the ADAMS project around the two target industrial domains, automotive and avionics, the ADAMS project will more specifically commit itself to achieve its objectives. The main objective of ADAMS is to favour the exploitation of the MARTE standard in domains having requirements similar to those that have triggered the standard elaboration process four years ago. Two domains are particularly active to standardize modelling approaches and deploy them on component-based middleware technologies: automotive and avionics. They share a large set of requirements with MARTE and thus are particularly relevant for focused dissemination and critical analysis of the current standard version. In addition, ADAMS will work on promoting MARTE on the one hand to the whole embedded systems community. On the other hand, ADAMS will also use all developed results to influence the related standardisation bodies, in order to close the feedback loop by organizing and delivering the feedback gathered from the automotive and avionics domains in the form of recommendation actions towards both OMG for MARTE evolution and domain initiatives and standards for convergence and evolution towards MARTE. To ensure a pertinent dissemination to both automotive and avionics domains, the specific work performed within ADAMS is organised around two working groups of experts from the corresponding domain. These working groups will deal with the concerns of the three following technical points of view: x The ways to specify non-functional properties. x The ways to describe application architecture and deployment. x The ways to specify the execution and communication infrastructure (middleware & OS). Project organisation for both working groups will be similar as denoted in following picture:

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Continental Corporation Support for extern analysis WP2 - MARTE and automotive domain

Non Functional Properties Point of view

EAST-ADL2

AUTOSAR (OSEK)

Architecture description Point of view

Execution infrastructure Point of view

MARTE SAE-AADL

IMA, ARINC

WP3 - MARTE and avionics domain Support for extern analysis Airbus

Key Issues MARTE has been a great success resulting mainly from a European initiative. The challenge now is to disseminate and promote its adoption through the European industry and trigger enhancements reflecting the practitioners’ needs. This is valuable for Europe due to its very strong economic activity in development of embedded, real time and distributed systems. Key point for its adoption is to demonstrate and convince about its conformance, usability and efficiency to deal with current middleware technologies used by the embedded system industry, and adapt it as necessary to related standards of the automotive and avionics domain (strongly structured, respectively, on AUTOSAR, EAST-ADL2, IMA/ARINC, and SAE-AADL).

Expected Impact The emergence and dissemination of high quality standards supporting modelling, design and deployment of embedded systems software is a key factor for the emergence of new services as well as cross domain products and solutions. As such, the MARTE OMG standard has the potential to support and standardize future embedded systems design flows and middleware for several application domains, especially automotive and avionics. By being proactive in the dissemination and feedback gathering of MARTE through a series of concrete tasks as indicated above in the work-package description, the ADAMS project will effectively contribute to deliver the value of the MARTE standard.

Embedded Systems Design RESEARCH PROJECTS

ALL-TIMES Integrating European Timing Analysis Technology The ALL-TIMES aims at interoperability of tools from SMEs and universities, and integrated tool chains using open tool frameworks and interfaces and thus an increase the productivity of embedded systems development projects by 25% KEYWORDS: timing analysis, WCET, worst case execution time, timing tools, integrated tool chains, scheduling analysis Main Objectives

At A Glance: ALL-TIMES Integrating European Timing Analysis Technology

Project Coordinator: Name: Björn Lisper Institution: Mälardalen University Email: [email protected] Project website: www.ICT-ALL-TIMES.eu Partners: AbsInt Angewandte Informatik GmbH (Germany) Vienna University of Technology (Austria) Gliwa GmbH (Germany) Symtavision GmbH (Germany) Rapita Systems Ltd (UK) Duration: 27 months Start: 2007-11-01 Total Cost: € 2 094 492 EC Contribution: € 1 600 000 Contract Number: INFSO-ICT-215068

The ALL-TIMES project aims at combining and developing research results and timing tools currently available and thus to strengthen the European lead in the timing analysis area. The ALL-TIMES project will enable interoperability of tools from SMEs and universities, and develop integrated tool chains using open tool frameworks and interfaces. By combining research results and commercial tools, ALL-TIMES will ensure the flow of ideas from basic research to practice. The two principal project objectives are: ALL-TIMES will focus x Integration of timing on combining and analysis tools developing research x Increase of productivity results and timing of embedded systems tools currently development projects by available and thus to 25% of the design time strengthen the pertaining to timing European lead in the issues timing analysis area. One of the overall objectives of the project is the provision of new integrated toolsets for timing analysis targeted at the embedded real-time systems market. This relates to the advancement of new analysis techniques for integrated scheduling analysis, WCET analysis and measurement. In particular, the project will deliver new methods for timing analysis at both the system level and the code level in an open framework. Another objective is achieving demonstrable increase of 25% in productivity in the timing domain of embedded systems development by enabling a quick, safe, and automatic efficient mechanism for deriving timing data as opposed to the manual, laborious traditional approach.

Technical Approach The project will provide a detailed requirements study with the aim at setting the scene for future timing analysis research. A secondary objective is therefore the increase in productivity of embedded systems development by enabling a quick and automatic efficient mechanism for deriving timing data as opposed to the manual, laborious traditional approach.

COOPERATION

European Commission Information Society and Media

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The technological objectives relate to the actual implementation of the theories, analysis methods, and tools developed in this project. These will be validated with prototypes and demonstrated with targeted pilot case studies at industrial companies towards the end of the project. A key component is the investigation of methods for the interoperability of tools, to facilitate easier integration into the customer build processes. An important objective of the project is the validation and dissemination of the technology to a wide potential customer base as a mechanism for providing a path to exploitation of the results developed within the project. These dissemination activities will be accompanied by publication of results in form of guidelines for non-expert users on applying timing analysis technologies, as well as other means such as academic conferences and participation in trade shows.

Key Issues EU industries face a difficult task to improve the reliability, safety, performance and resource efficiency of systems with regard to timing. Even though EU is leading in research and development, as well as technology transfer, the take up by industry is still low. This project aims at improving the lead of EU in the development and provision of advanced timing analysis techniques. There are several aspects to this problem; we classify them in the following themes: Theme 1: Interoperation, scale and automation There are fundamental research problems that need to be fully addressed to ensure that Europe continues its lead in the technology adoption process. The first one is the interoperation of tools. Furthermore, some of the current analysis techniques have serious scalability issues relating to the size of the programs to be analysed. Finally, a major issue is the full automation of the analysis process.

Theme 2: Integration into build process The adoption of a new technology implies change, which demands clear demonstrable benefits in perspective, and may be costly. Thus, new technology may be slow to deploy and integrate into the end-customer process. Academic prototypes are not usable by large companies that require commercial quality tools with long-term support guarantees. A second issue is the large number of evolved procedures and constraints, which can make it difficult to exploit a technology simply because required input data cannot be obtained, or because parameters yielding the biggest improvements cannot be changed. This project will address these issues by targeted pilot studies to demonstrate the added value that investing in timing analysis tools brings to customers. Theme 3: Education, and dissemination of knowledge The number of experts in timing analysis is fragmented over universities and small companies, and their impact to reach a wider audience is limited. The current level of education and knowledge of timing issues of engineers is not sufficient.

Expected Impact ALL-TIMES will strengthen the competitiveness of several key industries in Europe, most notably the automotive and aerospace areas. Beyond these industries, automation, manufacturing, robotics, medical, communication, and multimedia are markets where timing is important. The ALL-TIMES project will thus x Interface the five different analysis techniques listed above (three code-level and two systemlevel techniques) that are represented in the project x Provide an open (quasi-standard) interface to integrate additional timing analysis techniques and tools, aiming at becoming a de-facto standard. x Provide solutions for timing analysis/estimation in early design phases as part of design-space exploration and architecture optimization.

Timing analysis

Code analysis

Measurement

Measurement based analysis

System analysis

Static code analysis

Tracing and displaying

Figure 1 Relations between different timing analysis techniques

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Static scheduling analysis

Embedded Systems Design COORDINATION AND SUPPORT ACTION

ARCADIA Aligning ResearCh AgenDas In ARTEMIS The ARCADIA project main objective is to have better and effective coordination of the efforts in order to optimize the use of the resources for the Embedded System field to strengthening Europe´s future growth, competitiveness and sustainable development. KEYWORDS: Alignment of Strategic Research Agendas, aligning roadmaps in Embedded Systems, identifying international, national and cluster programs.

Main Objectives

At A Glance: ARCADIA Aligning ResearCh AgenDas In ARTEMIS

Project Coordinator: Name: Sergio bandinnelli Institution: ESI-Tecnalia Email: [email protected] Project Technical Manager: Name: Inaki Eguia Institution: ESI-Tecnalia Email: [email protected] Project website: www.arcadia-project.eu Partners: ESI-Tecnalia (Spain) Thales (France) SafeTrans (Germany) NKTH (Hungary) TU Vienna (Austria) UJF Filiale (France) Siemens (Germany) Eutema (Austria) ST-Microelectronics (Italy) Duration: 24 months Start: 2010.11.01 Total Cost: 750.000€ EC Contribution: 750.000€ Contract Number: INFSO-ICT-247912

European companies and other research and development organisations active in the field of Embedded Computing Systems took the lead in establishing, under the Sixth Framework Programme, the European Technology Platform on Embedded Computing Systems (referred as the "ARTEMIS Technology Platform"). One of the main ambitions of ARTEMIS, the Advanced Research and Technology in the Embedded Intelligent Systems Technology Platform when started in 2004, was to overcome the fragmentation in the Embedded Systems, by cutting barriers between application sectors so as to ‘de-verticalize’ the industry, sharing across sectors tools and technology that are today quite separate and establishing a new embedded system industry that supplies tools and technology that are applicable to a wide range of application sectors. The ARTEMIS Technology Platform developed a Strategic Research Agenda based on an extensive consultation with public and private stakeholders. An update of this SRA is planned for end of 2010.

ARCADIA will focus on aligning National and Regional European Agendas in Embedded Systems

The ARCADIA project main objective is to have better and effective coordination of the efforts in order to optimize the use of the resources, and to contribute in to the advance of an ERA for the Embedded System field to strengthening Europe's future growth, competitiveness and sustainable development.

COOPERATION

European Commission Information Society and Media

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Technical Approach

Key Issues

Indeed, there is a strong need to pursue the efforts to consolidate these achievements in order to advance the European Research Area building, particularly for coordinating national, regional and EU-wide R&D strategies and in undertaking actions and initiatives to advance the European Research Area and to align research agendas in the field of embedded systems.

ARCADIA process will follow the next key issues in order to success: 1. Transparency: as the decision taking procedures within the process are clearly and openly stated and each decision is properly justified on the basis of pre-defined criteria. 2. Open participation: that are public and known to every participant will allow the participation of all relevant stakeholders and any interested party 3. Commitment: the Participants will explicitly accept the rules and commit to the process, which involves supporting the outcome of it. 4. Consensus building: As the overall idea of the process is not to find an equidistant point from different positions but to reason together to enlarge the area of agreements: making the pie larger, rather than playing a zero sum game.

ARCADIA – Joining forces ARCADIA Project aims at building on top of these solid grounds. ARCADIA is conceived as an effective coordination among these initiatives, using the results obtained so far and closely collaborating in the execution of the project tasks. This will be achieved by: x

x

x

x

x

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Joining the multiple initiatives in the embedded system field, benefiting from the work done so far, avoiding duplication of efforts and aiming at ONE common vision. Mobilising resources from partners that are active members of ARTEMISIA representatives of the SME, academia and research organisations as well as large industrial groups. Actively seeking coordination with on-going initiatives, in particular COSINE2 and ARTEMISIA SRA WG, facilitating the bridge between a large number of National/regional authorities in Europe and industrial groups. Establishing relationships with embedded systems education and training, linking with the working groups in ARTEMISIA. Giving more visibility to all stake holders of the different perspectives (political, technical, national and European) through common dissemination events

Expected Impact The benefits for embedded systems research gained through ARCADIA can be summarised as follows: x

x

x

x

Advice on an effective and efficient use of the scarce R&D resources to advance the European Research Area Make particular focus on research priorities, such as the Embedded Systems Design, to advice on the best funding scheme to address them: FP7, ARTEMIS JU, National/Regional, Eureka Practical approach for aligning national and regional programmes sharing a common vision, but addressing specificities in their areas of competence. A comprehensive understanding of expected impact of R&D programmes in business and society.

Embedded Systems Design NETWORK OF EXCELLENCE

ArtistDesign ArtistDesign Network of Excellence on Embedded Systems Design The ArtistDesign NoE is the visible result of the ongoing integration of a community. It builds on existing international visibility and recognition, to play a leading role in structuring the area. KEYWORDS: Embedded Systems Design, Systems Architecture, Systems Engineering, Real-Time Programming, Applications, SoC, Dependability, Modelling, Model-based Design, Hard Real Time, Adaptive Real Time, Component-based Design, Compilers, WCET, Timing Analysis, Execution Platforms, Control for Embedded, Testing, Verification, Integrated Modular Avionics, Autosar, Wireless Sensor Networks, Distributed Systems Univ of Kaiserslautern KTH Linköping Univ of Lund Mälardalen Univ OFFIS PARADES Univ of Passau Scuola Superiore Sant’Anna Porto Polytech Saarland Univ Univ of Salzburg Uppsala University TU Vienna Univ. of York

At A Glance: ArtistDesign

ArtistDesign Network of Excellence on Embedded Systems Design

Project Scientific Coordinator Name: Joseph Sifakis Institution: Verimag Laboratory Email: [email protected]

Duration: 48 Months Start: 2008.01.01 EC Contribution: € 4.5 M

Project Technical Coordinator Name: Bruno Bouyssounouse Institution: Verimag Lab/UJF Filiale Email: [email protected]

Contract Number: NoE 214373

Main Objectives Project website: http://www.artist-embedded.org/ The central objective for ArtistDesign is to build on existing structures and links forged in Artist2, to become a virtual Center of Excellence in Embedded Systems Design. This will be mainly achieved through tight integration between the central players of the European research community. Also, the consortium is smaller, and integrates several new partners. These teams have already established a long-term vision for embedded systems in Europe, which advances the emergence of Embedded Systems as a mature discipline. ArtistDesign is the ArtistDesign will extend its main focal point for dissemination activities, dissemination in including Education and Embedded Systems Training, Industrial Design, leveraging Applications, as well as on well-established International Collaboration. infrastructure and links.

Partners: Univ. Joseph Fourier/VERIMAG UJF Filiale SAS – Floralis RWTH Aachen, Aalborg University Univ Aveiro Univ of Bologna, TU Braunschweig Univ of Cantabria CEA TU Denmark TU Dortmund EPFL ESI ETHZ IMEC INRIA

COOPERATION

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ArtistDesign will establish durable relationships with industry and SMEs in the area, especially through ARTEMISIA / ARTEMIS. ArtistDesign will build on existing international visibility and recognition, to play a leading role in structuring the area. The research effort aims to integrate topics, teams, and competencies, grouped into 4 Thematic Clusters: “Modelling and Validation”, “Software Synthesis, Code Generation, and Timing Analysis”, “Operating Systems and Networks”, “Platforms and MPSoC”. “Transversal Integration” covering both industrial applications and design issues aims for integration between clusters.

Technical Approach The ArtistDesign NoE implements a Joint Programme of Activities, composed of: ƒ Joint Programme of Management Activities (JPMA) plan, organize, direct and monitor the integrated effort to efficiently achieve the technical objectives within the ArtistDesign constraints of time schedule and budget. ƒ Joint Programme of Activities for Spreading Excellence (JPASE) These activities serve as a relay between the NoE and the international embedded systems design community at large. They are managed at the NoE level, and are mostly not specific to any cluster. ƒ Joint Programme of Integration Activities (JPIA) The JPIA activities are carried out on a global, NoE level, transcending the clusters. They form the supporting background for integration of the NoE, and are executed in phase and in interplay with the JPRA research activities. ƒ Joint Programme of Research Activities (JPRA) The JPRA is structured into 4 Thematic (horizontal) Clusters, and a Transversal Integration workpackage. Thematic clusters are autonomous entities, with specific objectives, teams, leader(s), and a dedicated yearly budget. The set of Thematic Clusters cover all the main topics in Embedded Systems Design. The thematic activities in the Transversal Integration workpackage focus on Design methodologies, with specific objectives (Predictability, Adaptivity).

Expected Impact The ArtistDesign NoE actions target the embedded systems community as a whole, at 2 levels: 1. Actions targeted towards the affiliated partners Affiliated partners are not core members in the consortium, but receive support for travelling to ArtistDesign meetings, and actively contribute to the implementation of the Joint Programme of Activities (JPA). These affiliated partners include industrial, SME, academic, and international affiliates. 2. Targeted towards the scientific and technical community in the large This is achieved mainly bottom-up through the organization of scientific events, publications, distribution of tools and components, industrial partnerships (not funded by ArtistDesign), education; and through the Artist2 web pages. Regarding Scientific events, we distinguish between conferences and workshops, schools, and high-level events mainly for International Collaboration.

Key Issues The research effort aims to integrate topics, teams, and competencies, grouped into 4 Thematic Clusters: “Modelling and Validation”, “Software Synthesis, Code Generation, and Timing Analysis”, “Operating Systems and Networks”, “Platforms and MPSoC”. “Transversal Integration” covering both industrial applications and design issues aims for integration between clusters.

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Embedded Systems Design RESEARCH PROJECTS

COCONUT A Correct-by-Construction Workbench for Design and Verification of Embedded Systems The COCONUT project is intended to propose a modelling and verification flow to enhance and speed-up embedded platform’s design and configuration of mixed continuous/discrete models KEYWORDS: embedded systems, hybrid systems, modelling, verification Main Objectives At A Glance: COCONUT A Correct-by-Construction Workbench for Design and Verification of Embedded Systems

Project Coordinator: Name: Franco Fummi Institution: University of Verona Email: [email protected] Project Technical Managers: Name: Graziano Pravadelli, Tiziano Villa Institution: University of Verona Email: [email protected] [email protected] Project website: www.coconut-project.eu Partners: Aerielogic (France) CEA-LETI (France) Certess S.A. (France) Fondazione Bruno Kessler (Italy) University of Southampton (UK) Graz University of Technology (Austria) Universität Paderborn (Germany) Università di Verona (Italy)

,

The COCONUT methodology follows the entire embedded platform design flow starting from specifications through all TLM levels down to RTL synthesis for hardware components, and compilation for software modules. The project addresses refinements related to the design of hardware, software and middleware with particular regards to application fields related to mixed continuous/discrete models, like for example networked multimedia and sensor network management. In this context, the S&T objective of the COCONUT project consists of developing a systematic methodology and a set of tools to integrate correctby-construction refinement/abstraction and postrefinement verification methods into a platform-based design flow. COCONUT will focus on Hereafter, a list of the definition of a formal high-level framework based on a requirements to be tight integration of design considered for the and verification through success of all refinement steps of an COCONUT project embedded platform follows. design flow. 1. To define a methodology, supported by tools, to identify system requirements for platform modelling and verification by identifying a connection between hybrid and discrete domains. 2. To provide a methodology to express useful properties at the hybrid and TLM domains, validate their consistency and completeness and use them for semi-automatically synthesizing critical components.

Duration: 30 months Start: 2008.01.01 Total Cost: € 3.348.224 EC Contribution: € 2.550.000

3. To improve and integrate different modelling techniques operating at both hybrid and discrete domains, based on correct-by-construction abstraction/refinement of models and properties.

Contract Number: INFSO-ICT-IST-1-217069

4. To integrate dynamic and static post-refinement verification around a coherent assertion-based approach. 5. To apply the COCONUT methodology and tools to a real platform for validating the approach and showing its effectiveness in the industry.

COOPERATION

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Technical Approach The embedded platform market is converging on a limited but more powerful set of embedded platforms, mainly due to increasing design cost which requires higher production volume. Differentiation among effective platform configurations is thus a key advantage for a platform user to approach the market with innovative solutions. Design and verification of such a kind of embedded platforms are two highly related problems which are still mainly faced by using unrelated methodologies. The complexity of both platform design and platform configuration requires an innovative design and verification flow able to effectively reduce the number of design errors and design recycles. This is a key factor for increasing system development productivity while achieving predictable system properties. Moreover, an incremental and hierarchical verification strategy is fundamental to manage the huge complexity of this embedded platform that cannot be verified in the whole at a structural level such as the RTL. Even at TLM the platform modelling would be difficult due to the presence of complex networks and continuous-time information. As a result, the addition of hybrid automata to SystemC TLM models will be proposed for tackling the modelling complexity. In both platform design and platform configuration, this very abstracted platform description requires correctby-construction refinements and/or automatic verification of manual refinements, to translate, without design errors, the abstract description into an actual application. This is the main objective of the COCONUT project. In this context, the key idea of COCONUT is depicted in the next Figure. Platform design and platform configuration are considered as a continuous mix of the following processes:

Abstraction

Proof of correctness

Synthesis

Validation Properties

Abstraction Level i

System Model

Verification

Refinement

20

Hybrid/discrete domain mapping

x

definition and validation of properties that represent the specification;

x

automatic synthesis of properties into code;

x

mapping of models between hybrid and discrete domains;

x

correct-by-construction abstraction/ refinement;

x

post-refinement verification with respect to the specification.

Such activities will be implemented in a set of tools working on more than one abstraction level whose correctness will be formally proved. Each model/property can be refined to a lower abstraction level or abstracted to a higher abstraction level, and verification should not be only a post-refinement step, but it should guide the design with a correct-byconstruction methodology.

Key Issues The key issue of the COCONUT project can be summarized in the following aspects: 1. Definition of system requirements and validation of specifications. 2. Automatic synthesis of properties. 3. Mapping between hybrid and discrete domains. 4. Correct by construction abstraction/refinement 5. Post refinement verification 6. Proof of correctness of the COCONUT activities.

Expected Impact The COCONUT project is in line with the general target of ensuring “improving the competitiveness of European industry and research”, and particularly it is expected to: x Increase the quality of both European research and industry by putting academia in touch with industrial challenges and allowing SMEs to access the research results they need for anticipating clients’ demand. x Let European research centres and SMEs increase the productivity of the embedded platform configuration phase, thus allowing a more effective design of innovative embedded systems. x Fit the objective of “greatly improve industrial production processes” thereby “increasing productivity” and final quality. Indeed, the goal of the project is to ensure system quality at design phase and detect design errors and faults when they are easy to repair.

Embedded Systems Design RESEARCH PROJECTS

COMBEST COMponent-Based Embedded Systems design Techniques COMBEST will provide a formal framework for component based design of complex embedded systems: 1) formal integration of heterogeneous components; 2) encapsulation of components; 3) prediction of emergent key system characteristics; 4) corresponding certificates. KEYWORDS: formal frameworks, component based design, complex embedded systems, formal integration, heterogeneous components, models of communication, models of execution, encapsulation functional properties, extra-functional properties, composability, compositionality, system characteristics, performance, robustness, distributed HW-architectures, design theory, heterogeneity, interface specifications, SPEEDS, rich components, compositional analysis Duration: 36 Month Start: 2008.01.01 EC Contribution: 2.75 M€

At a Glance: COMBEST COMponent-Based Embedded Systems design Techniques

Contract Number: STREP 215543

Main Objectives COMBEST will provide a formal framework for component based design of complex embedded systems. This framework will: 1. Enable formal integration of heterogeneous components, such as with different models of communication or execution; 2. Provide complete encapsulation of components both for functional and extrafunctional properties and develop foundations and methods ensuring composability of components; 3. Enable prediction of emergent key system characteristics such as performance and robustness (timing, safety) from such characterizations of its subcomponents; COMBEST will focus 4. Provide certificates for on formal guarantees of such key integration of system characteristics when heterogeneous deployed on distributed HWcomponents. architectures

Project Scientific Coordinator: Name: Joseph Sifakis Institution: Verimag Laboratory Email: [email protected] Project Technical Coordinator: Name: Bruno Bouyssounouse Institution: Verimag Lab/UJF Filiale Email: [email protected] Project website: http://www.combest.eu/ Partners: Univ. Joseph Fourier UJF/VERIMAG (France) UJF Filiale SAS - Floralis (France) TU Braunschweig (Germany) EADS (Germany), EPFL (Switzerland) ETHZ (Switzerland) INRIA (France) IAI (Israel), OFFIS (Germany) PARADES (Italy) Università Trento (Italy)

To achieve these objectives, COMBEST will:

COOPERATION

x

Develop a design theory for complex embedded systems, fully covering heterogeneity, interface specifications, composability, compositionality, and refinement for functional and extra-functional properties.

x

Build on substantial highly recognized background results of the academic partners, partly carried out within the integrated project SPEEDS.

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Extend results of the Integrated Project SPEEDS, both regarding heterogeneous rich components and compositional analysis methods.

x

Collaborate with the best US groups in embedded system design to build critical mass in a strategic area of vital interest to the European industrial ecosystem

Technical Approach The project pursues a dual approach, combining fundamental work with methods and tools for rigorous embedded systems design. The fundamental work in COMBEST studies component-based design, by tackling two main problems: x

Developing frameworks for the composition of heterogeneous components.

x

For such frameworks, develop theory allowing constructivity: inferring global properties of a system from the properties of its components. The methods and tools developed use results of the theoretical work, to ensure a rigorous design for heterogeneous systems. The tools cover modelling, verification, and performance analysis. Their use is supported by a global design methodology. In addition, we use two case studies, provided by industrial partners, to evaluate the relevance and applicability of the tools.

Expected Impact Key Issues For embedded systems, component-based design techniques should address both hardware and software components in a unified way. They should be able to handle hard constraints on performance and dependability as well as dissimilarities between levels of abstraction and communication primitives. The two main difficulties to handle are: x The presence of heterogeneous components. In software engineering, components are mainly used for structuring functions and associated data. In contrast, hardware components are inherently parallel, and synchronous. x Predictability of basic properties of the designed system. We argue in favour of constructivity, which is reasoning about global system properties based on properties of its individual components. Constructivity should allow satisfaction of essential properties by construction, to avoid costly a posteriori global system validation. Providing formal frameworks which overcome these difficulties is only a first step towards disciplined system design. It is essential that theoretical results be integrated in coherent component-based design flows, validated through comparison with existing industrial practice. Furthermore, theoretical results should be implemented in scalable supporting methods and tools.

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COMBEST will deliver significantly advanced technology for strengthening European excellence in embedded systems design. COMBEST will provide the basis for mastering holistic design methodologies, allowing European industries to maintain and even improve their technological leadership. More specifically, we expect a positive impact for: x Component re-use and domain independence. The emergence of componentbased design as the primary design method for embedded system should allow component reuse across multiple domains. A concentration of the efforts in the European supplier industry will become possible due to emergence of crossdomain tools and methods. This reduction of fragmentation and the focused use of resources will speed up the development cycles in the supplier industry. x

Decreased development cost. Decreasing the development cost is of particular importance in Europe, which tends to have a competitive disadvantage due to high cost of labour.

x

Decreased time-to-market. A shorter time to market will give the European industry is a decisive competitive advantage in today’s fast paced business world.

Embedded Systems Design RESEARCH PROJECTS

COMPLEX COdesign and power Management in PLatform-based design space EXploration The primary objective of COMPLEX is to develop an innovative, highly efficient and productive design methodology and a holistic framework for iteratively exploring the design space of embedded hardware/software (HW/SW) systems. KEYWORDS: Design Methodology, Electronic System-Level, Design Space Exploration, Timing, Power Consumption, Platform-based Design, Virtual Platform, UML, MARTE, SystemC™, TLM, IP-XACT Main Objectives At a Glance: COMPLEX COdesign and power Management in PLatform-based design space EXploration

Project Coordinator: Name: Wolfgang Nebel Institution: OFFIS e.V. Email: [email protected] Project Technical Manager: Name: Kim Grüttner Institution: OFFIS e.V. Email: [email protected] Project website: http://complex.offis.de Partners: OFFIS (DE) STMicroelectronics (IT) STMicroelectronics (CN) NXP (NL) Thales Communications (FR) GMV (ES) CoWare (BE) ChipVision (DE) EDALab (IT) Magillem (FR) Politecnico di Milano (IT) Universidad de Cantabria (ES) Politecnico di Torino (IT) IMEC (BE) ECSI (FR) Duration: 36 Month Start: 2009.12.01 Total Cost: 7.2 M€ EC Contribution: 4.8 M€

The COMPLEX consortium develops a new design environment for platform-based design-space exploration offering developers of next-generation mobile embedded systems a highly efficient design methodology and tool chain. The integrated environment allows iterative exploration and refinement of advanced applications to meet market requirements. The design technology in particular enables fast simulation and explores the use of different implementations at Electronic System Level (ESL) with up to bus-cycle accuracy at the earliest instant in the design cycle. The main objectives are: ƒ Highly efficient and productive design methodology and holistic framework for design space exploration of embedded HW/SW systems. The framework will be platform independent and application domain independent and will provide open interfaces for new industry players. ƒ

Combination and augmentation of well established ESL synthesis & analysis tools into a seamless design flow enabling performance & power aware virtual prototyping of the HW/SW system.

ƒ

Interfacing nextgeneration modeldriven SW design approach and industry standard model-based design environments.

ƒ

Multi-objective co-exploration for assessing design quality and optimizing the system platform with respect to performance, power, and reliability metrics.

ƒ

Fast simulation and assessment of the platform at ESL with up to bus-cycle accuracy at the earliest instant in the design cycle.

ƒ

Optimization benefits from run-time mode adaptation techniques, such as dynamic power management or application adaptation to varying workloads.

Contract Number: IP 247999

COOPERATION

COMPLEX will focus on early, fast yet accurate platformbased design space exploration at the system-level.

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Technical Approach

Key Issues

The COMPLEX framework is a design flow with performance and power aware virtual prototyping of an embedded HW/SW system. Several well established ESL synthesis and analysis tools from vendors such as CoWare, ChipVision, EDALab, and Magillem will be augmented and combined into the seamless COMPLEX design flow.

Existing barriers between HW and SW developers are lowered, allowing SW designers to explore various HW implementations and hiding irrelevant technical details, thus having a clear view on the results of the application code transformations in terms of timing behaviour and power consumption.

The hardware/software co-exploration considers both the architecture design space and the application space to assess trade-offs when designing nextgeneration embedded systems. The co-exploration is multi-objectively assessing the design quality and optimizing the system platform with respect to performance, power, reliability metrics, etc. The optimization benefits from run-time mode adaption techniques, such as dynamic power management or application adaption to evolving workloads, can be maximised and reported to successive synthesis steps using standardized output formats.

SystemC

BAC++

BAC++

SystemC

virtual system generator with TLM2 interface synthesis

power & timing aware SystemC simulation model

design space instance parameters

at virtual architecture level design space instance

SW tasks

power controller

IP components

at system level

Multi-Objective Design Space Exploration Framework system metrics

HW tasks

custom SW estimation

The COMPLEX results are expected to support the overcoming of technology roadblocks by reinforcing Europe's industrial strengths for building increasingly smaller, cheaper, more reliable and less power consuming electronic components and systems, taking into account the alternative paths to next generation technologies and sustainable development. The provision of environmentally friendly sustainable systems is a key differentiating factor in various applications. Moreover, this will support the competitiveness of industrial players such as automotive, avionics, industrial automation, consumer electronics, telecoms, and health. Consequently, COMPLEX will lay the foundations for innovation in various major products and services.

exploration & optimization

estimation & model generation

custom HW estimation

HW/SW task separation & testbench generation

IP-XACT

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architecture/ platform description

executable SystemC™ model

Expected Impact

at specification level

MARTE & Matlab/Simulink Model

simulation

executable Model-Driven specification design entry

The framework combines several standards for system modelling and integration: Possible design entry is either in C++/SystemC or a MARTE/UML model, offering seamless integration into a modeldriven design approach.

The COMPLEX framework enables system integrators to find the ideal technology platform. Technology providers benefit from COMPLEX since they can now offer fast and accurate platform models to their customers. EDA companies are offering a more complete solution to their customers with the COMPLEX framework.

simulation trace

design space definition

For co-development the COMPLEX framework follows a new approach using a unified internal representation of the HW and SW, called block annotated C++ (BAC++). It is generated by SW cross-compilers and HW behavioural synthesis tools. In the COMPLEX framework, the generated BAC++ code is integrated into a SystemC™/TLM2 virtual platform model, enabling fast system simulation.

Embedded Systems Design COORDINATION AND SUPPORT ACTION

COSINE2 Co-ordinating Strategies for Embedded Systems in the European Research Area Follow-up Project COSINE2 aims to enhance the impact of European RTD strategies in the area of Embedded Systems. To achieve this, it will be necessary to better align national research strategies with each other, with the EC programmes, and with new initiatives such as the ARTEMIS ETP (European Technology Platform) and the JTI (Joint Technology Initiative) on Embedded Systems. KEYWORDS: European Research Area (ERA), ERA-Net, Embedded Systems, Embedded Intelligence, National research funding programmes. At A Glance: COSINE2 Co-ordinating Strategies for Embedded Systems in the European Research Area Follow-up Project

Project Coordinator Name: Dr. Erich Prem Institution: eutema Technology Management GmbH Project Technical Manager Name: Martin Marek Institution: eutema Technology Management GmbH Email:[email protected] Project website: www.cosine-ist.org Partners: Eutema (Austria) Tekes (Finland) DLR (Germany) ISERD (Israel) UTIA (Czech Republic) VINNOVA (Sweden) BMVIT (Austria) NKTH (Hungary) IWT (Belgium) MUR (Italy) CEA (France) Duration: 30 months Start: 2007.12.01 Total Cost: € 600.000 EC Funding: € 600.000 Contract Number: INFSO-ICT-215594

Main Objectives The core aim of the Support Action is to improve cooperation between EU, national, and regional ES RTD programmes and policies and to realize the vision of European Embedded Systems Research Area. One particular aim is to open more national EU ES programmes for participants from other EU member states. COSINE2 will offer support for policy representatives and programme managers willing to co-operate. COSINE2 aims at offering a service to all European RTD policy actors willing to co-ordinate their programmes, regardless of their representation in the Support Action. COSINE2 will COSINE2 also intends to further improve cocollect success stories of operation between other co-operative EU, national, and programmes. Alignment and regional Embedded co-ordination of strategies Systems requires information on ES programmes and policies at EU and member policies. states level. An important sub-goal of COSINE2 is to install a process for continuous monitoring of ES strategies, policy and programme actors, and funding opportunities. This should also include links to selected international activities to allow informed decision making and to inform the research community, policy actors, and programme managers. In close cooperation with other EU projects such as ARTIST, COSINE2 aims to improve co-operation in the areas of education and training which are rather isolated today in the EU’s member states. COSINE2 aims at establishing and maintaining close contacts with the ARTEMIS Joint Technology Initiative taking opportunity of the representation of COSINE members in the ARTEMIS public authorities institutions. COSINE2 aims to interact with EU ES industry, to support the member states’ actors, and to assist at the level of national public policies. Also, COSINE aims at monitoring SME issues in ARTEMIS and in the JTI on Embedded systems.

COOPERATION

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Technical Approach

Key Issues

COSINE2 will achieve its goals based on linking Embedded Systems programme managers and policy makers, the EC and regional actors and creating the basis for informed strategic policy choices. It will distribute best-practice examples for trans-national co-operation and facilitate focused interaction with the industry driven ARTEMIS technology platform. COSINE2 will support countries developing or implementing Embedded Systems RTD strategies regardless of their participation in the project. Dedicated co-operation with regional organisations will improve the involvement of small and medium sized enterprises in research actions and accelerate the take-up of ES technology. COSINE2 will create wide impact with information services on ES RTD initiatives for policy makers, programme managers, and the research community. In this way, COSINE2 will realize the vision of a European Embedded Systems Research Area. Work is structured in four packages and project management. WP1 addresses European strategies and programmes for Embedded Systems. WP2 deals with the important relation to the ARTEMIS initiative. WP3 targets public relation and dissemination of project results. And WP4 tackles strategies for small and medium sized enterprises. Although COSINE2 as a Support Action cannot address SMEs individually, COSINE2 aims at getting the attention of important regional actors in the innovation system for the ES topic. COSINE2 aims at receiving public awareness and interaction with the stake holders. Instead, COSINE2 aims at linking and pinpointing existing information and combining it with newly collected and generated information for research policy makers but also for researchers. Also in this line, COSINE2 aims at fostering a discussion with the ES research on community on strategic research areas. COSINE2 aims at an efficiently managed policy support action that remains sensitive to the individual interests of the member states.

Embedded Systems are a key driving innovation factor in leading European industry sectors such as consumer electronics, automotive, or aerospace. As a reaction, policy makers in the EU and members states have created a collection of dedicated RTD initiatives. It is now time to improve their impact through opening, co-operation, and co-ordination with key strategic initiatives such as the ARTEMIS technology platform. COSINE2 will facilitate the opening of national research programmes, and create synergy among EU, national, and regional programmes and policies to improve the European Research Area for Embedded Systems. While the advent of the ARTEMIS technology platform and the Joint Technology Initiative have generated considerable dynamics in the area of embedded systems research and technology, many member states or regions in Europe still run their own programmes. COSINE2 is an effort to align these programmes. Also, COSINE2 aims at supporting countries in developing their first or new ES programmes and, most importantly, in trans-national co-operation of programmes.

Expected Impact COSINE2 will enhance research and technology in the area of Embedded Systems in Europe through optimizing the alignment of national research strategies. COSINE2 also aims at leveraging the cooperation of research programmes to a new level. It will tune RTD policies optimally to the new European Embedded Systems Research environment currently under significant change in the EU. The consortium joins national authorities and research agencies with the power to durably influence the European research area.COSINE2 is a strategic initiative to maintain Europe’s strong international position in the area of Embedded Systems technologies.

ES RTD Strategies WP 1

Programmes Policies

WP 2 WP 4 ARTEMIS(IA) SME support support

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WP 5 Management

Embedded Systems Design RESEARCH PROJECTS

DESTECS Design Support and Tooling for Embedded Control Software DESTECS will develop a methodology that combines continuous-time models with discrete-event models through co-simulation and multi-domain fault injection tests to faster build more dependable real-time embedded systems. KEYWORDS: embedded control software, dependability, fault-injection co-simulation, model-based design, design tools, formal methods. Main Objectives At A Glance: DESTECS Design Support and Tooling for Embedded Control Software

Project Coordinator Name: Jan F. Broenink Institution: University of Twente Email: [email protected] Project website: www.destecs.org Partners: University of Twente (Netherlands) Newcastle University (United Kingdom) Engineering College Aarhus (Denmark) CHeSS B.V. (Netherlands) Controllab Products B.V. (Netherlands) Neopost Technologies B.V. (Netherlands) Verhaert New Products & Services N.V. (Belgium) Duration: 36 months Start: 2010.01.01 Total Cost: € 3 622 190 EC Contribution: € 2 739 175 Contract Number: INFSO-ICT-248134

The goal of DESTECS is to improve the productivity of innovative embedded system design by providing new methods and tools that can be used to design fault-tolerant, embedded systems using a multidisciplinary, collaborative model-driven approach, with the following objectives: x To reduce the effort spent in design iterations compared to current best practice for faulttolerant embedded control systems by means of multidisciplinary collaborative modelling. x To demonstrate the viability of industrystrength open tool support for collaborative modelling and cosimulation.

DESTECS will focus on model-driven methods & tools for fault-tolerant embedded control software design

x To evaluate, in an industrial setting, the effectiveness of collaborative modelling methods and tools for rapid design exploration and tool support. x To build a user and research community in collaborative modelling and co-simulation for embedded systems development.

Technical Approach We will develop methods and tools for the construction, co-simulation1, multi-domain fault injection2 tests and maintenance of collaborative models of control systems. Maintenance encompasses managing the evolution of models under change (including refactoring) so as to maintain their compatibility and traceability.

1

Co-simulation is running executable, heterogeneous models of parts of the system and its environment in one harness together, allowing communication between them with the aim of understanding how well or badly the resulting embedded system may perform in practice. 1

Fault injection means explicitly modelling abnormal behaviour of the environment and introducing faults to certain primitives. This allows early exploration of the consequences of defects and errors, and hence improved selection of design alternatives, including fault tolerance strategies.

COOPERATION

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Leading research challenges are: providing support for potentially large multi disciplinary models, and describing faults and fault tolerance mechanisms. In effect, we develop a specification of a “Model Base” for collaborative design. In DESTECS, we will develop tools and methods in three phases of 1 year each, thus giving annual intermediate results. Industry-led evaluations (industrial case studies) run concurrently with the methods and tool development work. In each phase, the same case studies are conducted, but using increasingly developed methods and tools. In phase 1, existing tools (20-sim and Overture/VDM++) are used for the cases; in phases 2 and 3, the methods and tools developed within DESTECS in the previous phase are used. Feedback from these test cases is used in the next methods / tool development phase. The industrial case studies are: (1) modular document handling system, to be made more reconfigurable using DESTECS results; (2) an inertial measurement unit, to be faster incorporated in applications; and (3) a bi-wheeled personal transporter, being a demanding test case for DESTECS model-driven approaches, as the system is intrinsically unstable. Additionally, new examples will be gathered from industry via the Industry Follow Group (IFG), in order to gain an evaluation of the potential benefits and challenges of deploying collaborative modelling and co-simulation in real industrial contexts.

Key Issues DESTECS will advance model-driven development by focusing on two engineering domains: (1) discrete event modeling of controllers and architectures and (2) continuous-time modeling of physical systems. By coupling these domains through co-simulation, cross-domain design issues can be tackled even in the early stages of a design process.

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DESTECS will exploit co-simulation as a basis for modelling faults and analysing fault tolerant designs for embedded systems that need to be predictably resilient. We will develop an Integrated Development Environment (IDE) with plug-in tools that support the integration of continuous and discrete modelling tools. This helps to close the gap between the discrete-event and the continuous-time models. DESTECS will not replace current practice but it will support the heterogeneity of tools and encourage collaborative design by allowing best practices in different engineering domains to be integrated.

Expected Impact The DESTECS technology will increase productivity because it will provide a common framework (methods and tools) in which models may be developed and simulated rapidly together at an early stage. This means that the most abstract models in both worlds can be co-simulated and feedback can be provided between the different disciplines “up front”. This common framework makes it natural and easier to explore fault tolerance of the full system at a much earlier stage, potentially saving significant amounts of rework. So the DESTECS technology impacts the cost of development (due to reduced rework), the time to market (due to better ability to do the development in parallel and synchronise across disciplinary boundaries) and the dependability (through earlier and more reliable handling of potential faults and fault tolerance) of the product.

Embedded Systems Design RESEARCH PROJECTS

EMBOCON EMBedded Optimization for resource CONstrained platforms The EMBOCON project aims to radically expand the scope of embedded systems applications to which embedded optimization and control methods can be applied. KEYWORDS: Embedded systems, real-time optimization, numerical algorithms. Main Objectives

At A Glance: EMBOCON EMBedded Optimization for resource CONstrained platforms

Project Coordinator: Name: Dr. Paul Goulart Institution: Imperial College London Email: [email protected] Project website: www.embocon.org Partners: Imperial College London (UK) Katholieke Universiteit Leuven (Belgium) ETH Zurich (Switzerland) University of Heidelberg (Germany) University Politehnica Bucharest (Romania) Technische Universität Dortmund (Germany) LMS International LMS (Belgium) IPCOS NV (Belgium) BASF SE (Germany) Duration: 36 months Start: 2010.01.15 Total Cost: € 4514950 EC Contribution: € 3249814 Contract Number: ICT-

An embedded system must be able to make reliable decisions with limited or no human assistance, often in real-time, drawing on observations made of its environment. This applies, for example, to ABS in cars, engine controllers, aircraft autopilots, dispatching systems in electrical and gas networks and to various medical systems. To date, most of these decisions are computed either with simple algorithms or by look-up tables generated through simulation and extensive testing. The simplicity of these algorithms facilitates an intuitive understanding as well as their real-time implementation, often on low-cost and lowperformance hardware. In contrast, an EMBOCON is founded embedded optimizer on close collaboration takes sensor input and between mathematical chooses the best action algorithm developers, to follow based on control theorists, criteria specifying hardware specialists desirable outcomes and and industrial partners. a model of how the environment would respond to system actions. This procedure would typically be repeated periodically, or be triggered by external stimuli, thus enabling the embedded system to adapt to changes in its environment. This optimization-based embedded system design paradigm has been proven to offer dramatic improvement over traditional schemes, which are largely designed around heuristic rules requiring extensive tuning and experience. Widespread deployment has been hindered primarily by the non-determinism of current algorithms, the inability of existing optimizers to function on competitively priced hardware and a lack of robust design methods. EMBOCON addresses these issues through a comprehensive work program focused on optimization under realtime, resource and reliability constraints.

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Technical Approach In order to enable the use of real-time optimization on embedded systems, it is not possible to consider the behaviour and performance of optimization and control algorithms in isolation for the particular embedded systems hardware on which they are implemented. Instead, it will be necessary to bring about a unification of methods in control theory, mathematical optimization, electronic engineering and computer science. Optimization for Embedded Systems The challenges addressed by the EMBOCON consortium focus on systems that are pushing the boundaries of what is possible: either very fast or complex dynamics and/or very limited computational resources. The consortium will focus specifically on developing optimization algorithms that provide firm run-time guarantees, stability and robustness guarantees, and graceful performance degradation in the presence of tight computational constraints. A variety of algorithmic methods, tailored to embedded systems applications and addressing the most common classes of optimization problem, will form a set of EMBOCON core optimization modules.

An Open Platform for Embedded Optimization Uptake of embedded optimization methods in European industry, including the EMBOCON core modules, will be enabled through the release of an open-source software platform for embedded optimization. This platform will serve as a common interface for algorithm developers and industrial practitioners, enabling rapid prototyping of optimization-enabled systems. EMBOCON will act as a driver for the development of this platform, whose lifetime will far exceed that of the proposed program. Industrial Benchmarks EMBOCON will demonstrate that embedded optimization is ready for widespread industrial application across many sectors. A selection of industrial benchmarking studies, drawn from the automotive, process control, aeronautics and robotics industries, will demonstrate the feasibility and benefits of real-time optimization. These demonstrators will show both the benefits of embedded optimization in real-world settings, as well as the ease of application and effectiveness of the EMBOCON open software platform.



Expected Impact Real-time optimization has already revolutionized industrial practice in some industries, particularly in process control. Advances in modern computing hardware and algorithmic methods now offer an opportunity to bring these same benefits to a huge range of new industries. The EMBOCON project will bring embedded optimization into standard practice on ubiquitous resource-constrained hardware found in real-time and mission-critical applications across Europe. The creation of a standard software platform for developers and practitioners will improve substantially the uptake of embedded optimization in industrial practice. The EMBOCON consortium will strengthen a network of world-leading academic and industrial partners with complementary expertise in control, optimization and embedded systems in a range of industrial applications. Particular emphasis is placed on close collaboration between mathematical algorithm developers, control theorists, hardware specialists and industrial application engineers. The consortium will consolidate and extend Europe’s position as the world research leader in these areas and foster strong collaborative links between European academia and industry.

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Embedded Systems Design RESEARCH PROJECTS

ENOSYS intEgrated modelliNg and synthesis tOol flow for embedded SYStems design ENOSYS will provide an integrated design flow for a rapid development of SoC embedded systems a) by the automated generation of SystemC code from the highlevel specification; b) by rapidly determining near-optimal solutions for hardware/software partitioning. KEYWORDS: MARTE, SysML, SoC, integrated design flow, co-design, design space exploration, automated partitioning, automated hardware and software synthesis Main Objectives

At A Glance: ENOSYS

Duration: 36 months Start: 2010.01.01 Total Cost: €3,97 M€ EC Contribution: €2,6 M€

The aim of the ENOSYS project is to specify and develop a tool supported design flow for designing and implementing embedded systems by seamless integration of high-level system specifications, software code generation, hardware synthesis and design space exploration. ENOSYS will provide an integrated workbench combining SysML, MARTE and FalconML. The OMG SysML and MARTE will be evaluated and extended to address end-user demands and requirements for integration. The approach and the tool flow will be evaluated and validated with representative scenarios from the telecoms domain. The results will be reported and presented at OMG in order to influence standardization and improve opportunities for adoption. The specific scientific and technological objectives include: x Develop MARTE extensions that address the needs for capturing high level specification and for design synthesis. ENOSYS will focus on x Integrate the an integrated design MARTE profile into flow including the existing tool advanced system flow, permitting the modelling, design automatic generation of space exploration and hardware/software SystemC and the synthesis of SoC hardware synthesis systems. of HDL.

Contract Number: INFSO-ICT-248821

x

Develop the means for the rapid and automated determination of near-optimal embedded system implementations using design space exploration.

x

Develop the tool support required for seamless software/hardware co-design.

intEgrated modelliNg and synthesis tOol flow for embedded SYStems design

Project Coordinator Name: Dr. Andrey Sadovykh Institution: SOFTEAM Email: [email protected] Project website: www.enosys-project.eu Partners: SOFTEAM, Thalès Communications (France) Axilica, Loughborough University (United Kingdom) Intracom Telecom, University of Peloponnese (Greece)

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System Specification (Textual)

Technical Approach

Key Issues Today, SoC vendors realize that critical decisions must be made long before development teams engage in the hardware and software design for new SoC and programmable SoC-based products. It is becoming clear that hardware-software design and verification must form part of a single, unified effort, whereas the methodologies currently available were intended to aid either hardware-only or software-only development. That these tools are no longer adequate for modern SoC designs is confirmed by the recent emergence of new concepts that are disrupting the traditional design flow; these include systemlevel specification (specification capture), functional and architectural analysis, and highlevel estimation, partitioning and software synthesis.

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Detailed System Modeling (Action code insertion) SMF: 3

Native Code Generation

Native mode execution

Automatic Action Code Source-Source transformation (1) SMF: 4

Vectors passed?

N

Verification (Phase 1)

Modeling

System Modelling Flow

System Model Refinement (MARTE conceptual modelling) SMF: 2

Y

System Area/Power/ Performance constraints

Target Platform Model

Automatic Hardware/Software Partitioning SDF:1

Hardware System SDF:2b Behavioural Synthesis

Multicore CPU SDF:2c System Synthesis

Verification (Phase 2)

Software System Synthesis SDF:2a Synthesis and Design Space Exploration

ENOSYS Synthesis and Design Exploration Flow

The proposed ENOSYS integrated tool chain will allow the development of arbitrary-complexity silicon processing platforms using both automatic and semi-automatic methodologies. Starting at the specification level, design intent is captured precisely and unambiguously in an object-oriented language based on UML MARTE profile. In addition, existing hardware and software intellectual property (IP) blocks are seamlessly accommodated in the design flow. The later is driven by graphical design entry at the UML level. The ENOSYS tool chain undertakes the process of code generation for a programmable platform, including the SoC interconnect backbone and the multi-level wrappers, resulting in a highperformance simulation engine and more importantly, the behavioural synthesis of the nonCPU mapped UML objects into hardwired, streaming engines. The tool chain (fully automatic mode) or the designer (semi-automatic mode) can quickly analyze the performance of candidate architectures and determine which will be the most effective, according to the given optimization criteria, such as embedded memory optimisation and interconnect architecture, bandwidth, silicon area, operating frequency and power consumption. The tool will prune and perform exploration of the design space using a search-based approach, such as a genetic algorithm, to analyse candidate architecture and micro-architecture solutions at rates of tens of configurations per minute. Finally, the few configurations that satisfy the performance criteria will be presented and further refined in the process of converging to a near-optimal solution.

ENOSYS System Modelling Flow

System and Requirements Modeling SMF: 1

Cycle/Bit-true System Model (Software and Hardware) SDF:3 Performance Evaluation (System Execution, RTL/SystemC) SDF4

SystemC Execution

Y

N

Vectors passed?

N

Area/Performance objectives achieved Y

Software Component

Hardware Component

Downstream Implementation Flow Standard-Cell/FPGA)

Expected Impact ENOSYS targets the following main impact objectives: x Significantly increased productivity of embedded system development and shorten time-to-market for SoC systems. x

Reinforced European scientific and technological leadership in the design of complex embedded systems.

x

Improved competitiveness of European companies that rely on the design and integration of embedded systems in their products by reducing design costs and time to market.

Embedded Systems Design RESEARCH PROJECTS

ERA Embedded Reconfigurable Architectures ERA aims at investigating and developing new methodologies in both tools and hardware designs to break through current power and memory walls for the nextgeneration embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance for given power budgets. The envisioned ERA platform is adaptive and employs a structured design to integrate the necessary computing, networking, and memory elements. KEYWORDS: reconfigurable/adaptive computing, memory hierarchies, power models, parameterized processor designs, dynamic reconfiguration, power awareness, structured embedded systems design, application profiling and benchmarking, embedded Linux, reconfiguration-aware compilation algorithms, fault-tolerance, dynamic parallel execution, gcc compiler. At A Glance: ERA

Main Objectives

Embedded Reconfigurable Architectures

In the Objective ICT-2009.3.4 "Embedded Systems Design", a strong focus is placed on the development of novel (generic) design methodologies that can be applied to several application areas. In the ERA project, we describe a platform that can adapt itself through coarse-grain reconfigurable hardware to tailor the hardware itself for changing environments and needs of the applications running on the platform, for different application markets and platform usage. We identified the following main objectives: x to define and develop a dynamically reconfigurable integrated platform composed by the following components: a parameterized VLIW processor, a reconfigurable NoC, and a memory subsystem - taking into account power consumption as design parameter

Project Coordinator Name: Stephan Wong Institution: Delft University of Technology Email: [email protected] Project website: www.era-project.eu Partners: Delft University of Technology (The Netherlands) Industrial Systems Institute (Greece) University of Siena (Italy) Chalmers University of Technology (Sweden) University of Edinburgh (United Kingdom) Evidence s.r.l. (Italy) ST Microelectronics (Italy) IBM Research Laboratory (Israel) Federal University of the Rio Grande do Sul (Brazil)

x

to provide the support for flexible and fast reconfiguration of the platform by using direct hardware support as well as partial FPGA reconfiguration.

x

to provide the needed hardware monitoring and low-level OS support to efficiently control the hardware reconfiguration.

Duration: 36 months Start: 2010.01.01 Total Cost: € 4.014.513,00 EC Contribution: € 2.8 M

ERA will focus on the development of an adaptive embedded system platform to handle the challenges of current embedded processor designs

Contract Number: INFSO-ICT-249059

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x

x

to benchmark and analyze a set of existing applications in the area of mobile processing to extract a set of off-line and on-line measurable parameters. to build a supervisor which will be able to monitor the parameters and react to online application changes to appropriately reconfigure the hardware.

The envisioned adaptive ERA platform employs a structured design approach that allows integration of varying computing elements, networking elements, and memory elements. For computing elements, we will utilize a mixture of commercially available off-the-shelf processor cores, industryowned IP cores, and application-specific/dedicated cores, and we will dynamically adapt their composition, organization, and even instruction-set architectures to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler exploiting the synchronicities between software and hardware. We strongly believe that having the complete freedom to flexibly tune the hardware elements will allow for a much higher level of efficiency (e.g., riding the trade-off curve between performance and power). Finally, an additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems design.

Technical approach In the ERA project, we identified four key areas to pursue innovations in order to achieve our objectives: x definition and characterization of application benchmarks for embedded systems employing reconfigurable architectures.

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x

definition of a reconfigurable parameterized processor architecture.

x

definition of subsystem.

x

definition of the software/compiler tools and OS support for the ERA platform.

a

reconfigurable

and

memory

The applications exhibit behaviour that can be exploited for more efficient processing (at given power budgets) by adapting the hardware (processor and memory) to them. This paradigm shift requires new approaches in compiler algorithms and tools and advanced (embedded) OS-level support. All partners have expertise in one or several of the mentioned areas.

Key Issues We believe that the run-time adaptive behaviour of the ERA platform is the key to develop embedded platforms for the new, heterogeneous and multiapplications embedded market. A major concern is the power utilization. This translates in several key issues that must be addressed in order to achieve a breakthrough. To cope with the reconfiguration power problem, in this project we focus on the development of accelerators using a coarse-grain reconfigurable fabric, composed of a reconfigurable VLIW processor, a flexible memory organization and an interconnection network that can provide better usage of power resources by distributing its routing resources online. A software stack consisting of a compiler and OS will provide the means to drive both static and dynamic reconfiguration decisions according to the application characteristics and the user objectives (in terms of power and performance).

Expected Impact The industrial partners clearly identified the benefits of the ERA project expressed in their involvement in and commitment to the project. All the solutions proposed in this project will be combined in a demonstrator platform that we expect will allow the industrial partners fast access to new products developed on top of it. The intended platform will serve several purposes: x Quick development platform for the industry: the clear interfaces defined in this project should allow the industrial partners to take from the platform everything they need and still incorporate their own IPs. Moreover, for low volumes even the prototype can be used as a commercially viable product, since the consortium will use available FPGA technology to validate its contribution. x Academic purposes: the ERA platform can be easily used to build different instances of embedded processing solutions and we foresee and will actively pursue the possibility of incorporating the ERA platform as a teaching tool in embedded courses or labs.

Embedded Systems Design RESEARCH PROJECTS

GALAXY GALS InterfAce for CompleX Digital SYstem Integration The project evaluates the ability of the GALS approach to solve system integration issues and implement a complex GALS system on an advanced 40 nm CMOS process. KEYWORDS: GALS, Asynchronous Design, System Integration, NoC

Main Objectives At A Glance: GALAXY GALS InterfAce for CompleX Digital SYstem Integration

Project Coordinator: Name: Dr. Milos Krstic Institution: IHP Email: [email protected] Project website: www.galaxy-project.org Partners: IHP (Germany) The University of Manchester (UK) Ecole Polytechnique Fédérale de Lausanne (Switzerland) Alma Mater Studiorum - Università di Bologna (Italy) Silistix UK Limited (UK) Infineon Technologies AG (Germany) Duration: 36 months Start: 2007.12.01 Total Cost: € 4.079.489 EC Contribution: € 2.900.000 Contract Number: INFSO-ICT-214364

The increased complexity, performance requirements, and the need for power and EMI reduction present almost unsolvable challenges to designers of complex embedded systems. The continued technology improvement generates additional problems for embedded system design. The combination of complex application requirements and technology imperfections exacerbate the problems of timing closure and clock tree generation requiring additional design iterations. It is imperative to deal with these issues; one very promising option is the use of a Globally Asynchronous Locally Synchronous (GALS) design methodology. When analyzing why a GALS approach has not been adopted by industry we observe that several issues have not been fully addressed until now.

GALAXY will focus on the GALS low EMI properties, inherent low-power features and robustness to process variability problems in nanoscale geometries Firstly, the design-flow for GALS chip interconnect is not mature enough to guarantee reliable and comfortable chip design. Secondly, the main strengths of GALS design, such as improvement of system integration, better EMI characteristics and power reduction, were never completely exploited and proven in practice. Lastly, the targeted GALS applications were sometimes not a perfect match with the GALS techniques. In this project, we address these problems and intend to prove that the GALS methodology offers powerful solutions for modern embedded system design integration. We aim at promoting the development of GALS system design by providing an interoperability framework between the existing open or commercial CAD tools for rapid design and prototyping. We will explore and evaluate the ability of GALS to solve system integration issues as well as building on its reduced EMI and low-power properties. A promising target platform can be seen in the area of Networks on Chip (NoC). In this project we intend to investigate different approaches of implementing GALS-enabled NoC platforms, comparing them with fully synchronous implementations, and of integrating the NoC design flow into the GALS design flow.

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Furthermore, nanoscale technologies have their own issues such as process variability and reliability. In the framework of this project we will explore these critical issues in the context of GALS. Additionally we intend to evaluate the effectiveness of a GALS system design for a highly complex wireless communication application in a very advanced 40 nm CMOS process.

Technical approach On the basis of the previous discussion, we are planning to analyse existing GALS solutions. During the project we will select optimal GALS architectures for the target applications and define the communication interfaces. In this project, a GALS framework providing interoperability between design tools for rapid design and prototyping will be proposed. This design flow will be based on commercial CAD tools and on the existing Balsa framework with extensions to mixed synchronous-asynchronous systems. The main idea is to integrate the Balsa language and tools in a system level design environment, where Balsa will be seen just as any other language, in order to allow mixed descriptions of synchronous and asynchronous circuits. Consequently, we will generate a system level design tool that is able to handle IP blocks referring to Balsa, Verilog, VHDL and SystemC specifications with an open plug-in interface to easily accept new languages and tool flows. Our GALS design flow will be based on an open format for mixed synchronous-asynchronous IPs in order to consolidate asynchronous IPs dissemination and reuse. The IP format will be able to describe hardware/software entities at multiple levels of abstraction in multiple languages (SystemC, C, Verilog, VHDL, Balsa, etc.), with both synchronous and asynchronous interfaces. We will establish a library of the important GALS components scalable to different applications. This library of GALS interface IPs should enable a plug-andplay type of approach when designing a system with a heterogeneous mixture of synchronous and asynchronous IPs. It is planned to investigate the possibilities for lowering EMI and power with a GALS methodology. We plan to build an abstract model of the GALS circuit and generate the optimal algorithms for reducing the EMI. Additionally, the developed EMI reduction algorithms will be evaluated theoretically and in practice. We will investigate application of dynamic voltage and frequency scaling in conjunction with GALS in order to reduce power in comparison with standard synchronous low-power solutions. The project also intends to deploy the power-aware nature of GALS technology to bring NoC architectures to maturity. GALS-based NoCs would allow the synchronous design of network nodes at their optimum clock frequency, while facilitating asynchronous communication between modules.

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The project intends to consolidate GALS-NoCs as the enabling technology for widespread adoption of network-centric architectures for highly integrated MPSoC platforms in the nanometer regime.

Key Issues Practical IC implementations will be the key issue of the GALAXY project, as it will provide the best way to evaluate the developed GALS solutions and compare them against traditional circuits. We plan to have two separate ASIC implementation runs within the GALAXY project. The first chip will be specifically designed to be a test chip containing structures to evaluate GALS components. This chip will be used to evaluate the advantages of GALS-based design in reducing power consumption, reducing EMI, and improving process variation tolerance. Finally, we plan to build a complex target system using both a standard synchronous CMOS design flow and the GALS design flow developed in this project in a cutting edge 40 nm CMOS process. Selecting a suitable target platform for the second design is important. Since wireless communication is an application domain which is gaining more and more popularity and which poses significant technical challenges to system designers (performance- and power-wise), and since several group members have prior experience in this field, we will consider target platforms from this field. For example, one candidate will be an accelerator for an OFDM baseband processor with data rates up to 1 Gbps for communication systems in 60 GHz range which is currently under development in IHP.

Expected Impact The realization of the ambitious goals defined by the project will result in improved design-to-market time, fewer design iterations and finally in a lower cost of the system design process. The GALAXY project has ambition to further confirm the leadership of Europe in a GALS system-on-chip design and CAD support. This leadership is already established with previous realization of complex asynchronous and GALS demonstrators and tools. The involvement of our industrial partners will guarantee the success of the project and the impact to the embedded system design methodology and practice. SYNCHRONOUS BLOCK 1

SYNCHRONOUS BLOCK 2

data

SYNCHRONOUS BLOCK 3

Handshake signals

Embedded Systems Design RESEARCH PROJECTS

INTERESTED INTER-operable Embedded Systems Toolchain for Enhanced rapid Design, prototyping and code generation INTERESTED aims at realizing the first European-wide tool reference development ever, validated by Major Tool Users thru real life industrial validators, ensuring an integrated, lower cost, highly dependable, safe and efficient development process for the benefit of critical European industries) KEYWORDS: refrence tool suite , interoperability, integration, safety and dependability of embedded systems.

At A Glance: INTERESTED

Main Objectives

INTER-operable Embedded Systems Toolchain for Enhanced rapid Design, prototyping and code generation

The INTERESTED project has been built to exactly match the goals defined within the Objective ICT-2007-3.3b (“Suites of interoperable design tools for rapid design and prototyping”), namely creating a reference and open interoperable embedded systems toolchain, fulfilling the needs of the industry for designing and prototyping embedded systems. This project regroups a consortium of leading edge European embedded systems Tools Vendors, all being

Project Coordinator: Name: Eric Bantegnie Institution: Esterel Technologies Email: [email protected] Project website: www.interested-ip.eu

INTERESTED will focus on delivering and integrated embedded systems toolchain

high tech innovative SMEs, as well as European Major Tool Users representing several industries that are both integrating massively embedded systems and contributing to the overall competitiveness of Europe: Aerospace, Automotive, Railway and Transportation and Energy.

Partners: ESTEREL Technologies SA (France) AbsInt Angewandte Informatik (Germany) TTTech Computertechnik AG (Austria) Evidence S.r.l. (Italy) Symtavision GmbH. (Germany) UNIS, spol. s r.o.(Czech republic) Artisan Software Tools Ltd (United Kingdom) Sysgo AG (Germany) Airbus SAS (France) Magneti Marelli Powertrain SpA (Italy) Commissariat à l’Energie Atomique (France) Thales SA (France) Siemens AG (Germany) Duration: 36 months Start: 2008.01.01 Total Cost: 7364057€ EC Contribution: 5388995€ Contract Number: INFSO-ICT-214889

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Technical approach The method followed in the project is to: x

Integrate the requirements of Major Tool Users of embedded systems tools to realize a reference and open interoperable embedded systems tool-chain, having in mind a broad socio-economic benefit for the European citizens, the performance of Embedded Systems generating long term societal benefits such as increased aircraft and transportation safety, reduced fuel and energy consumption and competitiveness of key European industries.

x

Cover the full scope of Embedded Systems and Software engineering disciplines, spanning:

x

o

System and Application Software Design Modelling, Verification and Code Generation

o

Networking and RTOS execution platforms, Hardware-Dependent Software verification and Code Generation

o

Timing analysis and code execution verification

Validate the use of the INTERESTED tool-chain on real-life demonstrators (the “Industrial Validators”) representing key application domains for European leading industries: Aerospace, Automotive, Railway and Transportation and Energy.

From a technical standpoint, the INTERESTED reference Tool-Chain will integrate, using standards-based integration and interoperability solutions the following tools: x

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Architecture definition tools (UML/SysML tools from ARTISAN Software Tools as well as demonstrated interoperability with Open Source UML, SysML and AADL Modellers such as TOPCASED and Papyrus provided as interoperability demonstration case by Airbus and CEA (a convergence process is being initiated between these 2 tools and is funded outside of INTERESTED).

x

Embedded GUI design tools (SCADE Display from Esterel Technologies),

x

Application Software Design, Verification and Code Generation tools (SCADE Suite from Esterel Technologies),

x

Hardware-Dependent Software Design and Code Generation tools (Processor Expert from UNIS)

x

Networking Infrastructure support tools (FlexRay and TTP tools from TTTech)

x

RTOS execution platforms (PikeOS from SYSGO as well as demonstrated interoperability with domain specific execution platform such as the OASIS environment from CEA)

x

WCET and Stack Analysis Tools (aiT from ABSINT)

x

Schedulability analysis tools (SymTA/S from Symtavision and RT-Druid from Evidence), as well as numerical precision analysis tools (Fluctuat from CEA)

Key Issues Major Tool Users (AIRBUS, THALES, MAGNETI MARELLI, SIEMENS RAIL TRANSPORTATION and CEA) will bring their requirements for the Tool-Chain content, structuring, features, interoperability architecture and characteristics, as well as real-life demonstration cases for their use of relevant parts of the tool-chain and interoperability demonstration cases with inhouse or open source tools. They will ensure, thru appropriate metrics defined during the progress and evaluation of the cost reduction target that the INTERESTED reference tool-chain will enable. Tool Vendors within the INTERESTED project have established a preliminary list of Integration Technical Business Cases for the integration of their tools, will review them against the Major Tool Users requirements and will ensure that all selected Integration Technical Business Cases specifications and developments are architected in an interoperable way with 3rd party tools, such interoperability being verified within the Industrial Validators. One Major Tool User (CEA), due to its mission, enjoying strong links with academics partners, will steer an Academic Advisory Board to make sure that innovative and proper advice from academic Networks of Excellence such as ARTIST2 are clearly taken into account.

Expected Impact In summary, INTERESTED aims at realizing the first European-wide tool reference development environment ever, validated by Major Tool Users through real-life Industrial Validators, ensuring an integrated, lower cost, highly dependable, safe and efficient development process to the benefit of critical European industries. INTERESTED will thus contribute securing Europe’s competitiveness and independence in the critical Embedded Systems field.

Embedded Systems Design RESEARCH PROJECTS

MADES Model-based methods and tools for Avionics and surveillance embeddeD SystEmS MADES aims to develop the elements of a full-fledged model-driven approach for the design, validation, simulation, and code generation of complex embedded systems to improve the current practice in the field. KEYWORDS: Embedded Systems Design, Advanced Model-Driven Development.

Main Objectives

At A Glance: MADES Model-based methods and tools for Avionics and surveillance embeddeD SystEmS

Project Coordinator: Name: Alessandra Bagnato Institution: Txt e-solutions – Research Division Email: [email protected]

Corporate

Project Technical Manager: Name: Andrey Sadovykh Institution: Softeam Email: [email protected] Project website: www.mades-project.org Partners: TXT e-solutions (IT) Softeam (FR) University of York (UK) Politecnico di Milano (IT) The Open Group (UK) EADS Deutschland GmbH (DE) Duration: 30 months Start: 2010.02.01 Total Cost: € 3623931 EC Contribution: € 2450000

The project covers all the phases of the development process: from design to code generation, validation and deployment. Design activities will exploit a dedicated language developed on top of the OMG standard MARTE (Modeling and Analysis of Real-time and Embedded systems), and foster the reuse of components by annotating them with properties and constraints to ease their selection and enforce overall consistency. Validation activities will comprise the verification of key properties of designed artifacts and of the transformations used throughout the development process, and also the closedloop simulation of the entire system.

MADES will focus on a full-fledged modeldriven approach for the design, validation, simulation, and code generation for Avionics and surveillance embeddeD SystEmS

Code generation will address both conventional programming languages (e.g., C) and hardware description languages (e.g., VHDL), and will adopt compile-time virtualization techniques to smooth the impact of the diverse elements of modern hardware architectures and cope with their increasing complexity. All these aspects will be fully supported by prototype tools integrated in a single framework, and will be thoroughly validated on real-life case studies in the surveillance and avionic domains. The project also aims to develop a handbook to provide detailed guidelines on how to use MADES tools in the development of embedded systems and promote their adoption.

Contract Number: INFSO-ICT-FP7-248864

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Technical Approach

Key Issues

The MADES technical approach is based on the following: x Adapt and Develop Modelling Languages and Tools for Co-Design of Embedded Systems in the Avionics/Surveillance Domain x Develop Advanced Methods and Tools for Verification and Simulation for the CoDesign x Develop Advanced Methods and Tools for Code and Hardware description CoGeneration x Integrate developed MDE tools in a single framework for the seamless modelling, validation, and code generation x Validate with Case Studies from the Avionics/Surveillance Domains

The ideas of MADES are directly based on the needs for increased help demanded by developers and industry in embedded system design. As the systems that employ embedded software becomes more complex, they tend to contain more errors, and it becomes more relevant to provide tools to aid the developers to overcome the increased difficulties. The project will give a key help in this direction with its development efforts specifically dedicated to RTES (Real Time Embedded Systems). Major players in the Avionics and Surveillance Embedded System domain (Txt e-solutions and EADS) will provide key requirements to achieve projects objectives.

Error! Reference source not found. depicts a preliminary overview of the components to be developed in the project. All tools are plugged into the MADES framework based on Eclipse platform and its EMF based MDD Technologies. SOFTEAM’s CASE Tool implements dedicated MARTE extensions and is integrated with other tools. The Component Repository is used to store and locate generic UML Case Tools system components used for building embedded systems. The Verification and Simulation tools are integrated with the modeller and provide the validation features. The Traceability tool keeps track of changes happening during modelling and model transformations. The Software Code and HDL description generation is insured by Transformation and Generation engine.

MADES expects to achieve impact through:

MADES Integration framework – Eclipse and MDD Technologies Based on EMF Generic UML Case Tool

Verification and Simulation

Components repository