Encapsulated graphene field-effect transistors for air

Encapsulated graphene field-effect transistors for air stable operation Konstantinos Alexandrou, Nicholas Petrone, James Hone, and Ioannis Kymissis Citation: Applied Physics Letters 106, 113104 (2015); doi: 10.1063/1.4915513 View online: http://dx.doi.org/10.1063/1.4915513 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/106/11?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Doping and hysteretic switching of polymer-encapsulated graphene field effect devices Appl. Phys. Lett. 103, 253505 (2013); 10.1063/1.4851956 Unipolar to ambipolar conversion in graphene field-effect transistors Appl. Phys. Lett. 101, 253505 (2012); 10.1063/1.4772493 Self-aligned graphene field-effect transistors with polyethyleneimine doped source/drain access regions Appl. Phys. Lett. 101, 183113 (2012); 10.1063/1.4765658 Simulation study of channel mobility and device performance dependence on gate stack in graphene field-effect transistors Appl. Phys. Lett. 100, 112104 (2012); 10.1063/1.3693410 Influence of moisture on device characteristics of polythiophene-based field-effect transistors J. Appl. Phys. 95, 5088 (2004); 10.1063/1.1691190

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 160.39.55.122 On: Tue, 17 Mar 2015 14:46:48

APPLIED PHYSICS LETTERS 106, 113104 (2015)

Encapsulated graphene field-effect transistors for air stable operation Konstantinos Alexandrou,1,a) Nicholas Petrone,2 James Hone,2 and Ioannis Kymissis1 1

Department of Electrical Engineering, Columbia University, New York, New York 10027, USA Department of Mechanical Engineering, Columbia University, New York, New York 10027, USA

2

(Received 24 February 2015; accepted 6 March 2015; published online 17 March 2015) In this work, we report the fabrication of encapsulated graphene field effects transistors (GFETs) with excellent air stability operation in ambient environment. Graphene’s 2D nature makes its electronics properties very sensitive to the surrounding environment, and thus, non-encapsulated graphene devices show extensive vulnerability due to unintentional hole doping from the presence of water molecules and oxygen limiting their performance and use in real world applications. Encapsulating GFETs with a thin layer of parylene-C and aluminum deposited on top of the exposed graphene channel area resulted in devices with excellent electrical performance stability for an extended period of time. Moisture penetration is reduced significantly and carrier mobility degraded substantially less when compared to non-encapsulated control devices. Our CMOS compatible encapsulation method minimizes the problems of environmental doping and lifetime performance degradation, enabling the operation of air stable devices for next generation C 2015 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4915513] graphene-based electronics. V

Graphene, a 2D dimensional sheet of carbon first isolated in 2004 (Ref. 1) by Geim and Novoselov, has attracted immense scientific interest due to its excellent electrical,2–4 mechanical,5,6 and optical7 properties. Specifically, recent improvements on the scalable synthesis of graphene8,9 along with the demonstration of FETs with very high field effect mobility10,11 and impressive RF performance12,13 pave the way to the integration of graphene devices in the post-silicon era. However, being a true 2D material with a large surface to volume ratio means that the surrounding environment can directly affect the electronic properties of graphene due to the chemical adsorbents that can cause unintentional doping.14 In order to achieve record of high electron mobility or cut off frequency, graphene devices must be isolated from the environment, often operating under ultra high vacuum conditions and at temperatures as low as 5 K. When a back gated graphene transistor is exposed to the ambient environment, water molecules and oxygen will get adsorbed, leading to a p-doped graphene surface, where the Dirac point shifts to higher gate values and the electron conduction gets suppressed even further.15 Increased doping results in reduced performance and reliability of the fabricated graphene devices, limiting their use in practical applications where high vacuum and low temperatures conditions cannot be met. Consequently, characterizing and understanding the effect of the surrounding environment on graphene as well as developing an encapsulation method that will limit undesirable doping are of prominent importance. Various methods, such as inserting a fluoropolymer between graphene and the gate dielectric,16 capping graphene with a thin oxide layer,17,18 or encapsulating the graphene channel with an organic semiconductor,19 have shown that the electrical characteristics and stability of graphene field effects transistors (GFETs) can be further improved when isolated from the environment. In addition, a)

[email protected]

0003-6951/2015/106(11)/113104/4/$30.00

graphene encapsulated between hexagonal boron nitride (hBN) flakes has been demonstrated,20 exhibiting exceptional air stability while making it insusceptible to the surrounding environment. However, some of these methods are impractical for being integrated in the CMOS fabrication process as they are based on the use of mechanical exfoliation, while others don not achieve prolonged insulation from the environment for more than few weeks. We have developed an encapsulation method that is based on the deposition of a thin parylene-C and aluminum layer on top of the exposed graphene that resolves the aforementioned problems. Parylene-C belongs to a family of polymers that has already been used as a water/moisture barrier for organic light emitting diode (OLED) passivation21 and as coating for flexible electronics applications.22 In addition, the combination of parylene-C and aluminum has been reported to provide excellent passivation and stability of air-sensitive organic semiconductor devices.23 Using our encapsulation method on GFETs results in devices that exhibit reduced performance degradation or unintentional doping from the atmosphere even after being exposed to air for more than two months. In contrast, devices that had no encapsulation layer suffered from major performance and mobility degradation after being exposed to ambient atmosphere for a period of a few days. We believe that developing a CMOS compatible passivation/encapsulation process for GFETs is crucial for the evolution of graphenebased integrated circuits. Single layer CVD grown graphene on 20 lm copper foils was transferred on top of a heavily p-doped Si substrate with a 300 nm thermally grown SiO2. A thin layer of poly(methyl methacrylate) (PMMA) acting as a supporting layer was spin coated on top of the Cu foil at 3000 rpm for 45 s, followed by an annealing step at 145 C for 2 min. In order to etch unwanted graphene from the backside of the Cu foil, reactive ion etching (RIE) was used for 20 s at 50 W. Polydimethylsiloxane (PDMS) stamps were prepared, cured

106, 113104-1

C 2015 AIP Publishing LLC V


113104-2

Alexandrou et al.

Appl. Phys. Lett. 106, 113104 (2015)

at 80 C for 90 min, and placed on top of the PMMA layer as an extra supporting layer. We developed a slightly modified transfer process compared to the standard PMMA method,24 where adding PDMS stamps on top of PMMA gives us the advantage of being able to transfer graphene with few defects and low impurity doping. The whole Cu foil/ graphene/PMMA/ PDMS stack was inserted in ammonium persulfate (APS) copper etchant solution for 5 h, followed by an overnight rinsing step in deionized (DI) water, and a final 24 h drying step before being transferred. Si/SiO2 substrates were previously cleaned by Piranha to eliminate possible organic contaminants on the surface. Substrates were heated at 180 C as the PDMS/PMMA/graphene stack was placed carefully on top, promoting adhesion between graphene and the substrate. Substrates were then submerged in a chloroform bath for 2 h in order to dissolve PMMA and rinsed in isopropyl alcohol (IPA). Thermally evaporated Cr/Au (3 nm/50 nm) was deposited using a shadowmask for defining the drain/source contacts. Shadowmasking was used in our process in order to reduce the possible unwanted contamination/doping of graphene, as is the case when using a standard lithographic process.25 1.25 lm of parylene-C was deposited covering the graphene channel area, followed by a thermally evaporated 50 nm aluminum layer. Finished devices were then electrically characterized using the Keithley 4200 Parameter Analyzer and a 3-probe setup. Figures 1(a) and 1(b) show the schematic cross-section of the fabricated device and the Raman spectra of the transferred single layer graphene (SLG) on top of Si/SiO2 substrate. The absence of a D-peak

indicates the high crystalline quality of our CVD grown graphene, whereas the G/2D ratio clearly suggests the monolayer nature of the transferred graphene. Transfer characteristics of the fabricated device without any encapsulation layer are shown on Figure 2(a). The Dirac point of the as-fabricated device is at 22.3 V with a field effect mobility (l ¼ Lgm/WVdsCox) of 877 cm2/Vs showing clear p-doped behavior in air ambient environment. This p-doped behavior is in accordance with previous reports where functional groups,26 adsorbents,27 and trapped water molecules between graphene and substrate can cause this p-doping effect. Furthermore, measurements taken a week after the device was left in air clearly show the positive Dirac shift expected from additional p-doping of graphene due to adsorbed molecules. In the absence of any passivation/encapsulation layer, the Dirac point was shifted to gate voltage values higher than 60 V and the field effect mobility degraded to 512 cm2/Vs, a substantial difference from values attained immediately after fabrication. Many studies so far have indicated that an annealing step on a fabricated device28,29 is crucial in order to recover the lost performance caused by the unintentional p-dopants. As we show in Figure 2(b), annealing the device at 180 C for 1 min on a hotplate was enough to desorb the p-dopants on the surface and set the performance of the device to its as-fabricated levels. Although annealing is definitely one way to reset the device

FIG. 1. (a) Schematic cross-section of the encapsulated GFET with a parylene-C/Al encapsulation layer and (b) Raman spectra of SLG transferred on top of Si/SiO2 substrate using a 532 nm laser.

FIG. 2. (a) Transfer characteristics of the non-encapsulated GFET before and after 1 week of air exposure and (b) effect of hotplate annealing at 180 C to the air exposed non-encapsulated device.


113104-3

Alexandrou et al.

performance to the as-fabricated state, it has limited practical use in real-world device applications and does not offer a permanent solution since the device will again return to more heavily doped state when left in air. Figure 3(a) shows the effect of encapsulation when 1.25 lm of parylene-C was deposited on top of graphene. The as-fabricated device initially had a Dirac point at 14.1 V with l ¼ 1860 cm2/Vs. After being exposed to air for a week, the Dirac point shifted to 32 V with a mobility of 1206 cm2/Vs. Performance degradation of our device continued, and after two full weeks of air exposure the Dirac point shifted to values higher than 60 V, and to l less than 965 cm2/Vs. A DVDirac of 50 V after 2 weeks of air exposure clearly suggests that an encapsulation layer consisting only from parylene-C is not enough to fully passivate the device from the surrounding environment. In order to enhance the passivation properties even further, we thermally evaporated a 50 nm MoO3 layer on top of the parylene-C. MoO3 belongs to the metal oxide family of materials that exhibit great stability in air and have been used in OLED fabrication.30 Figure 3(b) shows the effect of the parylene-C/MoO3 encapsulation layer deposition on top of graphene channel area. An initial VDirac of 19.1 V shifted to values of 26 V and 35 V after 2 and 4 weeks of air exposure, a substantial improvement over the parylene-C encapsulation layer that was characterized before. The parylene only encapsulated device exhibited a VDirac shift of 50 V after 2 weeks of air exposure, whereas the combination of parylene-C/MoO3 encapsulated device exhibited a much

FIG. 3. (a) Id-Vgs transfer characteristic of devices encapsulated with parylene-C layer of 1.25 lm after 1 and 2 weeks of air exposure and (b) transfer characteristic of GFETs with an encapsulation layer consisting of 1.25 lm parylene-C/50 nm MoO3 after 2–4 weeks of ambient air exposure.

Appl. Phys. Lett. 106, 113104 (2015)

improved VDirac shift of 6.9 V. In addition, l of the asfabricated device fell from 593 cm2/Vs to 507 cm2/Vs (14.5% decrease) and to 436 cm2/Vs (26.48% decrease) after 2 and 4 weeks in air, respectively, a much improved behavior when compared to the parylene-only device that saw its mobility degrade for more than 48% (from 1860 cm2/Vs to 965 cm2/Vs). These results clearly indicate the importance of a second layer on top of parylene-C to further improve the passivation of graphene from the surrounding environment. Further optimization of the encapsulation layer resulted in replacing MoO3 with an aluminum layer that we deposited on top of parylene-C. In agreement with previous studies, aluminum reacts with atmospheric oxygen when exposed to air, forming a thin layer of Al2O3 (Ref. 31) that further inhibits the penetration of oxygen into the material. The oxygen blocking property of aluminum is highly desirable in our devices, where in conjunction with the parylene-C layer we expect improved air stability. Figure 4 shows the transfer characteristics of GFETs fabricated with an encapsulation layer consisting of 50 nm Al deposited on top of 1.25 lm of parylene-C. The device exhibits a VDirac shift of 1 V when exposed to air for two weeks, while l deviates little from as-fabricated values. Measurements after two months of ambient air exposure reveal that the device is still performing very close to the initial performance metrics with a DVDirac of 8.2 V and l of 964 cm2/Vs (a 5.5% decrease from the as-fabricated value). GFETs with a parylene-C/Al passivation layer performed significantly better than the other fabricated devices, with promising air stability operation under months of air exposure and without the need for an annealing step. In summary, air stable operation of GFETs was achieved from the development of a CMOS compatible encapsulation method. Fabricated devices exhibited very little performance and mobility degradation over a long period of time, with reduced electron-hole conduction asymmetry and minimal Dirac voltage shift. Our results show that the combination of parylene-C and aluminum thin films deposited on top of the exposed graphene area are an excellent water/oxygen barrier fully compatible with the transistor fabrication process. Understanding the influence of the surrounding environment

FIG. 4. Id-Vgs of the device encapsulated with 1.25 lm parylene-C/50 nm Al after being exposed to ambient air conditions for as long as 2 months.


113104-4

Alexandrou et al.

on graphene devices, as well as being able to passivate them, is necessary for the wider adoption and further optimization of graphene based electronics. This material was based upon work supported by the NSF MRSEC program through Columbia in the Center for Precision Assembly of Superstratic and Superatomic Solids (DMR-1420634) and the Defense Threat Reduction Agency (DTRA) under HDTRA1-11-0022. 1

K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov, Science 306(5696), 666 (2004). 2 Y. Zhang, Y.-W. Tan, H. L. Stormer, and P. Kim, Nature 438(7065), 201 (2005). 3 A. K. Geim and K. S. Novoselov, “The rise of graphene,” Nat. Mater. 6(3), 183 (2007). 4 P. Avouris, Nano Lett. 10(11), 4285 (2010). 5 C. Lee, X. Wei, J. W. Kysar, and J. Hone, Science 321(5887), 385 (2008). 6 K. S. Kim, Y. Zhao, H. Jang, S. Y. Lee, J. M. Kim, K. S. Kim, J.-H. Ahn, P. Kim, J.-Y. Choi, and B. H. Hong, Nature 457(7230), 706 (2009). 7 R. R. Nair, P. Blake, A. N. Grigorenko, K. S. Novoselov, T. J. Booth, T. Stauber, N. M. R. Peres, and A. K. Geim, Science 320(5881), 1308 (2008). 8 B. Sukang, H. Kim, Y. Lee, X. Xu, J.-S. Park, Y. Zheng, J. Balakrishnan, T. Lei, H. Ri Kim, Young II Song et al., Nat. Nanotechnol. 5(8), 574 (2010). 9 Z. Yan, J. Lin, Z. Peng, Z. Sun, Y. Zhu, L. Li, C. Xiang, E. Lo€ıc Samuel, C. Kittrell, and J. M. Tour, ACS Nano 6(10), 9110 (2012). 10 S. V. Morozov, K. S. Novoselov, M. I. Katsnelson, F. Schedin, D. C. Elias, J. A. Jaszczak, and A. K. Geim, Phys. Rev. Lett. 100(1), 016602 (2008). 11 K. I. Bolotin, K. J. Sikes, Z. Jiang, M. Klima, G. Fudenberg, J. Hone, P. Kim, and H. L. Stormer, Solid State Commun. 146(9), 351 (2008). 12 Y.-M. Lin, C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu, A. Grill, and Ph. Avouris, Science 327(5966), 662 (2010).

Appl. Phys. Lett. 106, 113104 (2015) 13

L. Liao, Y.-C. Lin, M. Bao, R. Cheng, J. Bai, Y. Liu, Y. Qu, K. L. Wang, Y. Huang, and X. Duan, Nature 467(7313), 305 (2010). 14 H. Wang, Y. Wu, C. Cong, J. Shang, and T. Yu, ACS Nano 4(12), 7221 (2010). 15 C. M. Aguirre, P. L. Levesque, M. Paillet, F. Lapointe, B. C. St-Antoine, P. Desjardins, and R. Martel, Adv. Mater. 21(30), 3087 (2009). 16 W. C. Shin, S. Seo, and B. J. Cho, Appl. Phys. Lett. 98(15), 153505 (2011). 17 P.-H. Ho, Y.-C. Yeh, D.-Y. Wang, S.-S. Li, H.-A. Chen, Y.-H. Chung, C.-C. Lin, W.-H. Wang, and C.-W. Chen, ACS Nano 6(7), 6215 (2012). 18 A. A. Sagade, D. Neumaier, D. Schall, M. Otto, A. Pesquera, A. Centeno, A. Zurutuza, and H. Kurz, Nanoscale 7, 3558 (2015). 19 T.-J. Ha, D. Akinwande, and A. Dodabalapur, Appl. Phys. Lett. 101(3), 033309 (2012). 20 A. S. Mayorov, R. V. Gorbachev, S. V. Morozov, L. Britnell, R. Jalil, L. A. Ponomarenko, P. Blake, K. S. Novoselov, K. Watanabe, T. Taniguchi, and A. K. Geim, Nano Lett. 11(6), 2396 (2011). 21 A. P. Ghosh, L. J. Gerenser, C. M. Jarman, and J. E. Fornalik, Appl. Phys. Lett. 86(22), 223503 (2005). 22 T.-N. Chen, D.-S. Wuu, C.-C. Wu, C.-C. Chiang, Y.-P. Chen, and R.-H. Horng, Plasma Processes Polym. 4(2), 180 (2007). 23 S. P. Subbarao, M. E. Bahlke, and I. Kymissis, IEEE Trans. Electron Devices 57(1), 153 (2010). 24 A. Reina, H. Son, L. Jiao, B. Fan, M. S. Dresselhaus, Z. Liu, and J. Kong, J. Phys. Chem. C 112, 17741 (2008). 25 J. Fan, J. M. Michalik, L. Casado, S. Roddaro, M. R. Ibarra, and J. M. De Teresa, Solid State Commun. 151(21), 1574 (2011). 26 R. Wang, S. Wang, D. Zhang, Z. Li, Y. Fang, and X. Qiu, ACS Nano 5(1), 408 (2011). 27 E. H. Hwang, S. Adam, and S. Das Sarma, Phys. Rev. B 76(19), 195421 (2007). 28 Z. Cheng, Q. Zhou, C. Wang, Q. Li, C. Wang, and Y. Fang, Nano Lett. 11(2), 767 (2011). 29 H. Sojoudi, J. Baltazar, C. Henderson, and S. Graham, J. Vac. Sci. Technol., B 30(4), 041213 (2012). 30 K. Morii, M. Ishida, T. Takashima, T. Shimoda, Q. Wang, Md. K. Nazeeruddin, and M. Gr€atzel, Appl. Phys. Lett. 89(18), 183510 (2006). 31 Wm. H. Krueger and S. R. Pollack, Surf. Sci. 30(2), 263 (1972).
