methods such as window optimization and template matching are being applied. Template matching algorithms explore the circuits for gate cascades that can ...
Exact Template Matching Using Boolean Satisfiability Nabila Abdessaied∗
Mathias Soeken∗§
∗ Institute
Robert Wille∗§
Rolf Drechsler∗§
of Computer Science, University of Bremen, 28359 Bremen, Germany Systems, DFKI GmbH, 28359 Bremen, Germany {nabila,msoeken,rwille,drechsle}@informatik.uni-bremen.de
§ Cyber-Physical
Abstract—Reversible logic is an emerging research area that has shown promising results in applications such as quantum computing, low power design, and optical computing. Since the synthesis of minimal circuits is a cumbersome task, many synthesis algorithms apply heuristics and can therefore not provide a minimal solution. As a consequence, post synthesis methods such as window optimization and template matching are being applied. Template matching algorithms explore the circuits for gate cascades that can be replaced by smaller ones using a special class of identity circuits, so called templates. The determination of cascades applicable for substitution is the bottleneck of the template matching algorithm and problem-solving methods have been proposed in the recent past. Since these algorithms are based on heuristics, it cannot be ensured that a matching cascade can always be found. In this paper, we propose a new approach that determines matching cascades based on Boolean satisfiability and therefore ensures that these cascades are always found if they exist. Experimental results demonstrate that template matching yields smaller circuits when applying the new method for cascade determination.
I. I NTRODUCTION Reversible logic is an emerging technology in the domain of quantum computing [1], [2], [3], low power design [4], [5], optical comuting [6], as well as nanotechnologies [7]. In reversible circuits, all computations are performed in an inverted manner which provides new promising enhancements for computation technologies. Motivated by the benefits brought by these circuits, researchers started to develop new design methods. Several synthesis approaches have been proposed to determine a circuit realization for a given function. Significant improvements and achievements [8], [9], [10], [11] have been made since the truth table based approach has taking place. However, the majority of the synthesis approaches do not guarantee optimal realizations, in fact, the algorithms that do guarantee an optimal solution (e.g. [12]) are only applicable to small circuits of about 4 to 6 lines. As a result, several post synthesis optimization approaches [9], [13] have been proposed to minimize a given circuit after it has been synthesized. The template matching algorithm explained in [9] is one of these optimization techniques. Given a set of templates which is a special class of identity circuits, the algorithm tries to determine sub-circuits
that match a part of a template. In this case, the determined sub-circuit can be replaced with the inverted remaining part of the template due to reversibility. If the remaining part is smaller, the overall circuit size can be reduced. The efficiency of the template matching algorithm highly depends on the strategy used for matching the template in a circuit. Since the considered search space that should be inspected in order to find a match for a template is usually very large, many heuristic approaches have been investigated that work efficiently but cannot guarantee that a matching subcircuit can be found if it exists. To overcome this limitation, we propose a new approach that exploits Boolean satisfiability techniques allowing an exhaustive but yet efficient determination of cascades according to a given set of templates. For this purpose, the search for a cascade is formulated as a decision problem and encoded as a Boolean formula that is afterwards solved using an SMT solver. If the instance is satisfiable, the matching cascade can be replaced by the second half of the template. Otherwise, it can be concluded that the template cannot be used to further reduce of the circuit cost. We have implemented the algorithm and compared it to the search method presented in [9]. Experimental results show that cost reductions of up to about 60% compared with respect to the initial circuit and up to 28% with respect to the method in [9] can be achieved. The remainder of the paper is organized as follows. Section II introduces the basics of reversible logic, the template matching algorithm, and SMT. In Section III the general structure of our approach is explained, while details on the SMT encoding are provided in Section IV. Experimental results are given in Section V and the paper is concluded in Section VI. II. BACKGROUND A. Reversible Circuits A Boolean function is reversible if it maps each input assignment to a distinct output assignment. As a result, such a function must have the same number of input and output variables X := {x1 , . . . , xn }. A circuit realizing a reversible function is a cascade of reversible gates. In the literature, several types of reversible gates have been introduced. Besides the Fredkin gate [14] and the Peres gate [15], multiple controlled
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(a) Reversible gate Fig. 1.
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Reversible circuitry
Toffoli gates [16] are widely used. In this paper we consider only Toffoli gate circuits. A Toffoli gate has the form T(C, t) with a set of control lines C = {xi1 , · · · , xik } ⊂ X and a target line t ∈ X \ C. C may be empty. The target line t is inverted if and only if all control lines are assigned 1, i.e. a gate maps an input assignment (x1 , . . . , t = xj , . . . , xn ) to (x1 , . . . , xi1 ∧ xi2 ∧ · · · ∧ xik ⊕ xj , . . . , xn ). Quantum cost are often used to measure the cost of a reversible gate. Every reversible gate can be transformed into a sequence of elementary quantum gates [17] where each elementary gate has a quantum cost of one. Example 1: Fig. 1(a) shows a Toffoli gate with two control lines. The control lines are denoted by •, while the target line is denoted by . The annotated values demonstrate the computation of the gate for a given input assignment. Fig.1(b) shows different Toffoli gates in a cascade forming a reversible circuit.
⊕
B. Template Matching Procedure Templates have initially been proposed in [9] and their definition has been adjusted several times in the past. The current widely accepted definition states that a template is an identity circuit with m gates such that each sub-circuit of size less than d m 2 e cannot be reduced by another template. Furthermore, a template consists of two different line types which we call C-lines and T-lines and which should not be mistaken for control lines and target lines of a gate (cf. Fig. 2). A C-line of a template is a line in which all gates only have control lines but no target lines, all other lines are T-lines. This separation is of use since any C-line can be duplicated, removed, or replaced without changing the functionality of the circuit. This is illustrated by means of Figs. 3(a), 3(b), and 3(c), respectively. Further, the order of the gates can be rotated being wrapped at the circuit boundaries, again without changing the functionality. This is illustrated in Fig. 3(d).
b c d e
a b c d e
b c d e (b) Removal
a b c d e (d) Rotation
Fig. 3.
Template disposition
Since a template is an identity circuit it can be split anywhere in the middle and the left part equals the inverse of the right part and vice versa. The template matching algorithm is applied in order to reduce the circuit size or its costs. It takes a circuit and tries to find sub-circuits in it that match a part of a template. If that part is longer or more expensive than the remaining part the sub-circuit is replaced by the inverse of it. The matching procedure tries to find the first gate and then subsequently looks for the other gates which do not need to be necessarily adjacent. Using the moving rule, gates can be moved in the circuit without changing the circuit’s functionality [9]. Example 2: Fig. 4 illustrates the basic template matching algorithm. It shows a template in the lower left corner with a left and a right part. A sub-circuit matching the left part of the template is found in the original circuit, hence, this subcircuit can be replaced with the inverse of the right part of the template yielding a smaller simplified circuit of less cost. The degree of optimization in template matching depends on the considered templates that are used in the process and the search method for finding matching sub-circuits. The latter task is the most complex part in the template matching algorithm and not feasible when being applied in an exhaustive manner. In order to determine matching templates, the circuit is rearranged by applying the time consuming moving rule. As a consequence, heuristics are used to find sub-sequences
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that do not guarantee that a sub-circuit is found if it exists. For example, some of them take a circuit and try to match its gates to the template from the input to the output side of a that circuit, other ones apply the search additionally in the reverse direction in order to increase the chances of matching the template in the circuit. C. Satisfiability Modulo Theories Boolean satisfiability (SAT) is a decision problem that determines if the variables of a given propositional formula can be assigned in such a way that the formula evaluates to true. Equally important is to determine whether no such assignments exist, which would imply that the formula is the contradiction. In the latter case, the function is said to be unsatisfiable, otherwise it is satisfiable. Most modern SAT solvers require the formula to be in conjunctive normal form, i.e. a conjunction of clauses which in turn are disjunctions of literals. Satisfiability Modulo Theories (SMT) is also a decision problem but with more complex theories rather than only propositional logic. A detailed introduction is given in [18]. SMT is is about checking the satisfiability of first-order formulas containing operations from various theories such as the Booleans, bit-vectors, arithmetic, arrays, and recursive data-types. SMT solvers are available that handle complex formulas such as Z3 [19], MathSAT [20], Boolector [21], and SWORD [22]. III. G ENERAL I DEA In this work, we are proposing a new search method that determines matching sub-circuits in a circuit given a template while keeping the general concepts for template matching as they have been explained in [9]. Instead of applying heuristics for the search, we suggest an exact and efficient template matching algorithm based on SMT which allows to exhaustively explore the full search space and therefore guarantees that a matching sub-circuit is found if it exists. Fig. 5 outlines the proposed approach. Given a template with m gates and the original circuit, the proposed algorithm creates a Boolean formula encoding the decision problem
whether there exists a sub-circuit in the original circuit that matches the first k gates of the given template. While initially setting k ← m, k is decremented by 1 as long as the Boolean formula is unsatisfiable. If the formula is satisfiable the matching sub-circuit can be extracted from the satisfying assignment that is returned from the SMT solver. The template length k is only decreased as long as the left part of the template is larger in cost than the right one. IV. E NCODING U SING SMT This section describes the proposed approach in detail. The encoding as a decision problem is explained by listing all constraints that are necessary for searching a correct match of a given template in a circuit. A. Decision Problem The overall decision problem can be stated as follows. Let G = g1 · · · gd be a circuit of n lines and T = g10 · · · gd0 0 be a template of n0 lines with gj = (Cj , tj ) and gi0 = (Ci , ti ) for j = 1, . . . , d and i = 1, . . . , d0 , respectively. The considered lines are defined over the variables {x1 , . . . , xn } and {x01 , . . . , x0n0 }, respectively. Can the first k ≤ d0 gates of the template T be matched in G, i.e. can positions m1 , . . . , mk in G be found such that the gates can be moved together and resemble the first k gates of T . Notice that also the order of lines in the template does not necessarily need to match the original order of lines in the circuit. As a result, besides the matching positions m1 , . . . , mk also a line reordering l1 , . . . , ln0 is part of the solution, if the template can be matched. Example 3: Figs. 6(a) and 6(b) show a circuit and a template, respectively. The first k = 4 gates of the template can be matched to the gates in the circuit at positions m1 = 3, m2 = 4, m3 = 5, and m4 = 6 when a line mapping l1 = 1, l2 = 3, l3 = 2, and l4 = 4, i.e. x1 7→ x01 , x2 7→ x03 , x3 7→ x02 , and x4 7→ x04 . B. Gate Positions and Line Mapping The variables m1 , . . . , mk and l1 , . . . , ln0 represent gate and line indexes in the intervals [1, d] and [1, n0 ], respectively. A one-hot encoding is used for all these variables, i.e. m ~ i ∈ IBd
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= 1001100 = 0010010 = 0110111 = 1000001 Fig. 7.
= 0000001 = 1001000 = 0000000 = 0110110
the encoding we assume that the template can be extended to at most n lines such that it fits the circuit. Also, let us assume that the template has τ T-lines. Then the first n − τ circuit lines for the template are defined as
Circuit encoding
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c~1 0 = c˜0 ∨ c˜1 ∨ c˜2 c~2 0 = c˜0 ∨ c˜1 ∨ c˜2 c~3 0 = 10010 c~4 0 = 00000 Fig. 8.
and = 00000 = 00000 = 01001 = 10110
0 n − τ are encoded in the exact same manner as for the original circuit lines. Example 5: The encoded bit-vectors for the circuit lines of the template from Fig. 6(b) are illustrated in Fig. 8. Notice that the order of the C-lines as it is given in Fig. 6(b) does not matter anymore and is encapsulated in the c˜j variables.
Wk
~ = with M ~ i being the bit-mask containing all position i=1 m indexes. The line mapping variables do not have to follow an order, however all bit-vectors need to be one-hot encoded and they must all differ, i.e.
0 t~i ∈ IBk
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0 tˇj @ ~li = ~ci @ m ~j
with i = 1, . . . , n and j = 1, . . . , k. Taking the control lines, that is the formula on the left hand side, it means the following. Assuming there is a control line in the j th gate of the template at the line where line i maps to. Then, there must also be a control line in the j th gate chosen by the mapping m ~ j in the original circuit at line i and vice versa. The same applies for target lines. Notice that the fact that we have vertical and horizontal encodings for template and circuit gates plays a key role in this encoding.
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Moving rule graph for circuit in Fig. 6(a)
E. Moving Rule The encodings given so far are not sufficient yet, since at the current state arbitrary gates in the original circuits can be matched although it might not be possible to move them together. As a consequence, the moving rule needs to be encoded into the SMT instance as well. In order to have a formal representation of the moving rule, we are making use of the moving rule graph that has been introduced in [23]. In a moving rule graph each vertex represents a gate of the circuit and two gates are connected by an edge if and only if the gates cannot be interchanged by moving. Example 6: The moving rule graph for the circuit in Fig. 6(a) is depicted in Fig. 9. We write gi < gj if gj cannot be moved before gi and gate gi cannot be moved past gj . Since the moving rule is transitive, gi < gj if and only if there exists a path between the vertex representing gi and the vertex representing gj in the moving rule graph. This leads to the final constraint which ensures the moving capabilities. For all 0 < i < j < k ≤ d such that gi < · · · < gj < gk and there is no j 0 such that gi < gj 0 < gk , add the constraint ~ [i] ∧ M ~ [k] ⇒ M ~ [j]. M These constraints can easily be generated with the help of the moving rule graph. Example 7: Given the moving rule graph in Fig. 9, the extracted constraints are as follows: ~ [1] ∧ M ~ [7] ⇒ M ~ [2] M ~ [1] ∧ M ~ [7] ⇒ M ~ [5] M ~ [1] ∧ M ~ [7] ⇒ M ~ [6] M ~ [1] ∧ M ~ [6] ⇒ M ~ [4] M ~ ~ ~ ~ ~ ~ [6] M [1] ∧ M [4] ⇒ M [3] M [3] ∧ M [7] ⇒ M ~ ~ ~ ~ ~ ~ [6] M [3] ∧ M [6] ⇒ M [4] M [4] ∧ M [7] ⇒ M V. E XPERIMENTAL R ESULTS The proposed approach has been implemented in C++. In order to read the reversible circuits as well as the templates, we used the open source toolkit for reversible circuit design RevKit [24]. The SMT problem, i.e. the template matching problem is encoded using the metaSMT [25] framework which provides the use of SAT and SMT solvers directly over its API through the language. Different solvers can be used within the metaSMT framework, for our experiments the Boolector [21] SMT solver turns out to be the most efficient one. The approach has been evaluated on a Dual-Core AMD Processor with 4 GB of main memory. We used circuits
provided in RevLib [26] as benchmarks. We have compared our approach to the one proposed in [9] and used the same set of templates that is presented in the work. Table I summarizes the obtained results for the conducted experiments. The first three columns give the name of the initial not optimized circuits as well as its number of gates and quantum cost (QC). In the following columns, the obtained results for the heuristic template matching approach and the proposed approach are presented. For each the resulting number of gates, the quantum cost, the run-time, and the improvement compared to the initial circuit is given (Impr/IC). For the proposed approach additionally the improvement compared to the heuristic approach is listed (Impr/HTM). Considering quantum cost, for most of the circuits significant cost reduction can be seen when applying the new approach. Applying the heuristic approach reduces the quantum costs by around 29.14% when considering all circuits. It is clearly observed that these results can be improved when applying the approach based on Boolean satisfiability. The proposed approach leads to an additional cost reductions of 11.42% on average and 27.46% in the best case. The results clearly confirm the impact of the exhaustive search to the circuit costs. The effect is in particular observable for large circuits. Heuristic template matching is already a time consuming process. However, as it is shown, the new approach needs an enormous computation time compared to the heuristic method. This is expected due to the fact that the match is determined exhaustively by the SAT solver, which needs higher run-time to provide the corresponding answer. VI. C ONCLUSION In this paper, a new search method for applying templates in the template matching algorithm has been proposed. Instead of using heuristics for matching gates, the problem is encoded into an instance of Boolean satisfiability and therefore ensures an exhaustive examination of the search space. The proposed approach leads to improvements in terms of circuit costs compared to the heuristic template matching approach. Experimental results clearly confirm these improvements. R EFERENCES [1] M. Nielsen and I. Chuang, Quantum Computation and Quantum Information. Cambridge Univ. Press, 2000. [2] P. W. Shor, “Algorithms for quantum computation: discrete logarithms and factoring,” Foundations of Computer Science, pp. 124–134, 1994. [3] L. M. K. Vandersypen, M. Steffen, G. Breyta, C. S. Yannoni, M. H. Sherwood, and I. L. Chuang, “Experimental realization of Shor’s quantum factoring algorithm using nuclear magnetic resonance,” Nature, vol. 414, p. 883, 2001. [4] R. Landauer, “Irreversibility and heat generation in the computing process,” IBM J. Res. Dev., vol. 5, p. 183, 1961. [5] C. H. Bennett, “Logical reversibility of computation,” IBM J. Res. Dev, vol. 17, no. 6, pp. 525–532, 1973. [6] R. Cuykendall and D. R. Andersen, “Reversible optical computing circuits,” Optics Letters, vol. 12, no. 7, pp. 542–544, 1987. [7] R. C. Merkle, “Reversible electronic logic using switches,” Nanotechnology, vol. 4, pp. 21–40, 1993.
TABLE I E XPERIMENTAL RESULTS Bench 3 17 4gt5 21 mod5mils 18 4gt10 22 aj-e11 81 hwb4 12 ex2 151 4 49 7 1-2-3 27 hwb5 132 mini-alu 84 wrd53 683 hwb5 131 C17 1172 sym6 63 hwb5 13 sym9 714 hwb6 142 C17 1171 C17 117 hwb6 141 cm82a 1263 max46 1772 cm82a 1262 cm82a 1264 cm82a 1261 hwb6 14 m152a 1302 cm152a 130 cm82a 126
Gates 6 3 9 3 22 24 15 32 25 39 35 41 36 38 36 75 51 50 31 69 50 53 45 53 53 53 153 43 88 313
QC 14 19 21 47 118 144 219 220 285 339 483 548 576 654 777 915 949 1002 1003 1657 1826 2011 2556 2565 2643 3336 3465 5574 8754 12811
Heuristic Template Gates QC 6 14 3 19 7 11 4 44 22 102 24 92 21 145 31 187 33 221 40 320 36 392 50 282 43 475 45 509 51 461 83 803 73 478 56 992 35 735 80 1244 54 1414 58 1718 61 1224 61 2349 57 2464 71 2615 169 2925 43 5454 99 7159 356 11224
Matching (HTM, [9]) Time Impr/IC 0.01 0.00 0.01 0.00 0.02 47.62 0 6.38 0.15 13.56 0.14 36.11 0.11 33.79 0.67 15.00 0.23 22.46 0.79 5.60 0.29 18.84 2.22 48.54 1.52 17.53 0.99 22.17 0.8 40.67 10.32 12.24 1.14 49.63 0.66 1.00 0.28 26.72 1.87 24.92 2.41 22.56 1.29 14.57 1.15 52.11 2.06 8.42 1.32 6.77 1.24 21.61 3.7 15.58 2.65 2.15 7.77 18.22 30.91 12.39
[8] K. Fazel, M. A. Thornton, and J. E. Rice, “ESOP-based Toffoli gate cascade generation,” in IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2007, pp. 206–209. [9] D. M. Miller, D. Maslov, and G. W. Dueck, “A transformation based algorithm for reversible logic synthesis,” in Design Automation Conf., 2003, pp. 318–323. [10] R. Wille and R. Drechsler, “BDD-based synthesis of reversible logic for large functions,” in Design Automation Conf., 2009, pp. 270–275. [11] M. Soeken, R. Wille, C. Otterstedt, and R. Drechsler, “A synthesis flow for sequential reversible circuits,” in Int’l Symp. on Multi-Valued Logic, 2012, pp. 299–304. [12] R. Wille and D. Große, “Fast exact Toffoli network synthesis of reversible logic,” in Int’l Conf. on CAD, 2007, pp. 60–64. [13] M. Soeken, R. Wille, G. W. Dueck, and R. Drechsler, “Window optimization of reversible and quantum circuits,” in IEEE Symp. on Design and Diagnostics of Electronic Circuits and Systems, 2010, pp. 341–345. [14] E. F. Fredkin and T. Toffoli, “Conservative logic,” International Journal of Theoretical Physics, vol. 21, no. 3/4, pp. 219–253, 1982. [15] A. Peres, “Reversible logic and quantum computers,” Phys. Rev. A, no. 32, pp. 3266–3276, 1985. [16] T. Toffoli, “Reversible computing,” in Automata, Languages and Programming, W. de Bakker and J. van Leeuwen, Eds. Springer, 1980, p. 632, technical Memo MIT/LCS/TM-151, MIT Lab. for Comput. Sci. [17] A. Barenco, C. H. Bennett, R. Cleve, D. DiVinchenzo, N. Margolus, P. Shor, T. Sleator, J. Smolin, and H. Weinfurter, “Elementary gates for quantum computation,” The American Physical Society, vol. 52, pp. 3457–3467, 1995.
Gates 6 4 6 4 24 24 18 39 34 51 48 39 51 63 30 87 49 64 52 112 81 72 51 83 72 78 172 43 106 443
SMT Based Template Matching QC Time Impr/IC 14 0.7 0.00 16 0.08 15.79 10 0.8 52.38 36 0.17 23.40 96 13.98 18.64 92 9.55 36.11 131 12.95 40.18 151 336.47 31.36 218 140.58 23.51 295 97.88 12.98 348 255.12 27.95 284 577 48.18 419 1371.03 27.26 419 5465.24 35.93 337 240.68 56.63 714 6704 21.97 392 3021.39 58.69 896 459.54 10.58 708 81.97 29.41 1128 3963.94 31.93 1261 2109 30.94 1360 991.97 32.37 1153 583.12 54.89 1704 11403.1 33.57 1897 1536.02 28.23 2162 1170.06 35.19 2620 4769 24.39 5452 2927.56 2.19 7154 4604 18.28 8847 10639 30.94
Impr/HTM 0.00 15.79 9.09 18.18 5.88 0.00 9.66 19.25 1.36 7.81 11.22 -0.71 11.79 17.68 26.90 11.08 17.99 9.68 3.67 9.32 10.82 20.84 5.80 27.46 23.01 17.32 10.43 0.04 0.07 21.18
[18] C. W. Barrett, R. Sebastiani, S. A. Seshia, and C. Tinelli, “Satisfiability modulo theories,” in Handbook of Satisfiability, 2009, pp. 825–885. [19] L. M. de Moura and N. Bjørner, “Z3: An efficient SMT solver,” in Tools and Algorithms for the Construction and Analysis of Systems, 2008, pp. 337–340. [20] R. Bruttomesso, A. Cimatti, A. Franz´en, A. Griggio, and R. Sebastiani, “The MathSAT 4 SMT solver,” in Computer Aided Verification, 2008, pp. 299–303. [21] R. Brummayer and A. Biere, “Boolector: An efficient SMT solver for bit-vectors and arrays,” in Tools and Algorithms for the Construction and Analysis of Systems, 2009, pp. 174–177. [22] R. Wille, G. Fey, D. Große, S. Eggersgl¨uß, and R. Drechsler, “SWORD: A SAT like prover using word level information,” in VLSI of Systemon-Chip, 2007, pp. 88–93. [23] N. Scott, G. Dueck, and D. Maslov, “Improving template matching for minimizing reversible toffoli cascades,” in Int’l Reed-Muller Workshop, 2005. [24] M. Soeken, S. Frehse, R. Wille, and R. Drechsler, “RevKit: An Open Source Toolkit for the Design of Reversible Circuits,” in Reversible Computation 2011, ser. Lecture Notes in Computer Science, vol. 7165, 2012, pp. 64–76, RevKit is available at www.revkit.org. [25] F. Haedicke, S. Frehse, G. Fey, D. Große, and R. Drechsler, “metaSMT: Focus on Your Application not on Solver Integration,” in Int’l Workshop on Design and Implementation of Formal Tools and Systems, 2011. [26] R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, “RevLib: an online resource for reversible functions and reversible circuits,” in Int’l Symp. on Multi-Valued Logic, 2008, pp. 220–225, RevLib is available at http://www.revlib.org.
