EXPERIMENTAL & CLINICAL CARDIOLOGY
Volume 20, Issue 8, 2014
Title: "Ecg Processing on Reconfigurable Hardware for Efficient Artifact Reduction"
Authors: Victor U. Ruiz, Encarnacion Castillo, Diego P. Morales, Antonio Garcia, Luis Parrilla, Daniel Gonzalia, Francisca S Molina and Jesus Florido
How to reference: Ecg Processing on Reconfigurable Hardware for Efficient Artifact Reduction/Victor U. Ruiz, Encarnacion Castillo, Diego P. Morales, Antonio Garcia, Luis Parrilla, Daniel Gonzalia, Francisca S Molina and Jesus Florido/Exp Clin Cardiol Vol 20 Issue8 pages 3023-3028 / 2014
Ecg Processing on Reconfigurable Hardware for Efficient Artifact Reduction
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Experimental & Clinical Cardiology
ECG processing on reconfigurable hardware for efficient artifact reduction Article Type: original article
Victor U. Ruiz1, Encarnación Castillo1, Diego P. Morales1*, Antonio García1, Luis Parrilla1, Daniel Gonzalía2, Francisca S Molina2 and Jesús Florido3 * Corresponding Author:
[email protected] 1 Department of Electronic and Computer Technology. University of Granada (Spain) 2 Maternal-Fetal Medicine Unit, Department of Obstetrics and Gynaecology, San Cecilio University Hospital (HUSC), Granada, Spain 3 Department of Obstetrics and Gynaecology, University of Granada, Granada, Spain
Abstract Denoising of ECG (ElectroCardioGram) signals, usually contaminated from different noise sources, is decisive for correct parameter extraction. Meanwhile, wavelet transform is a useful tool for a variety of signal processing applications and signal compression. This paper presents the hardware implementation of a waveletbased processing algorithm that performs simultaneous wandering and noise suppression in ECG signals. Measures from real recordings are employed in order to validate the overall hardware implementation. On the other hand, required hardware resources fulfill the requirements of portable applications. Keywords Non invasive Fetal ECG, Wavelet Transform, Denoising, FPGA, parametrizable IP Core.
1. Introduction The use of Fetal Electrocardiogram (FECG) for fetal
antepartum diagnosis has been a long-term medical and technological challenge, and a discipline of innovation in both fields. Other sources of information, such as ultrasound measurements preceding labor [1] provide information on fetus wellbeing and allow the measurement of fetus heart rate, but it does not give a real FECG measurement. During labor, the use of an electrode directly attached to baby’s scalp allows the straight FECG measurement and its reliable use for fetal status diagnosis [2]. Making this information available at an early stage will enable the diagnosis of potentially prejudicial fetal heart behaviors, and it requires the acquisition of electrocardiogram (ECG) signals over the maternal abdomen. The extraction of FECG immersed in the maternal abdominal ECG measurements is a non-intrusive technique that is harmless for the fetus. However, this method does require computerized processing that has made this real-time analysis practical for clinical use. The goal of this work is to present a hardware implementation for real-time ECG signal processing that can be implemented on a portable device, eliminating the need of a computerized implementation. From these premises, ECG acquisition from the human
Exp Clin Cardiol, Volume 20, Issue 8, 2014 - Page 3023
Ecg Processing on Reconfigurable Hardware for Efficient Artifact Reduction
skin involves the use of high gain instrumentation amplifiers. This fact makes the ECG signal to be contaminated by different sources of noise. This circumstance is highlighted when the target is the measurement of fetal ECG signals acquired over the mother’s abdomen. ECG signal processing is necessary in order to remove from these signals artifacts that difficult visual inspection and ECG feature extraction, such as the fetal heart rate extraction from ECG signals acquired from the abdomen of pregnant women [3]. These contaminants have an instrumental and physiological origin [4]. Among these noises, the power line interference and the baseline wandering (BW) are the most significant. Except for these two noises, other noises may be wideband and usually caused by complex stochastic processes, which also distort the ECG signal. In any case, BW and other wideband noises are not easily suppressed by analog hardware frontends [5]. Instead, software schemes are more powerful and feasible for off-line processing. Nevertheless, hardware platforms are the goal for portable ECG acquisition and processing systems. Wavelet transform (WT) [6] is a useful tool for a variety of signal processing applications and signal compression [7], being the noise suppression for ECG signals a highlight application [8]. Thus, this paper develops a FPGA-based architecture for removing these noises using a custom wavelet-based algorithm [9] that allows easier suppression of the mentioned wideband noises. This new hardware implementation has been carried out in a FPGA with a new design that includes a microprocessor, which acts as a signal path flow controller, while specifically designed wavelet coprocessors perform the BW and wideband noise suppression.
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an effective method for ECG signals requiring no complex treatment of the noisy signal [10]. It localizes the most important spatial and frequential features of a regular signal in a limited number of wavelet coefficients. Moreover, due to the orthogonality of the transform, the random noise is spread fairly uniformly among all detail coefficients, assuring that wavelet shrinkage can reduce noise effectively while preserving the sharp features (peaks of QRS complex). The proposed hardware architecture is based on the denoising algorithm detailed in [9], which employs only one wavelet decomposition and reconstruction step for both wideband and BW noises. This saves important resources and/or time, facilitating its hardware implementation [12], [13]. The algorithm structure for the application of this denoising approach is: Decomposition: the wavelet decomposition is applied down to a certain level L [9] in order to produce the approximation coefficients
for capturing
the BW, where nL is the sequence length at Lth level. Zeroing approximations: the approximation coefficients of L-level
are replaced by an all-zero vector.
Modified details: the level M (with M
