Experimental Evaluation of Voltage Source Inverter Switching Model with Embedded C Code Controller Bo Wen1, Rolando Burgos1, Paolo Mattavelli1,2, and Dushan Boroyevich1 1 Center for Power Electronics Systems Virginia Tech, Blacksburg, VA 24061 2 University of Padova, Italy
[email protected] Keywords: Voltage Source Inverter, C code, loop-gain Abstract: A switching model of Voltage Source Inverter (VSI) is built in Simulink with C code controller. The procedure of building the model is present. Hardware of VSI is built to evaluate the model in frequency domain and time domain. INTRODUCTION Voltage Source Inverter (VSI), as shown in Figure 1, is widely used in Uninterruptible Power Supply (UPS) [1], motor drive [2], and grid-tied inverter [3]. Switching model simulation plays an important role in the inverter design process. It is being used to verify various design aspects of the hardware, for example, switching ripple, harmonic performance, and transient response. This paper shows a modeling procedure for VSI switching model. Building switching model is not a new and challenge topic for power converter design engineer. Building a switching model which is evaluated by the hardware measurement in both frequency domain and time domain is a topic very few literature has discussed. [4] shows a modeling verification, validation, and uncertainty quantification procedure for a three-phase two-level boost rectifier. Testing procedure is discussed for the switching model of boost rectifier in [4]. The modeling procedure is not well discussed. This paper shows the modeling procedure for VSI. This procedure first model and calibrate the sub component of VSI, including power semiconductor, passive components, sensors, and signal conditioning circuit. Then, a C code controller is constructed using S-function in Simulink, the C code can be used directly in the microprocessor to control the hardware. Finally, the model is validated by comparing the frequency domain and time domain response results from simulation and experiments. Specification of VSI is shown in Table I. The circuit diagram together with the control scheme is shown in Figure 1.
The paper is organized as follow: section 2 models the sub components of VSI; section 3 discusses the C code controller in Simulink for VSI; section 4 presents the validation method and results of VSI in the aspect of smallsignal transfer function. Lac
1.
Table I. VSI specification Input DC Voltage (V) Output Voltage phase (rms V) Output Frequency (Hz) Switching Frequency (kHz)
270 57.5 400 20
vb
ia Vdc Filter
+
SVM
dα θ
dβ αβ dq
θ
dq
+ abc
Rac
vc
ib
DSP
va
Filter
Cac
line-tophase transf + + abc θ dq
vq v iq idref vd dd id dref Controller Controller dq iqref vqref
Figure 1. Voltage source inverter with digital control scheme
2.
SUB COMPONENTS MODELING VSI consists three groups of sub components, including power semiconductor device, passive components, and control system. 2.1. Model of semiconductor device and dead time Although the modeling aim of this paper is not to evaluate the efficiency performance, the basic device parameters such as forward voltage and on resistance should be modeled because of their influence to the converter electrical performance both in time domain [5] and frequency domain [6][7]. If the IGBT module is used in simulation, one can specify the IGBT parameters [8], for example, device on resistance, and forward voltage. This approach models IGBT as an on resistance series with a forward voltage as shown in Figure 2. In this paper, IGBT module from FuJi IPM 6MBP30RH060 is being used. Parameters are extracted from datasheet. On resistance (RF) is 0.05 Ω; forward voltage (VF) for IGBT is 1 V; forward voltage for diode is 0.75 V. Dead time is set to avoid shoot
through of IGBT module. Dead time introduces harmonic to the inductor current of VSI [5]. Dead time influence the small-signal model of VSI [6][7]. Dead time is set by digital controller in the hardware. The same value is used in switching model which is 1us.
Table II. VSI AC inductor measurement results Inductance (µH) 962 985 972
L1 L2 L3
Resistance (mΩ) 123 132 89
Table III. VSI AC capacitor measurement results
RF
VF
Switch
C1 C2 C3
Figure 2. Power semiconductor device model
2.2. Model of passive components In order to model the converter correctly, first thing need to do is to measure the parameters of the hardware. Beside the power semiconductor, for the power stage the measured components are mainly passive components. For VSI, the passive components are AC inductor, AC capacitor. Figure 3 shows the hardware of the AC inductor and AC capacitor. Inductor is modeled as its inductance series with parasitic resistance as being shown in Figure 4. Capacitor is modeled as its capacitance series with parasitic resistance and inductance as being shown in Figure 5. The Agilent 4294A impedance analyzer is being used to measure the parameters of each inductor and capacitor. Table II, Table III list the measured results.
Capacitance (µF) 32.0 31.5 31.8
Resistance (mΩ) 51 54 52
Inductance (µH) 0.61 0.61 0.63
2.3. Model of sensors Four signals are collected from the hardware power stage as signal type and sensor number are list in Table IV. Table IV. Signals used for feedback control Signal name Ia Ib Vab Vca Vdc
Sensor number LA55-P LA55-P LV25-P LV25-P LV25-P
The sensors are calibrated using voltage source and multi-meter. The purpose is to find the relationship between voltage value in the circuit and the output value of corresponding sensor as shown in Figure 6.
A
x
Current
y DC
Sensor
AC capacitor AC inductor Figure 3. VSI AC inductor and capacitor
L
RL
Figure 4. Model of inductor
C
RC
L
Figure 5. Model of capacitor
Figure 6. Current sensor calibration The model is shown in (1). The output of the calibration results the sensors’ gain and offset.
y ax b
(1)
x is the output value from ADC, y is the value used for control. a is the sensor gain and b is sensor offset. Their value for each signal is list in Table V.
implementation in microprocessor faster, because C code for the algorithm is already tested in simulation.
Table V. Gain and offset values for VSI sensors a -0.0008320 -0.0008329 -0.02010 -0.02008 -0.02000
Ia Ib Vab Vca Vdc
b -2.465 -2.393 -57.28 -56.02 -56.80
void main (void){ …… // initialization of DSP PieVectTable.EPWM1_INT = &epwm1_isr; …… // wait for interrupt }
2.4. Model of signal conditioning circuit The signal conditioning filters is being used for noise rejection. They are being built using operational amplifiers. The circuit diagram is shown in Figure 7, the designed filter transfer function is shown in (2). Agilent 4395A network analyzer is used to measure the on board filter transfer function from u to y, the results are shown in Figure 8. There are five filters for the total five signals collected from the power stage circuit. The measured results and the designed filter transfer function are compared for both magnitude and phase. 75pF 15kΩ
15kΩ
+
y
39pF
Figure 7. Circuit diagram of on board signal conditioning filter Y ( s) 1 U (s) 6.5811013 s 2 1.17 106 s 1
Phase (deg)
switching period
Figure 9. Working scheme of DSP C code Start
Run ADC and scale value
Are voltage and current value within limits ?
No
Shut down PWM outputs
Yes
(2)
Voltage and current loop control of VSI
Space Vector Modulation
designed result measured results by network analyzer
Figure 10. Flow chart of interrupt function
102
designed result measured results by network analyzer 103 104 105 Frequency (Hz)
106
Figure 8. On board signal conditioning filter measurement results 3.
} PWM interrupt function, fsw
Magnitude (dB)
0 -5 -10 -15 -20 -25 45 0 -45 -90 -135 -180
interrupt void epwm1_isr(void){
C CODE CONTROLLER FOR VSI MODEL The idea of using C code directly in simulation model is to make sure that the control algorithm, modulation algorithm in the model is the same as they are in the hardware. This approach also makes the algorithm
3.1. Control algorithm for VSI The algorithm running in DSP is in a main function and interruption mode. As Figure 9 shows, DSP runs the main function just to wait pulse width modulation (PWM) unit to give interrupt signal, which happens every switching period. When the interrupt signal is detected, interrupt function will be run. Figure 10 shows the flow chart of interrupt function in which the convert control algorithm is realized. First, run ADC control code to get signals from ADC, scale the signals’ values for control. Second, compare current and voltage values with their limitation for protection purpose, if one signal hits the limits, PWM outputs will be shut down to both converters, if not, go for next step.
Third step is to run VSI voltage and current control. The final step is to run space vector modulation (SVM). The calculated duty cycles are being put to the modulator at the next interrupt instant. This digital control algorithm introduces one switching cycle delay. As Figure 11 shows, at the begin instant of kth switching period, power stage voltage and current signals are collected by sensor and ADC, it will take a period of time for ADC to finish conversion. The digital processor then take some time to run the feedback control and SVM algorithm, the results of the computation will be updated to the modulator’s registers at the beginning of (k+1)th switching period. In this process, the computation results of kth switching instant is update at the (k+1)th switching instant, this yields a switching period delay. [9] The triangular-carrier modulation is used as being shows in Figure 12. The modulator will introduce additional half switching cycle delay according to [9]. Ts
kTs
(k+1)Ts
Sampling AD Computation instant conversion
Duty cycle update
Figure 11. Digital delay caused by digital control algorithm
sc sb sa
da(,b,c)(t)
(k+1)Ts
(k+2)Ts
Figure 12. Triangular-carrier modulation 3.2. Incorporate C code in Simulink model Matlab provides S-function to enable the possibility of using the same C code in the model. An S-function is a computer language description of a Simulink block written in Matlab, C, C++, or FORTRAN. The ideal is to build an S-function block using the DSP interrupt function to model the controller for the converters.
To build an S-function block in Simulink, one can use S-function builder or legacy-code command. In this section, the procedure of how to use Legacy Code Tool build an Sfunction block for C code is described. To use Legacy Code Tool, one needs to create a data structure to define the following information: The name of the S-function The existing C function which is to be incorporated The input and output specification of the C function The sampling time of S-function The legacy_code command initializes the Legacy Code Tool data structure. After the data structure fields are defined. One can use legacy_code to: Generate an S-function for use in simulation. Compile S-function source file Generate a masked S-function block for calling the Sfunction which can be used in Simulink simulation file For more information please check the Matlab document [10]. Here shows the detailed procedure to generate the Sfunction and the block to model the controller with C code imbedded. First, write C code with variable declaration and interrupt function. Save the code as a C file, name it using the name of interrupt function name, for this case is epwm1_isr. Second, specify the inputs and outputs of interrupt function as follows: void epwm1_isr(double *y1, double *y2, double *y3, double u1, double u2, double u3, double u4, double u5) Here, y represents the output of the function; u represents the input of the function. For this case, we have five inputs which are five signals from VSI power stage. The outputs are three duty ratios to control the converter power stages. After the small modification of the C code, which is just format modification, the algorithm is not changed, the legacy_code command can be used to generate S-function and the block which can be used in Simulink model. The process is very simple, the following Matlab script can achieve this goal: def = legacy_code('initialize'); def.SourceFiles = {'epwm1_isr.c'}; def.HeaderFiles = {'math.h'}; def.SFunctionName = 'ex_sfun_ctrl_VSI_AFE'; def.OutputFcnSpec = 'void epwm1_isr(double y1[1], double y2[1], double y3[1], double u1, double u2, double u3, double u4, double u5)'; def.SampleTime = 1/20e3; legacy_code('sfcn_cmex_generate',def); legacy_code('compile',def); legacy_code('slblock_generate',def)
In the above Matlab script, legacy_code command initializes the Legacy Code Tool data structure. (def = legacy_code('initialize');) C code source file is specified. The file uses the same name as the interrupt function epwm1_isr. (def.SourceFiles = {'epwm1_isr.c'};) A header file is specified for math calculation. (def.HeaderFiles = {'math.h'};) The S-function is named to be ex_sfun_ctrl_VSI. (def.SFunctionName = 'ex_sfun_ctrl_VSI';) Specify the output function. (def.OutputFcnSpec = 'void epwm1_isr(double y1[1], double y2[1], double y3[1], double u1, double u2, double u3, double u4, double u5)';) Specify the sampling time of S-function which is the switching frequency 20 kHz. (def.SampleTime = 1/20e3;) Generate the S-function using legacy_code function. (legacy_code('sfcn_cmex_generate',def);) Compile the S-function. (legacy_code('compile',def);) Finally generate the S-function block for use in the Simulink model. By running the script shown before, Matlab will pop a Simulink model window which contains the generated Sfunction block.
Dref. Duty ratios in dq frame are then transferred to αβ frame for SVM. Small-signal perturbation propagates to gate commands for the power module and further to the voltage generated by the power module at the each phase-leg middle point. When the perturbed voltage applied to the output LC filter and resistor load, the current of the inductors are perturbed. These currents are collected back to digital processor and transferred to dq frame. The perturbed d channel duty ratio and d channel current are sent back to network analyzer by digital to analog converter. Network analyzer then measures the transfer function from dd to id. To measure the transfer function from dq to iq, same procedure can be followed. The only change is to apply the perturbation to Dqref and collect perturbed dq and iq back to network analyzer. Lac vb
ia Vdc
Rac
va
ib vc Filter
Cac
DSP +
SVM
dα θ
θ
dβ αβ dq
C code controller block
Ddref id
dd Dqref
+
iq
+
DAC Triangular-carrier modulator
dq
+ abc
DAC
ADC 4395A
Digital control delay
Figure 13. Simulation model of VSI with C code controller 4.
EXPERIMENTAL EVALUATION In order to compare the control performance of model and VSI hardware, transfer function and feedback control loop-gain measurement [11][12] is a powerful approach. Power converter feedback control, usually there are current loop and voltage loop, is designed based on converter duty ratio to current transfer functions. Compare these transfer functions from model simulation and hardware measurement is the first step to calibrate the model. Figure 14 shows the measurement setups of VSI d channel duty ratio (dd) to d channel current (id) transfer function. Network analyzer 4395A is being used for this measurement. First, 4395A generate small signal perturbation, this perturbation is connected to digital controller, which is used to control power stage of VSI, after analog to digital conversion, and the perturbation is added to d channel duty ratio reference
Figure 14. Dd to id transfer function measurement
Bode Diagram
Magnitude (dB)
40
Lac
35
Vdc
30 25 20
Filter
Filter DSP +
SVM
dα
90
dd dq
αβ
θ
θ
dβ dq
0
PI PI
Iqref
id
Idref ++-
+ abc
iq
Rac
Cac
line-tophase transf + + abc θ dq
vd
vq
+
DAC
-90
dq
va
vc
ib
tfiddd_vsi_m tfiddd_vsi_s tfiqdq_vsi_m tfiqdq_vsi_s
15 180 Phase (deg)
vb
ia
DAC
ADC 3
10
4395A
4
10
Frequency (Hz)
Figure 15. Duty ratio to current transfer functions comparison In simulation, the same approach is being used to simulate the transfer function, instead of using network analyzer, Matlab system identification toolbox[13] is used. Figure 15 shows the results of dd to id, dq to iq transfer functions comparison results. From the results we can see that, beside a 1.4dB error on the magnitude, the simulation results and the measurement results are matching each other. Based on the transfer functions been measured, PI controller (kpi = 0.0072; kii = 86.8) is designed. Figure 16 shows the d channel current feedback control loop-gain measurement setup. Current loop-gain is measured by breaking the feedback control loop and injecting perturbation using network analyzer. The breaking point is chosen at the feedback signal id, the signals before and after adding perturbation are sent out to network analyzer to measure the loop-gain. Figure 17 shows the simulation and measurement results of d and q channel current loop-gains. The comparison shows the simulation results match the measurement results very well.
Figure 16. D channel current feedback control loop-gain measurement Bode Diagram
40 Magnitude (dB)
2
10
20 0 -20 -40
Tid_vsi_m Tid_vsi_s Tiq_vsi_m Tiq_vsi_s
-60 180 Phase (deg)
-180 1 10
90 0 -90 -180 1 10
2
10
3
10
4
10
Frequency (Hz)
Figure 17. D and q channel current feedback control loopgains comparison In order to design the voltage feedback control, transfer function from current reference to voltage should be measured. In order to measure the transfer function from idref to vd, Idref is set to run the current loop first. Then perturbation is applied to Idref, this perturbation will propagate through current control loop and SVM to the VSI output voltages va, vb, and vc. Output voltages are collected to digital processor and transferred to dq frame as being shown in Figure 16. Perturbed idref and vd are sent back to network analyzer to measure the transfer function from idref to vd. Same approach can be used to measure transfer function from iqref to vq. Figure 18 shows the results of
measurement and simulation of d and q channel current reference to voltage transfer function. Bode Diagram
Magnitude (dB)
20
control loop and injecting perturbation using network analyzer. Figure 20 shows the simulation and measurement results of d and q channel voltage loop-gains. The comparison shows the simulation results match the measurement results very well.
0
Bode Diagram
50
-20 -40 -60 180
Magnitude (dB)
tfvdidref_vsi_m tfvdidref_vsi_s tfvqiqref_vsi_m tfvqiqref_vsi_s
0
-50
Phase (deg)
90 -100 180 Phase (deg)
0 -90 -180 1 10
2
3
10
4
10
10
Frequency (Hz)
Lac vb
ia
Filter
Filter
DSP +
SVM
dα θ
θ
dβ αβ dq
dd dq
PI PI idref iqref
idref id +i +- qref
dq
iq
Vdref +Vqref + PI PI
Cac
line-tophase transf + + abc θ dq
+ abc
vd
vq
2
3
10
10
4
10
vca_exp 150 vbc_exp 100 v 50 ab_exp 0 -50 vca_sim vab_sim -100 vbc_sim -150 0 0.005
Time (s)
0.01
0.015
Figure 21. VSI output line-to-line voltage comparison between simulation and experiment
+
DAC
-90
Figure 20. D and q channel voltage feedback control loopgains comparison
Rac
vc
ib
0
Frequency (Hz)
Voltage (V)
Vdc
va
90
-180 1 10
Figure 18. D and q channel voltage to current reference transfer functions comparison
Tvd_vsi_m Tvd_vsi_s Tvq_vsi_m Tvq_vsi_s
DAC
ADC 4395A
Figure 19. D channel voltage feedback control loop-gain measurement PI controller (kpv = 0.0033; kiv = 150) is used in voltage feedback control loops based on the measured transfer functions from idref to vd and iqref to vq. Figure 19 shows the d channel voltage feedback control loop-gain measurement setup. The setup is similar as the current loop-gain measure scheme. The difference is to break the voltage feedback
Finally, the values in time domain of VSI output lineto-line voltages are compared between simulation and experiment measurement results as being shown in Figure 21. 5. CONCLUSIONS This paper develops a switching model of VSI which is being built in Simulink with C code controller embedded. The procedure of building the model is present. Hardware of VSI is built to evaluate the model in frequency domain. Transfer functions from duty cycle to current in dq synchronous rotating frame are measured, which shows good matching between simulation and experimental results. Then PI controllers for current control loop are designed based on VSI transfer function. Loop-gains of current and voltage loops are evaluated by experiments also. The results show good matching with experimental results. The model
is also evaluated in time domain, the results shows good matching between the simulation model and the hardware. References [1] N. Abdel-Rahim and J. E. Quaicoe, “Three-phase voltage-source UPS inverter with voltage-controlled current-regulated feedback control scheme,” Industrial Electronics, Control and Instrumentation, 1994. IECON ’94., 20th International Conference on, vol. 1, pp. 497–502 vol.1, 5. [2] F. Blaabjerg, J. K. Pedersen, and P. Thoegersen, “Improved modulation techniques for PWM-VSI drives,” Industrial Electronics, IEEE Transactions on, vol. 44, no. 1, pp. 87–95, Feb. 1997. [3] Guoqiao Shen, Dehong Xu, Luping Cao, and Xuancai Zhu, “An Improved Control Strategy for GridConnected Voltage Source Inverters With an LCL Filter,” Power Electronics, IEEE Transactions on, vol. 23, no. 4, pp. 1899–1906, Jul. 2008. [4] S. Ahmed, R. Burgos, C. Roy, D. Boroyevich, P. Mattavelli, and F. Wang, “Modeling Verification, Validation, and Uncertainty Quantification (VV&UQ) procedure for a two-level three-phase boost rectifier,” Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE, pp. 1894– 1901, 5. [5] A. R. Munoz and T. A. Lipo, “On-line dead-time compensation technique for open-loop PWM-VSI drives,” Power Electronics, IEEE Transactions on, vol. 14, no. 4, pp. 683–689, Jul. 1999. [6] S. Ahmed, Z. Shen, P. Mattavelli, D. Boroyevich, M. Jaksic, K. Karimi, and J. Fu, “Small-signal model of a voltage source inverter (VSI) considering the dead-time effect and space vector modulation types,” Applied Power Electronics Conference and Exposition (APEC), 2011 Twenty-Sixth Annual IEEE, pp. 685–690, 6. [7] Zhiyu Shen, M. Jaksic, S. Ahmed, P. Mattavelli, and D. Boroyevich, “Parametric study of dead time effect on three phase AC output impedance of Voltage Source Inverter (VSI),” Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on, pp. 1–8, Aug. 2011. [8] Bo Wen, D. Boroyevich, and P. Mattavelli, “Investigation of tradeoffs between efficiency, power density and switching frequency in three-phase twolevel PWM boost rectifier,” Power Electronics and Applications (EPE 2011), Proceedings of the 201114th European Conference on, pp. 1–10, Aug. 2011. [9] S. Buso and P. Mattavelli, “Digital Control in Power Electronics,” Synthesis Lectures on Power Electronics, vol. 1, no. 1, pp. 1–158, Jan. 2006. [10] “Integrate C Functions Using Legacy Code Tool MATLAB & Simulink.” [Online]. Available: http://www.mathworks.com/help/simulink/sfg/integrati
ng-existing-c-functions-into-simulink-models-with-thelegacy-code-tool.html. [Accessed: 27-May-2013]. [11] B. H. Cho and F. C. Y. Lee, “Measurement of Loop Gain with the Digital Modulator,” Power Electronics, IEEE Transactions on, vol. PE-1, no. 1, pp. 55–62, Jan. 1986. [12] F. Gonzalez-Espin, E. Figueres, G. Garcera, R. Gonzalez-Medina, and M. Pascual, “Measurement of the Loop Gain Frequency Response of Digitally Controlled Power Converters,” Industrial Electronics, IEEE Transactions on, vol. 57, no. 8, pp. 2785–2796, Aug. 2010. [13] “Estimating Transfer Function Models for a Boost Converter - MATLAB & Simulink Example.” [Online]. Available: http://www.mathworks.com/help/ident/examples/estim ating-transfer-function-models-for-a-boostconverter.html. [Accessed: 28-May-2013].
