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Experimental Results of the New ZVS PWM Voltage Source Inverter with Active Voltage Clamping and Comparison with Classical Structures Adriano PCres
Ivo Barbi
Department of Electrical Engineering FURB - Regional University of Blumenau Phone: +55 (47) 323-7200 - Fax: +55 (47) 323-4939 Cx.P.: 1507 - CEP: 89010-971 - Blumenau - SC - Brazil
[email protected]. br
INEP - Institute of Power Electronics UFSC - Federal University of Santa Catarina Phone: +55 48 33 1-9204 - Fax: +55 48 234-5422 Cx.P.: 5 1 19 - CEP: 88040-970 - Florianopolis - SC - Brazil
[email protected]
Abstract: In this work experimental results of the new pulsewidth-modulation zero-voltage-switching voltage source inverter is presented. At rated load, commutation under ZVS condition is satisfied, and a quasi ZVS commutation is guaranteed under all other load current. The novel topology has the feature of being modulated by any conventional pulse-widthmodulation strategy employed in the hard-switching inverters. The maximum voltage applied in all switches is clamped and limited in a reduced value and it does not produce excessive current stress. Operation description, theoretical analysis and design example are presented in the paper. A comparison among the results obtained from the new inverter topology with classical structures is made, including the results obtained from an Undeland snubber aided inverter.
strategy. In practice this topology needs a resonant current about twice the load current value. Another philosophy was proposed in the auxiliary resonant commutated pole inverter (ARCPI) [5,6, 71. In this topology the resonant pole is connected in parallel with the load. This type of circuit has a complex control strategy and the resonant current assumes large values that are reflected to the main switches increasing their current stress. In this work the new topology of a pulse-widthmodulation zero-voltage-switching active-voltage-clamping voltage source inverter is experimentally tested. The proposed inverter combines the goals of soft switching commutation in all active switches, high frequency capability, conventional PWM strategy and no excessive additional voltage or current stress. In the main switches, ZVS commutation is achieved at rated load, and a quasi ZVS commutation is guaranteed under all other load current conditions. The commutation of the auxiliary switches is ZVS under all load condition. Experimental results prove that the design methodology is effective, and the soft-switching circuit is well suited for a voltage source inverter applications. To provide a comparison reference an Undeland snubber aided inverter was implemented, and some other results obtained from classical structures are used to.
1. Introduction
In the output of a voltage source inverter, excellent voltage and current waveforms are expected, and a minimal harmonic content is considered. To achieve a minimal harmonic content and to reduce the audible noise in voltage source inverters it is desirable operate at high switching frequencies. However, when the switching frequency increases, the efficiency and reliability of the PWM converter deteriorate significantly. Some efforts have been made to reach this aim and various topologies were proposed to achieve soft switching in voltage source inverters [ 1 , 2 , 3 , 4 , 5 , 6 , 71. A great contribution to this area is the Undeland snubber [ 11. It is a passive topology and it is not able to regenerate the commutation energy directly. The resonant pole inverter (WI) [2] provides zero voltage switching (ZVS) in all switches, but it has an excessive resonant current that also circulate in the load. The rugged inverter (ARDPI) [3] combine the advantages of PWM strategy and soft switching techniques, but needs excessive resonant current to get soft commutation. The resonant current required must be at least twice the load current value. The auxiliary resonant pole inverter topology (ARPI) [4] gives a good improvement regarding to this problem (theoretically). However it requires modification in the PWM
0-7803-6407-4/00/$10.00 @2000IEEE
2. Circuit Description a n d Principle of Operation Fig. 1 shows the proposed zero-voltage-switching pulsewidth modulation voltage-source inverter with active voltage clamping (ZVS-PWM-VSI-AVC). The new topology was derived from the family of ZVS-PWM active-voltageclamping DC to DC converters [8]. The inverter consists of two main switches (S2 and S3), two auxiliary switches (SI and S4), six diodes (01-06), six resonant capacitors ( G I CrQ, two resonant inductors (Lrl and Lr2) and two clamping capacitors (Cgland Cg2),besides the DC bus and the load. The topological stages for one period of commutation are shown in Fig. 2, and the main theoretical waveforms are shown in Fig. 3. The novel soft commutation inverter presents nine stages of operation, explained as follows:
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from E to zero, respectively. The voltages across Cr3 and Cr6 increase from zero to E.
E . Zn
iL,.l(t)=i,(t)+-ssrn(w,t)
and w, =-
+ vLR(t)
-
TI . Figure 1 -The Proposed ZVS-PWM Voltage Source Inverter with Active Voltage Clamping.
First Stage (to, tl): in this stage the main switch S2 is conducting. The current through Lrl is equal to the load current and the current through Lr2 is equal to zero. During this stage energy is transferred to the load. Second Stage (tl, tl): at the instant t l , switch S2 is turnedoff and the resonant capacitors Cr2 and Cr.5 are linearly charged. The voltage across Crl varies from zero to E+vgl and the voltage across Cr.5 varies from zero to E. The resonant capacitors Crl and Cr6 are discharged and the voltages across their terminals vary from E+vgl and E to zero, respectively. The resonant current iLrl remains constant and equal to the load current. Third Stage (tz, t3): when the voltage across Cr2 equals E+v,l the voltage across Crl becomes null, and diode DI starts to conduct. Simultaneously the voltage across 0 . 5 becomes equal to E, the voltage across Cr6 becomes null, and diode 0 6 starts to conduct the load current. The inductor Lrl demagnetizes through the clamping capacitor Cgl via DZ. During this stage switch SI must be gated on, so that in the next stage soft commutation is achieved. Fourth Stape (t3, t4): when iLrI becomes zero, diode DI is blocked and switch SI starts to conduct without commutation losses. Current iLrl changes its direction and increases linearly in a negative sense. Fifth Stage (t4, ts): at the instant t4, the switch SI is blocked. Capacitor Crl is charged and capacitor Cr2 is discharged linearly, while the current through Lrl remains constant and equal to the load current. The voltage across Crl increases from zero to E+vgl, while the voltage across Cr2 decreases from E+vgl to zero. Sixth Stage (ts, t6): when VC,.~ becomes equal to zero, diode D2 starts to conduct the current iLrl. In this stage Lrl is demagnetized through E and its energy is recovered. Seventh Stage (t6, t,): at the instant 26 the current through Lrl becomes null and diode D2 is blocked. Switch S2 starts to conduct without commutation losses. The current through Lrl increases sharply, fed by E via S2 and 0 6 . Eighth Stage (t,, t8): when iLrl becomes equal to the load current, the current in diode 0 6 becomes null, blocking it. A resonance involving L r l , Crl, 0 3 , 0 . 5 and Cr6 begins. The current through Lrl increases in a sinusoidal fashion. The voltages across Crl and Cr.5 decrease from E+vgl to vg/ and
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1
Lr = L r l = Lr2 and Cr = Crl = Cr2 = ... = Cr6 Ninth Stage (t8, tg): when the voltage across Cr6 equals E, the voltage across Cr.5 becomes null and diode D.5 starts to conduct. The current through Lrl decreases as a consequence of the resistive elements present in the loop formed by S2, Lrl and D.5. When the current through Lrl becomes equal to the load current, the first stage of operation restarts and one switching period is completed.
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-
CO
U
h) Eighrh stoge.
il Ninth stow.
Figure 2 -Topological Stages for One Switching Period.
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"K
111fI\-
fn=75
0.1:
0.1(
-
0.0:
I I
0. I
02
0.3
0.4
I
Figure 4 -Normalized Maximum Clamping Voltage.
4. Commutation Analysis Soft commutation is achieved when the following expression is satisfied. The regions for main switches soft commutation are graphically represented by Fig. 5. Auxiliary switches commutation are ZVS under all load condition.
.
~
"cf i(l)
.
.
J
I7
15 I4
13
. .
7
1 'Of1 l2
.
.
lg
lg
Figure 3 -The Main Theoretical Waveforms in One Switching Period.
3. The Clamping Action The normalized clamped voltage v g l ( t ) is expressed by (2). The normalized maximum clamped voltage is given by expression ( 3 ) and it is graphically represented by Fig. 4.
Where: ma is the amplitude modulation ratio
y=- zo Zn f n =-f r
fs
The maximum active switches voltage is the sum of the DC bus voltage ( E ) and the maximum clamped voltage. The clamped voltage can be easily controlled by an appropriate combination of resonant parameters (CY and Lr). The resonant parameters also control the soft commutation range.
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0.2
0.3
1
Figure 5 - Soft Commutation Regions.
5. Design Procedure A 2.5kVA ZVS-PWM-VSI with active voltage clamping was designed to drive an induction motor with the following characteristics: Vo,., = l20V ; Vo,,,, = I70V Io,.,,, = 20.8 A ; IoOntm = 29.5 A f o = 601% ; ma = 0.773 Lo = 4.77mH ; Ro = 5.4Q Z O ~ O=H5.76R ~ ; COS ~p = 0.95 The DC bus has a medium point and its total voltage is equal to E = 440V. Choosing fn=75 and the soft commutation range between 20" and 160" and with the aid of Fig. 5, y = 0.I 1 75 is obtained. Hence: Lr Zo -= -= 49.02R 4cr y
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fs = 20 kHz
(switchingfrequency) f r = fs f n = 1.50 Mh?z (resonantfrequency) Lr=-= Zn 5.2p.H 27r f r Lr Cr = _ _ = 0.54 nF 2 zn2
I
cg =
=I 2
(clamping capacitor)
4 a 2 Lrfs2 vgnia.y
=
~ Iv fGnma - 53.63 V Figure 7 - Voltage Across and Current Through the Load.
ma E iLqlla,r -= 38.44 A 2zo
6. Experimental Results A laboratory prototype of a 2.5kVA zero-voltageswitching pulse-width-modulated voltage-source inverter with active voltage clamping (ZVS-PWM-VSI-AVC) has been built, using the scheme shown in Fig. 6 and the values calculated in the previous section. ...
Figure 8 -Clamped Voltages in Cgl and Cg2.
Figure 6 -The Experimented Inverter.
The inverter is operated under conventional sinusoidal pulse-width modulation. The relevant devices specifications are given below. SI and S4 - STGP7NB6OH - ST Microelectronics S2 and S3 - IRG4PC50U - International Rectifier D l - 0 4 - MUR460 - Motorola D5 and 0 6 - HFA15TB60 - International Rectijier Lf - 633 pH (output inductorfilter) Cf - 22 pF (output capacitor3lter).
Figure 9 - Current Through Lrl Superposed with the Load Current.
The following figures show the experimental results at full load condition. Fig. 7 shows the voltage across and the current through the load. The inductive load nature causes the phase shift between the both curves. The clamping voltages across Cgl and Cg2 are shown in Fig. 8. They are limited to 47.1V and 46.7V, respectively. The resonant current through Lrl is shown in Fig. 9 for one load period and in Fig. 10 for one switching period. The maximum value of the resonant current is limited to 37A.
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Figure 10 -Detail of Lrl Current During One Switching Period.
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Fig. 11 shows voltage across and current through the auxiliary switch S I . It can be seen that despite of the IGBT tail current, the commutations are lossless.
l/i. . . . . .
-
. .
~
.
~~~
-
~
Figure 14 - Main Switch S2 Turn-On Proceis-Under Quasi ZVS Condition.
. . ..
Fig. 15 shows a detail of turn-off process in the main switch S2. It can be seen the effect of the IGBT tail current.
. . .
~ _ _ _ _ _ _ ~. .. Figure I I -Voltage Across and Current Through the Auxiliary Switch SI. ~
~
r-
In Fig. 12 it is shown voltage across and current through the main switch S2.
lOOVidiv 10 Ndlv 500nsldiv
Figure 15 - Detail of the Main Switch S2 Tum-Off Process.
Fig. 16 shows the efficiency of the new inverter. At full load condition the measured efficiency was 96.1%.
,i
1
Figure 12 -Voltage Across andC&ent Through the Main Switch S2
96
A detail of the turn-on process in the main switch is shown in Fig. 13. This figure proves that the turn-on process of the main switch S2 is entirely lossless at rated load.
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90 0
250
500
750
1000
1250
1500
1750
2000
Ps[WI
Figure 16 - Efficiency of the New Inverter. .
.
10 Aldiv
7. Comparison with Classical Structures lpldiv
c.
.
-~ -
Figure 13 - Detail of the Main Switch S2 Turn-On Process.
Fig. 14 shows the main switch S2 turn-on process under an other current condition. This commutation is quasi ZVS and it occurs because exists an insufficient resonant current circulating through the Lrl inductance. This phenomenon do not interfere in the efficiency of the inverter.
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In order to compare the results obtained with the new soft commutation inverter, another inverter using the Undeland snubber with the same characteristics depicted in section 5 has been implemented. The inverter with the Undeland snubber applied in this case is shown in Fig. 17 and the principal components used are given bellow. Ls = 2.8pH ; Cs = 4.InF ; Rg = 8 . 3 3 0 ; Cg = 40,uuF
D I- Dz
= HFA15TB60 ; DS= MUR460
S i - Sz = IRG4PCSOU
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__- - _ _ __ Figure 19 - Detail o f the Switch SI Tum-OffFrocess
- _I
Figure 17 - Half-Bridge Inverter Aided by the Undeland Snubber.
rl
.
[%I 95
Fig. 18 shows the turn-on process of switch S1 for the Undeland snubber.
I: /, 75
70
-
,
,
,
,
,
,
500
750
1000
1250
1500
1750
,
55
50 0
250
2000 PS [w]
Figure 20 - Efficiency o f the Inverter Aided by the Undeland Snubber.
In Table I it is shown a summary of a comparison made among classical structures of soft-commutated inverters explored in the recent past years [ l , 2, 3,4, 5 , 6 ,7]. Analyzing Table I it can be seen that the new ZVS PWM VSI AVC is suitable to voltage source inverter applications. The current and voltage stress are limited to 30% of the load current and 11% of the DC bus, respectively. The control strategy used was the classical sinusoidal pulse width modulation. The efficiency measured was 96.1% at full load condition. The Undeland snubber aided inverter is a passive solution and when the switching frequency increases, the commutation losses become higher and the efficiency decreases significantly. A solution for this case is to add a DC-DC converter in the snubber to regenerate the commutation loss.
Figure 18 - Detail o f the Switch SI Turn-On Process.
In Fig. 19 a detail of the switch SI turn-off process is shown. It can be seen, in this figure, the IGBT tail current. Fig. 20 shows the efficiency of the half-bridge inverter with the Undeland snubber. In this picture, it can be seen that the result obtained from the inverter aided by the Undeland snubber is worse than the result obtained from the ZVS PWM VSI AVC case. When the switching frequency becomes higher the commutation losses also becomes higher and a passive solution, such as the Undeland snubber, would be a bad choice.
Table 1 - Summary of a Comparison Made Among Classical Structures of SotLCommutated Inverters.
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The RPI topology needs modification in the PWM strategy and produces a very higher current stress in the main switches. The rugged inverter (ARDPI) uses the conventional PWM strategies, but submit the switches to a higher current stress. The ARPI can solve the current stress but needs modifications in the PWM strategy. The ARCPI topology presents a high current stress and needs a modified modulation.
9. References
[31
8. Conclusion In this paper a new zero-voltage-switching pulse-width modulation voltage-source inverter with active-voltage clamping (ZVS-PWM-VSI-AVC) was presented and analyzed. The experimental results obtained from the new soft-switching voltage-source inverter was compared to the main characteristics of some classical soft-commutated inverters. The comparison results prove that it is suitable for voltage source inverter applications. Some characteristics of the new inverter are better than characteristics of the other topologies. The new inverter topology combines the advantages of a soft-commutated converter using the zerovoltage-switching technique in a wide range of load current and those of a conventional pulse-width modulation. Out of the soft-switching region the commutation is quasi ZVS, and this characteristics do not affect the efficiency. The measured efficiency at full load condition is 96.1%. The current and voltage stress was limited to 30% of the load current and 1 1 % of the DC bus, respectively.
[41
[51 t61 [71
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UNDELAND, T. M.; JENSET, F.; STEINBAKK, S.; ROGNE, T. and HERNES, M. A snubber configtrration for both power transistor and GTO PWM inverters. Conference Records of the IEEE PESC 1984, pp. 42-54. BOYER, S.; FOCH, H.; ROUX, J.; METZ, M. Chopper and PWM inverter wing GTO 's in dual tlivristor operation. Proceedings of the Second European Conference on Power Electronics and Applications 1987, pp. 383-389. CHERITI, A.; HADDAD, A.; DESSAINT, L. A.; MEYNARD, T. A.; MUKHEDKAR, D. A rngged soft comrnirtated PWM inverter for AC drives. Conference Records of the IEEE PESC 1990, pp. 656662. FOCH, H.; CHERON, Y.; METZ, M.; MEYNARD, T. Commirtafion mechanisms arid soft commirtation in static converters. Proceedings ofthe First Brazilian Power Electronics Conference - COBEP 1991, pp. 338-346. BINGEN, G. Utilisation de transistor a.fort cirrrent e tension elevee. Procedings of the First EPE, 1985, pp. 1.15-1.20. McMURRAY, W. Resonant snubbers icifh air.riliaty switches. Conference Records of the IEEE IAS Annual Meeting, 1989, pp. 829-834. DE DONCKER, R. W.; LYONS, J. P. Tl7e airxiliar?. resonant connmrtated pole converter. Conference Records of the IEEE IAS Annual Meeting, 1990, pp. 1228-1235. DUARTE, C. M. C.; BARBI, 1. A neic'famili~of ZVS-PWM acfiveclamping DC-to-DC boost converter.7: ana!isis. design, and e.rperimentation. IEEE Transactions on Power Electronics, vol. 12, N o 5, July 1997, pp. 824-83 I . PERES, A; BARBI.1. A new ZVS PWM voltage source inverter with active voltage clamping. Conference Records of the IEEE INTELEC 1999, pp. 26-2.1/26-2.6. PERES, A; BARBI.1. A new soft commutation PWM voltage source inverter. Proceedings of the Fifth Brazilian Power Electronics Conference - COBEP 1999, pp. 602 - 607.
