Explicit Continuous Model for Long-Channel Undoped ... - IEEE Xplore

1868

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005

Explicit Continuous Model for Long-Channel Undoped Surrounding Gate MOSFETs Benjamin Iñíguez, Senior Member, IEEE, David Jiménez, Jaume Roig, Hamdy A. Hamid, Lluís F. Marsal, Senior Member, IEEE, and Josep Pallarès, Member, IEEE

Abstract—We present an analytical and continuous dc model for cylindrical undoped surrounding-gate (SGT) MOSFETs in which the channel current is written as an explicit function of the applied voltages. The model is based on a new unified charge control model developed for this device. The explicit model shows good agreement with the numerical exact solution obtained from the new charge control model, which was previously validated by comparison with three-dimensional numerical simulations. Index Terms—Charge control model, compact device modeling, surrounding-gate (SGT) MOSFETs.

I. INTRODUCTION

T

HE surrounding-gate (SGT) MOSFET is one of the most promising candidates for the downscaling of CMOS technology toward the nanometer channel length range, since the surrounding gate allows an excellent control of the channel charge in the silicon film, reducing short-channel effects [1]–[3]. However, the extension of the applications of the SGT MOSFETs is critically dependent on the availability of compact models of these devices for circuit design and simulation. Standard compact models for bulk or even SOI MOSFETs do not seem to be valid for SGT MOSFETs, since they are based on the charge sheet approximation, which assumes that only a very thin layer at near the silicon/oxide interface contributes to the channel current between source and drain. This approximation is not valid in thin-film surrounding gate MOSFETs, where there is an inversion or an accumulation of carriers in the whole silicon film, and the whole volume contributes to the channel current. In a previous work, [3], we presented a physically based current-voltage model for undoped (or lightly doped) SGT MOSFETs, valid and continuous through all operating regimes. Short-channel effects were ignored, because the excellent gate control extends the validity of the gradual channel approximation to submicron devices; anyway, the model was proven to show good agreement with three-dimensional (3-D) numerical Manuscript received December 2, 2004; revised April 11, 2005. This work was supported in part by the Ministerio de Ciencia y Tecnología under Project TIC2003-08213-C02-01, and in part by the European Commission under Contract 506844 (“SINANO”) and Contract 506653 (“EUROSOI”). The review of this paper was arranged by Editor T. Skotnicki. B. Iñíguez, H. A. Hamid, L. F. Marsal, and J. Pallarès are with the Departament d’Enginyeria Electronica, Eléctrica i Automatica, Universitat Rovira i Virgili, 43007 Tarragona, Spain. D. Jiménez is with the Departament d’Enginyeria Electrònica, Escola Tècnica Superior d’Enginyeria, Universitat Autònoma de Barcelona, 08193-Bellaterra, Barcelona, Spain. J. Roig is with the Centro Nacional de Microelectrónica, CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain. Digital Object Identifier 10.1109/TED.2005.852892

simulations. However, in this model, the current cannot be written as an explicit expression of the applied voltages, and the equations have to be solved numerically. This may limit the use of this model in circuit simulation, because it leads to an increase of the simulation time, compared to explicit models. In this paper, we present an explicit continuous dc model for the SGT MOSFET. The new model is based on a unified charge control model for a SGT MOSFET, which results from a reformulation of the previous model [3]. The channel current is written in terms of the charge densities at the source and drain ends. Examining, with the new charge control model, the dependences of the channel charge density on the applied voltages in each operating regime, we propose approximate explicit expressions of the channel charge densities in terms of the applied bias, and valid and infinitely continuous through all operating regimes. Therefore, the channel current becomes an explicit function of the bias. Another very important advantage of the new model is the absence of empirical fitting parameters. Therefore, all parameters have a physical meaning. We have demonstrated that our approximate explicit solution fits very well the numerical exact solution of the charge control model in all operating regimes. The resulting explicit model of the channel current shows also a very good agreement with the exact calculation (from the numerical solution of the charge control model) of the channel current. Due to its infinite order of continuity, the new model provides smooth transitions through all operating regimes, which is very desirable in circuit simulation. II. MODEL AND RESULTS Assuming the gradual channel approximation (GCA), in an undoped (lightly doped) cylindrical n-type SGT-MOSFET (Fig. 1) Poisson’s equation takes the following form: (1) where , being q the electronic charge, the inthe permittivity of silicon, trinsic carrier concentration, the electrostatic potential, and the electron quasi-Fermi potential. It has been assumed that the hole density is negligible compared with the electron density. Equation (1) must satisfy the following boundary conditions: (2) where is the surface potential. The first one is a symmetry condition.

0018-9383/$20.00 © 2005 IEEE

IÑÍGUEZ et al.: EXPLICIT CONTINUOUS MODEL FOR SG MOSFETs

Fig. 1.

1869

Cross section of a surrounding gate MOSFET.

The current mainly flows along the direction; therefore, we can assume that is constant along the direction; i.e., . Equation (1) can be analytically solved yielding [1]–[3] (3) is related to through the second boundary condition in (2). The total mobile charge (per unit gate area) can be written as , where and is the work-function difference between the gate electrode and intrinsic silicon. From Gauss’s law, the following relation must hold: (4) Substituting (3) into (4) leads to

(5) is a constant (of ) to be determined from where is a structural parameter. For a given (5), and , can be solved from (5) as a function of . Note that varies from the source to the drain, being at the source at the drain end. end, and By writing as a function of , we can obtain a charge control model relating the carrier charge density with the bias. We obtain from (3) that ; therefore, in terms of , . Using we can write , we finally can this expression in (4), write , where . . Replacing it in (5) we obtain Therefore, the following charge control model:

(6) This charge control model, without the third term in the righthand side (RHS), is very similar to the Unified Charge Con-

Fig. 2. Channel charge density (per unit area) at the source (V = 0) in (a) linear and (b) logarithmic scale. R = 6:25 nm. Dashed line with circles: model using (17). Solid line: numerical solution of (6).

trol Model (UCCM) derived previously for bulk and single-gate fully-depleted SOI MOSFET [4]–[6]. The third term appears because of the existence of volume accumulation or inversion, although this effect, in the RHS of (6), is also included in the other two terms. Quantum mechanical effects have not been considered in this model; anyway, they are negligible for silicon films nm). For films thinner than thicker than 10 nm (i.e., 10 nm, quantum confinement should be considered; it leads to a reduction of the channel charge density and an increase of the threshold voltage [7]. The drain current is calculated from (7) We will obtain an expression of charge densities. From (6) we obtain

in terms of the carrier

(8)

1870


Fig. 3. Transfer characteristic at V = 0:1 V in (a) linear and (b) logarithmic scale. R = 6:25 nm. Dashed line with circles: model using (17). Solid line: model using the numerical solution of (6).

Fig. 4. Transfer characteristic at V = 1:0 V in (a) linear and (b) logarithmic scale. R = 6:25 nm. Dashed line with circles: model using (17). Solid line: model using the numerical solution of (6).

Writing between

Anyway, it is possible to find approximate explicit expressions of in the asymptotic limits of subthreshold and above threshold. We can see that in (6), well above threshold, the two logarithmic terms in RHS are smaller than the first term in RHS, and (6) can be approximated as

as a function of and and , we obtain:

in (7), and integrating

(9) (10) Without the third term in RHS, this expression is very similar to the conventional one for bulk or SOI MOSFET. As in other device models derived from UCCM, the second term in the RHS of (9) dominates in strong inversion (when channel charges are large), and the first term dominates in weak inversion (when channel charges are small). We observed that the third term in RHS is only important near threshold, but cannot neglected in this regime. To calculate the channel current, we have to solve (6) for at the source and at the drain. However, (6) has no exact analytical solution and in principle has to be solved numerically.

And therefore (11) where On the other hand, we can see that in (6), well below threshold, since (12) where

.


1871

An approximate explicit expression of in terms of the bias will, in turn, lead to an explicit model of the channel current. In fact, in previous works explicit solutions of UCCM in bulk and single-gate SOI MOSFETs were proposed and tested [4]–[6]. An approximate explicit solution of the standard UCCM equation is [6], is (13) shown at the bottom of the page. This expression tends to (10) and (12) above and below threshold, respectively. However, we observed that this explicit expression of (13) does not work very well above threshold The modeled using (13) is significantly lower than the calculated from the numerical solution of (6). The reason of this difference is that the two logarithmic terms in the RHS of (6) increase, although above threshold, and they are not negligible. slowly, with Nevertheless, this effect can be modeled as a correction of . This logarithmic increase of the threshold voltage with above threshold is also significant in DG SOI MOSFETs [8]. By considering this effect, from (6), we can write the above threshold charge density as

(14) , is actually a first iteration for

where . Equation (14) is a much more accurate expression for above threshold than (10). In order to keep a unified expression for , we need a unified expression of the threshold voltage. From below threshold, but from (12), the threshold voltage is (14), above threshold, it is (15) We cannot use (15) as a unified threshold voltage expression, because the second term in the RHS of (15) would tend to as we decrease below threshold (since then tends to 0). However, for the same reason, the third term of the RHS below threshold, as it should. tends to 0 as we decrease Note, on the other hand, that well above threshold, , . and A suitable unified expression of the threshold voltage is: (16)

Fig. 5. Output characteristics. R = 6:25 nm. Dashed line with circles: model using (17). Solid line: model using the numerical solution of (6).

Below threshold, and , as it should. Well and , above threshold, as it should. Our final explicit expression of is written as (17), shown at the bottom of the page. In (17) is calculated from (16), where is calculated from the unified expression of (13), that ignores the logarithmic corrections of the threshold voltage shown in (18) at the top of the next page. . This In (17) term assures the correct behavior of Q above threshold, above threshold, and therefore since , as it should. Below threshold has . no influence since We can see in Fig. 2(a) and (b) that the expression given by (17) agrees very well with the numerical solution of (5), both below and above threshold. No fitting parameters are used. We m, a silicon film assumed a device with channel length nm, a silicon oxide thickness nm, radius and a midgap gate electrode (gate working function of 4.61 eV).

(13)

(17)

1872


(18)

Therefore, and are calculated from (17) using and , respectively. The expression of the channel current given in (9) becomes explicit. We observe in Figs. 3–5 that the new explicit model provides very good agreement with the channel current values obtained using the numerical solution of (6). The device simulated is the same as for Fig. 2. The fitting is quite good from below to above threshold, and the transitions between the operating regimes are smooth, because of the infinite order of continuity of the model. III. CONCLUSION In this paper, we have presented an analytical dc model for cylindrical undoped SGT MOSFETs. The model is based on a new unified charge control model developed for this device, from which we derived a channel current expression in terms of the channel charge densities at the source and drain ends of the channel. The model becomes explicit by using appropriate expressions for the channel charge densities in terms of the applied voltages. The channel charge distribution in the silicon film is adequately accounted for in the charge control model. Good agreement is found between the new explicit model and the numerical exact solution obtained from the charge control model which, in turn, was previously validated by comparison with 3-D numerical simulations. Besides, the channel current expression presents an infinite order of continuity over all operating regimes, which makes the model very promising for circuit simulation. REFERENCES [1] D. Jiménez, J. J. Sáenz, B. Iñíguez, J. Suñé, L. F. Marsal, and J. Pallarès, “Modeling of nanoscale gate-all-around MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 5, pp. 314–316, May 2004. [2] Y. Chen and J. Luo, “A comparative study of double-gate and surrounding-gate MOSFETs in strong inversion and accumulation using an analytical model,” in Proc. Int. Conf. Modeling Simulation Microsystems, 2001, pp. 546–549. [3] D. Jiménez, B. Iñiguez, J. Suñé, L. F. Marsal, J. Pallarès, J. Roig, and D. Flores, “Continuous analytic current-voltage model for surrounding-gate MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 571–573, Aug. 2004. [4] C.-K. Park, C.-Y. Lee, K. Lee, B.-J. Moon, Y. H. Byun, and M. Shur, “A unified current-voltage model for long-channel nMOSFETs,” IEEE Trans. Electron Devices, vol. 38, pp. 399–406, Feb. 1991. [5] M. S. Shur, T. A. Fjeldly, T. Ytterdal, and K. Lee, “Unified MOSFET model,” Solid State Electron., vol. 35, no. 12, pp. 1795–1802, Dec. 1992. [6] B. Iñíguez, L. F. Ferreira, B. Gentinne, and D. Flandre, “A physicallybased C -continuous fully-depleted SOI MOSFET model for analog applications,” IEEE Trans. Electron Devices, vol. 43, no. 4, pp. 568–575, Apr. 1996. [7] L. Ge and J. G. Fossum, “Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 287–294, Feb. 2002. [8] Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic draincurrent model for DG-MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 2, pp. 107–109, Feb. 2004.

Benjamin Iñíguez (M’96–SM’03) received the B.S., M.S., and the Ph.D. degrees in physics from the University of the Balearic Islands, Spain, in 1989, 1992, and 1996, respectively. His doctoral research focused on the development of CAD models for short-channel bulk-Si and SOI MOSFETs. From February 1997 to September 1998 he was working as a Postdoctoral Research Scientist at the ECSE Department, Rensselaer Polytechnic Institute (RPI), Troy, NY, where he studied advanced devices such as short-channel a-Si and poly-Si TFTs, GaN HFETs, and heterodimensional MESFETs. From September 1998 to February 2001 he was a Research Scientist (Postdoctoral Marie-Curie Grant Holder) in the Microelectronics Laboratory, Université catholique de Louvain, Belgium, working on the characterization and modeling of thin-film and ultrathin-film SOI MOSFETs from dc to RF conditions. In February 2001 he joined the Department of Electronic Engineering, Universitat Rovira i Virgili, Tarragona, Spain, as Titular Professor. His current research interests are characterization and modeling of advanced electron devices, in particular nanoscale SOI MOSFETs and organic and polymer TFTs, as well as the study of photonic crystals. Dr. Iñíguez was awarded the Distinction of the Catalan Government for the Promotion of University Research in 2004.

David Jiménez received the Ph.D. degree in electronics engineering from Universitat Autonoma de Barcelona in 2000. He has been an Associate Professor at the Departament d’Enginyeria Electronica from Universitat Autonoma de Barcelona since 2004. His research activity is focused on compact modeling of nanoscale transistors such as multiple-gate MOSFETs and silicon nanowire transistors.

Jaume Roig, photograph and biography not available at the time of publication.

Hamdy A. Hamid was born in 1970. He received the B.S. degree in electrical engineering from the Higher Technological Institute, Ramadan City, Egypt in 1994, and the M.S. degree in electronic engineering from Ain Shams University, Cairo, Egypt, in 2000. He is currently pursuing the Ph.D. degree at the Electronics Department (DEEEA), Universitat Rovira i Virgili (URV), Tarragona, Spain. From April to June 2005 he was a Graduate Visting Student at the Electrical Engineering Department, University of Liverpool, UK. His research focuses the physics and modeling of nanoscale MOSFETs.


Lluís F. Marsal (SM’04) received the B.S. and M.S. degrees from the University of Barcelona, Barcelona, Spain, in 1991, and the Ph.D. degrees from the University Politècnica de Catalunya, Barcelona, in 1997, all in physics. His doctoral research was a contribution to the non-crystalline silicon-carbon alloys on crystalline silicon heterojunctions. In 1991, he joined the Department of Electronic Engineering, University Rovira i Virgili, Tarragona, Spain, where he became Assistant Professor in 1994 and Associate Professor in 2000. From April 1998 to May 1999 he was a Postdoctoral Researcher at the Department of Electrical and Computer Engineering, University of Waterloo, ON, Canada, where he worked on SiGe /Si solar cell characterization and simulation. His research interests have been mainly devoted to the study of advanced electron devices. Recently, he focuses his work on the study of photonic crystals based on silicon, as well as nanoscale Si devices and organic and polymer TFTs.

1873

Josep Pallarès (M’00) received the physics degree from the University of Barcelona, Barcelona, Spain, in 1991, and the Ph.D. degree in physics from the Polytechnic University of Catalonia (UPC), Barcelona, in 1997. His doctoral research addressed the analysis of the SRH current in pn heterojunctions (in particular noncrystalline/crystalline heterojunctions). In 1991, he joined the Department of Electronic Engineering, University Rovira i Virgili (URV), Tarragona, Spain, as Assistant Professor. During 1999 he was a Postdoctoral Researcher at the Debye Institute, University of Utrecht, The Netherlands, working on TFT technology and characterization. He became Associate Professor at URV in 2000. His current research interests are the study of photonic crystals based on silicon, porous silicon, nanoscale Si devices and organic and polymer TFTs.