Fabrication and characterisation of 200 mm germanium-on-insulator ...

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Mar 30, 2006 - Introduction: Germanium is expected to improve performance in various fields, such as nano-electronics [1] sub-32 nm mode (for its high carrier ...
Fabrication and characterisation of 200 mm germanium-on-insulator (GeOI) substrates made from bulk germanium C. Deguet, L. Sanchez, T. Akatsu, F. Allibert, J. Dechamp, F. Madeira, F. Mazen, A. Tauzin, V. Loup, C. Richtarch, D. Mercier, T. Signamarcheix, F. Letertre, B. Depuydt and N. Kernevez The formation and detailed characterisations of a 200 mm germaniumon-insulator substrate made from germanium bulk material as donor wafer using the Smart CutTM technology is reported. Detailed characterisations of final GeOI structures are presented: final roughness, defectivity evaluation, thickness measurement, and electrical characterisation.

Introduction: Germanium is expected to improve performance in various fields, such as nano-electronics [1] sub-32 nm mode (for its high carrier mobility and compatibility with high k material), solar cells [2] (good lattice match with III-V family for GaAs epitaxy growth), and near-infrared detectors [3]. Recent developments on thin GeOI substrates (germanium-on-insulator) have given rise to a new generation of innovative germanium templates. Feasibility of GeOI substrates using the Smart CutTM technology [4] has been already demonstrated in previous publications using two different donor wafers: bulk germanium wafers from Umicore [5] were used to make 100 mm GeOI wafers [6] and pure epitaxial germanium on silicon wafers to realise 200 mm GeOI [6, 7]. Even if epitaxial germanium on silicon wafers are good candidates for GeOI substrate development, they have a threading dislocation density of the order of a few 106 cm2, which could be a drawback for future applications. Bulk germanium wafers have a better crystalline quality than epi-wafers but suffer from COP-like defects comparable to conventional CZ silicon bulk wafers. This Letter therefore focuses on 200 mm GeOI substrates made from Ge bulk wafers and the associated results. GeOI realisation: We used 200 mm bulk germanium wafers provided by Umicore, with different doping levels (n-type or p-type). First, we developed a low-consumption HF-based Ge cleaning process, which leaves the surface with metallic contamination levels below 5  1010 at=cm2 as measured using the VPD ICPMS technique. This process has good particle removal efficiency, without any degradation of the initial surface roughness. After cleaning, a plasma enhanced chemical vapour deposition (PECVD) oxide was deposited on the germanium donor wafer to form a part of the final buried oxide. This oxide was deposited and densified at temperatures around 600 C, which are fully compatible with germanium. The thickness of this oxide is a few 100 nm. Capped germanium wafers were ion implanted with Hþ, with doses and energies in the mid-1016 at=cm2 range for the dose and 50–100 keV for the energy. Surfaces were then cleaned and prepared for room-temperature hydrophilic bonding to thermally oxidised Si base substrates. Because of the difference between the thermal expansion coefficients of Si and Ge, the main difficulty consists in managing the splitting. Once the transfer step was optimised in terms of implantation and splitting conditions, GeOI structures were formed on full wafers. Final treatments (such as annealing and polishing) generate GeOI surfaces fully compatible with device processing.

Fig. 1 Top view photograph of final GeOI wafer, 200 mm diameter (donor wafer is a 200 mm bulk Ge wafer)

Characterisation of GeOI substrates: A completed 200 mm GeOI wafer made from bulk material is shown in Fig. 1. Finished GeOI

substrates have been characterised from a morphological point of view where they are compared with starting material. The thickness of the transferred germanium film depends on the energy of the ions during implantation. Typically with the used energies the transferred thickness is equal to a few thousand angstroms. The final thickness of Ge is adjusted using SOI-like chemo-mechanical polishing (CMP) process, using a slurry based on colloidal silica. The final thickness can be reduced down to 40 nm according to the final application. Typically the average thickness on the final substrate is about 200 nm with a standard deviation equal to 5%, indicating a good final uniformity. Cross-sectional transmission electron microscopy (TEM) images are shown in Fig. 2 to illustrate the crystallographic quality of the final GeOI substrate. On the TEM cross-section, the thickness of the germanium is about 200 nm, and the buried oxide thickness equals 350 nm. The bonding interface between thermal silicon oxide and deposited oxide can be seen in the TEM picture. The high-resolution TEM image shows that the crystalline quality of the germanium layer has been preserved, which is a characteristic of the Smart CutTM technology. No threading dislocations are seen on this TEM cross-section.

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Fig. 2 Cross-sectional TEM image and high-resolution TEM image of GeOI substrate (final Ge thickness 200 nm for this sample)

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Fig. 3 Two different kinds of defects that appear on final GeOI

Very smooth final germanium surfaces are obtained. RMS roughness measured by an atomic force microscope is below 0.2 nm and Z range value around 2 nm is associated with a 5  5 mm scan. This value is comparable (even better) than starting material roughness on the bulk Ge wafer (RMS value below 5 A). Final GeOI substrates have been measured using a surface inspection tool from KLA-Tencor (Surfscan 6200). This tool uses an incident laser scanning the wafer surface, measuring the scattering light with a 0.25 mm defect size threshold. A comparison between the final defects on the GeOI substrates and the defects coming from the starting material has been carried out, showing a good correlation. On the final GeOI wafer we have an average of less than 10 defects=cm2, which is comparable to the initial defectivity on bulk Ge (about 3 defects=cm2). The final defects are a combination of defects existing on the bulk Ge and defects due to the process. A defect review has been carried out using both optical and electron beam microscopes. We have shown that we have essentially two different kinds of defects: first, some regular round shape defects (see Fig. 3a) that are enlarged during final soft touch polishing; secondly, some ‘flat’defects (Fig. 3b) coming from a delamination of the top Ge surface that could appear during a specific process step. The majority of the defects due to the process are probably induced by a weak interface between the germanium and the oxide.

ELECTRONICS LETTERS 30th March 2006 Vol. 42 No. 7

The GeOI samples have also been characterised from an electrical point of view. The pseudo-MOSFET technique [8] has been used to measure electrical conductivity at the interface between the germanium and the BOX. Fig. 4 shows a C-MOSFET characterisation of an ˚ p-type ‘bulk’ GeOI wafer. Typical results unprocessed 2000=4000 A obtained are around 5  1012 eV1 cm2 for density of interface states (Dit) at the Ge=SiO2 interface, around 300 cm2 V1 s1 for electron mobility, me, and over 350 cm2 V1 s1 for hole mobility, mh. The lower me value, already well known for MOSFETs on germanium, could be due to the stronger impact of Dit on electrons than on holes.

C. Deguet, L. Sanchez, J. Dechamp, F. Madeira, F. Mazen, A. Tauzin, V. Loup and N. Kernevez (CEA-DRT-LETI, CEA=GRE, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France) E-mail: [email protected] T. Akatsu, F. Allibert, C. Richtarch, D. Mercier, T. Signamarcheix and F. Letertre (SOITEC SA, Advanced Technology Division, Parc Technologique des Fontaines, 38190 Bernin, France) B. Depuydt (UMICORE, Watertorenstraat, 33 B-2250 Olen, Belgium) References

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Fig. 4 ID(VG) and gm(VG) curves obtained by C-MOSFET on GeOI wafer at low VD (200 mV)

Conclusions: We have demonstrated a recent 200 mm GeOI formation from Ge bulk wafers using the Smart CutTM technology, and associated characterisation results. Encouraging results are obtained in terms of final roughness, defectivity, film thickness and electrical characteristics, which are compatible with state-of-the-art MOS processing. However, the understanding of the germanium interface phenomena becomes crucial not only to develop the GeOI material but also to correlate the properties of this material with the anticipated multiple functions and to fulfil the application-driven requirements (on mechanical strength, electrical, photoelectric and photovoltaic properties).

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Chui, C., Kim, H., Chi, D., Triplett, B., McIntyre, P., and Saraswat, K.: ‘A sub-400 C germanium MOSFET technology with high-k dielectric and metal gate’. IEEE Proc. Int. Electron Device Meet. (IEDM), 2002, p. 437 King, R., Law, D., Fetzer, C., Sherif, R., Edmondson, K., Kurtz, S., Kinsey, G., Cotal, H., Hurt, D., Ermer, J., and Karam, N.: ‘Pathways to 40% efficient concentrator photovoltaics’. 20th European Photovoltaic Solar Energy Conf., Barcelona, Spain, 2005, p. 118 Masini, G., Cencelli, V., Colace, L., De Notaristefani, F., and Assanto, G.: ‘Monolithic integration of near-infrared Ge photodetector with Si complementary metal-oxide-semiconductor reactant electronics’, Appl. Phys. Lett., 2002, 80, (18), p. 3268 Bruel, M.: ‘Silicon on insulator material technology’, Electron. Lett., 1995, 31, p. 1201 Umicore, Watertorenstraat 33, B-2250 Olen, Belgium Letertre, F., Deguet, C., Faure, B., Richtarch, C., Hartmann, J.M., Chieu, F., Beaumont, A., Allibert, F., Morales, C., Dechamp, J., Perreau, P., Pocas, S., Personnic, S., Lagahe-Blanchard, C., Ghyselen, B., Le Vaillant, Y.M., Jalaguier, E., Kernevez, N., and Mazure, C.: ‘Germanium-on-insulator (GEOI) structure realised by the Smart CutTM technology’, Mater. Res. Soc. Proc., 2004, 809, (B4.4), p. 153 Deguet, C.: ‘200 mm germanium-on-insulator (GEOI) structures realised from epitaxial wafers using the smart cut technology’, Electrochem. Soc. Proc., 2005, 2005-06, p. 78 Cristoloveanu, S., Munteanu, D., and Liu, M.S.T.: ‘A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction and applications’, IEEE Trans. Electron Devices, 2000, 47, (5), p. 1018

Acknowledgments: The authors acknowledge all who have contributed to this work at CEA-LETI Grenoble and SOITEC. # IEE 2006 Electronics Letters online no: 20060208 doi: 10.1049/el:20060208

19 January 2006

ELECTRONICS LETTERS 30th March 2006

Vol. 42 No. 7