Fabrication, Modeling, and Characterization of High ... - IEEE Xplore

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 12, DECEMBER 2010

Fabrication, Modeling, and Characterization of High-Aspect-Ratio Coplanar Waveguide Shane T. Todd, Member, IEEE, Xiaojun T. Huang, John E. Bowers, Fellow, IEEE, and Noel C. MacDonald, Fellow, IEEE

Abstract—A silicon micromachining process has been developed to fabricate high-aspect-ratio coplanar waveguide (hicoplanar). A new closed-form analytical transmission line model that is valid for both conventional coplanar waveguide (CPW) and hicoplanar is introduced and compared with simulations and experimental results. The major novelties of the model are that it includes the effect of the conductor height on the output parameters and combines Wheeler’s inductance rule and perturbation theory to predict the line resistance. Transmission lines with characteristic impedances of 18–25 have been fabricated on high-resistivity silicon. Attenuation was measured to be 2.4–3.4 dB/cm at 30 GHz before silicon removal and 1.7–2.4 dB/cm at 30 GHz after silicon removal. The analytical model is compared with Ansoft High Frequency Structure Simulator simulations and experimental data and shows excellent agreement.

Index Terms—Coplanar waveguides (CPWs), high aspect ratio, microelectromechanical systems (MEMS), micromachining, transmission lines, RF CMOS.

I. INTRODUCTION ONOLITHIC microwave integrated circuits (MMICs) fabricated on silicon have been made possible by advances in CMOS technology. The scaling down of CMOS dimensions have increased the cutoff frequency of CMOS transistors; this has allowed for the creation of several types of millimeter-wave CMOS MMICs, including amplifiers [1], [2], oscillators [3], mixers [4], and transceivers [5]. While compound semiconductor MMICs have better performance than CMOS MMICs, CMOS offers advantages, including lower fabrication costs and higher integration with electronic circuits. A fundamental problem with CMOS MMICs is that the conductivity of the silicon substrate can cause substantial dielectric loss in transmission lines. Milanovic et al. showed that the loss can be as high as 25–50 dB/cm at 30 GHz for coplanar waveguides (CPWs) on CMOS-grade silicon [6]. Much work has been dedicated to mitigating the substrate loss.

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Manuscript received January 11, 2010; revised July 16, 2010; accepted September 02, 2010. Date of publication November 18, 2010; date of current version December 10, 2010. This work was supported by the Kavli Foundation. S. T. Todd was with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA. He is now with the Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), 117685 Singapore (e-mail: [email protected]). J. E. Bowers is with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA (e-mail: bowers@ece. ucsb.edu). X. T. Huang and N. C. MacDonald are with the Department of Mechanical Engineering, University of California, Santa Barbara, CA 93106 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2010.2086531

The most common approach to reducing substrate loss is to fabricate transmission lines over a ground plane that shields the lines from the substrate. Microstrip and CPW transmission lines have been fabricated on silicon using this approach [1], [2], [7]. The transmission lines are typically made from the metal layers of the CMOS process with metal 1 serving as the ground plane shield. Losses are usually greater than 3 dB/cm at 30 GHz for 50- lines in these types of devices. Micromachining methods have also been employed to reduce the substrate loss of silicon. A popular micromachining approach is to reduce field exposure to the substrate through silicon removal or transmission-line elevation [8]–[12]. Micromachining can also be used to increase the transmission-line dimensions, which contributes to lower loss in lines on silicon substrates. The increased dimensions reduce conductor loss through current spreading and reduce substrate loss by improved field confinement. Micromachined coaxial transmission lines are an excellent demonstration of reduced conductor loss [13]–[15]. The rectangular coaxial transmission lines achieved low loss, demonstrated excellent isolation between lines, and eliminated field interaction with the substrate. High-aspect-ratio CPWs are another example of transmission lines created from micromachining methods. We will refer to high-aspect-ratio CPW as hicoplanar in this paper. Hicoplanar lines differ from conventional CPWs in that the height of the conductors is very tall ( 10–200 m). The tall conductor walls of hicoplanar reduce the current density in the line and improve field confinement. It is possible to fabricate hicoplanar with line loss that is comparable to microstrip. LIGA methods have been most commonly employed to create hicoplanar [16]–[19]. Although micromachined transmission lines provide many advantages over conventional transmission lines, they currently have limitations. Fabrication complexity and cost of micromachined transmission lines limit easy integration into standard processes. Another significant limitation is that most micromachined transmission lines do not have a planar surface. This makes the integration of devices (such as active microwave circuits and micromachined switches) on top of the transmission lines difficult or impossible. In this paper, we introduce a novel micromachining method that creates hicoplanar with a planar surface. We have reported hicoplanar on silicon in previous publications [20], [21]. In this paper, we expand on the results presented in [20] by introducing an analytical model that predicts the transmission line parameters. The hicoplanar presented in this paper promises to overcome the current loss limitations of transmission lines in CMOS MMICs. The planar surface of the hicoplanar allows for integration with other devices on the wafer surface, thus

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TODD et al.: FABRICATION, MODELING, AND CHARACTERIZATION OF HIGH-ASPECT-RATIO CPW

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Fig. 1. 3-D schematic of hicoplanar fabricated on silicon (from [20]).

hicoplanar can also be used as a transmission-line platform for hybrid microwave integrated circuits (HMICs). A 3-D schematic of hicoplanar transmission lines on silicon is shown in Fig. 1.

Fig. 2. (a) Cross-sectional schematics of transmission lines used in impedance and attenuation simulations with dimension definitions. (b) Cross-sectional schematics of transmission lines used in isolation simulations with dimension definitions (after [20]).

II. ADVANTAGES OF HICOPLANAR Hicoplanar provides two main advantages to conventional transmission lines, including low conductor loss and high isolation, which were discussed previously [20], [21]. Here, we will explain these advantages in a more general form by comparing the normalized conductor loss and midband isolation of hicoplanar to conventional CPW and microstrip lines. The schematics in Fig. 2 define the cross-sectional geometries of the microstrip, CPW, and hicoplanar lines used in the comparisons. For CPW and hicoplanar conductor loss, we use derived equations that are presented in Section IV. We use Ansoft High Frequency Structure Simulator (HFSS) simulations to generate microstrip conductor loss, impedance, and isolation and CPW and hicoplanar isolation. We use a homogeneous dielectric in all three transmission lines, with a relative dielectric constant of one. Au conductors with conductivity of 3.5 10 S/m are used for all conductors. The transmission-line widths are kept constant at 300 m, and all calculations are evaluated at 30 GHz. To demonstrate the hicoplanar conductor loss advantage, we compare the normalized conductor loss versus impedance relationships of hicoplanar, microstrip, and conventional CPW lines. Fig. 2(a) shows single transmission-line geometries used to calculate conductor loss. The normalized conductor loss is taken as , where is the intrinsic impedance of free space, is the width of the transmission line, is the effective dielectric constant of the transmission line, and is the surface resistance of the conductor. The normalized , which makes the impedance impedance is taken as normalized to a homogeneous dielectric constant of one. The normalized conductor loss will depend on the absolute values of frequency, material parameters, and transmission-line dimensions somewhat, but these effects are not very significant. Thus, by using normalized parameters, we make the comparison valid

Fig. 3. Plots of normalized conductor loss versus normalized characteristic impedance for microstrip, conventional CPW, and hicoplanar transmission lines. The minimum hicoplanar loss curve traces the minimum conductor loss for hicoplanar lines with different conductor heights.

over a very wide range of possible geometries, materials, and frequencies. Fig. 3 compares the normalized conductor loss versus normalized impedance relationships of microstrip, conventional CPW, and hicoplanar. For microstrip, the signal line width is kept constant and the substrate height is adjusted to generate the loss-versus-impedance curve. For CPW, the transmission-line width is kept constant and the signal-to-width ratio is adjusted to generate the loss-versus-impedance curve. For hicoplanar, the transmission-line width is kept constant, and different conductor height-to-width ratios are evaluated. At each conductor height, the signal width is swept to generate the loss-versus-impedance curves. Fig. 3 shows that hicoplanar achieves a loss minimum at each conductor height. A trace of

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Fig. 4. Plots of midband isolation versus impedance for microstrip, conventional CPW, and hicoplanar transmission lines with a separation distance equal to . The hicoplanar minimum loss curve corresponds to geometries that give the minimum conductor loss as demonstrated in Fig. 4.

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Fig. 5. Process flow for creating hicoplanar transmission lines (from [20]).

these loss minimums shows that hicoplanar achieves low loss over a wide range of impedances. The hicoplanar minimum loss curve demonstrates that hicoplanar achieves lower loss than CPW for all impedances and lower loss than microstrip for lower impedances. To demonstrate the hicoplanar isolation advantage, we compare the midband isolation-versus-impedance relationships of hicoplanar, microstrip, and conventional CPW lihes. The midband isolation represents the worst case isolation between two transmission lines when their lengths are equal to . The midband isolation between two adjacent transmission lines is given by [22] (1) where and are the even- and odd-mode impedances of the two adjacent transmission lines that are coupled together. Fig. 2(b) shows the geometries of the coupled transmission lines used to calculate isolation. For all transmission lines, the transmission-line width is kept constant and the separation distance between the adjacent transmission lines is set to . For microstrip, the substrate height is adjusted to generate the isolation versus impedance curves. For conventional CPW, the signal-to-width ratio is swept to generate the isolation-versus-impedance curves. For hicoplanar, a series of conductor height-to-width ratios are analyzed, and at each conductor height the signal width is adjusted to generate the isolation versus impedance curves. Fig. 4 shows plots of the midband isolation versus impedance for microstrip, conventional CPW, and hicoplanar. The hicoplanar isolation curve is generated using the dimensions that give minimum hicoplanar loss that was demonstrated in Fig. 3. Fig. 4 shows that hicoplanar achieves superior isolation over all impedances to both microstrip and conventional CPW when the hicoplanar minimum loss dimensions are used. This

result, in combination with the conductor loss advantage shown previously, means that hicoplanar can achieve both lower conductor loss and higher isolation in a given chip area than microstrip and conventional CPW.

III. FABRICATION The fabrication method of the hicoplanar transmission lines, shown in Fig. 5, was discussed in detail in [20]. The process begins with silicon deep reactive ion etching (DRIE) to create mesas and trenches which define the topology of the hicoplanar. Next, wet thermal oxidation at 1050 C transforms the silicon mesas into thermal oxide, creating a low-loss dielectric for the transmission lines. An anisotropic SiO etch follows; this removes high-stress SiO from the bottom of the trenches. A Ti/Au seed layer is then deposited using a sputtering system with good step coverage. Au electroplating fills both the ground and signal trenches with conductor in the next step. Next, the top of the structure is planarized using lapping and CMP to electrically isolate the signal and ground lines. A final backside DRIE removes the silicon underneath the hicoplanar lines which isolates the electric field from the silicon substrate. This lowers the effective dielectric constant, raises the line impedance, and lowers the attenuation due to the conductivity of the silicon substrate. Two hicoplanar arrays with different characteristic impedances have been successfully fabricated. The dielectric widths are 8.85 and 11 m after thermal oxidation, and the conductor height is 38 m after lapping and polishing. A backside etch removed 450 m of silicon to isolate the transmission lines from the substrate. The Au conductivity was measured to be 3.5 10 S/m. Each hicoplanar array consists of a thru line, a short line, and line lengths of 100, 200, 400, 800, and 1600


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Fig. 6. SEMs of a hicoplanar thru line showing: (a) the topside after planarization and (b) the backside after backside silicon DRIE (from [20]).

m for thru-reflect-line (TRL) calibration. Fig. 6 shows scanning electron micrographs (SEMs) of the topside and backside of the hicoplanar arrays. One important limitation of the current process is that only relatively narrow SiO mesa widths can be achieved because larger mesa widths require long oxidation times [21]. This makes it practically difficult to produce hicoplanar lines with impedance greater than 30 . In future work, it is important to develop a process that allows for wider SiO mesas so that higher impedances can be achieved. Also important for future work is the development of a high-aspect-ratio copper electroplating process to replace the gold process. Copper would provide higher conductivity and lower transmission line loss, while being less expensive to fabricate than gold. Other issues to consider are fabrication yield and device reliability. A major factor that could limit the device reliability would be the response to thermal stress. Since SiO and Au have different coefficients of thermal expansion, any increase in temperature will cause stress to develop in both materials which could lead to cracking of the SiO and delamination of the metal from the dielectric surface. To test the device response to thermal stress, we cycled the temperature of the substrate after fabrication to 100 C for 2 h and then to 150 C for 2 h and examined the structures after each cycle. We noticed no cracking of the dielectric or delamination of the metal after both cycles were complete. It is also worth mentioning that, while taking microwave measurements, a substantial force was applied to the transmission lines by the probe tips. Since the devices have no silicon underneath them for mechanical support, they rely entirely on the Au/SiO membrane of the transmission line to support the applied force of the probe tips. The transmission lines withstood this force with no evidence of cracking or delamination.

IV. TRANSMISSION-LINE MODEL A quasi-TEM transmission-line model has been developed that is valid for both conventional CPW and hicoplanar. The model includes the finite thickness of the conductors and gives a closed-form expression for the resistance. Consider that the finite thickness of the conductors is important for hicoplanar, since hicoplanar is composed of tall conductors. The quasi-TEM model is developed by evaluating the capacitance and inductance between the different surfaces of the signal and ground lines. Fig. 7 shows the capacitances associated with the coupling

Fig. 7. Coupling between the different conductor surfaces in CPW represented by capacitances.

combinations between different surfaces. These include the ca, pacitance between the height of the conductor walls the capacitance between the ground and signal top and bottom surfaces , the capacitance between the ground conductor wall and signal top and bottom surfaces , and the capacitance between the signal conductor wall and ground top and bottom surfaces . is the capacitance of the paris the capacitance of infinitely allel-plate waveguide and thin CPW. Both are easily obtainable and have been derived previously in literature [22], [23]. and are more difficult to analyze, however, especially when the field lines between the surfaces enter two different dielectrics. Obtaining closed-form expressions for coupling between surfaces with mixed dielectrics can be difficult using standard modeling techniques, such as conformal mapping [24]. Fortunately, for CPW and hicoplanar, the coupling between the conductor sidewalls and the top and bottom surfaces will be weak and much smaller than the coupling between the other surfaces. Therefore, as an approximation, and can be ignored. This approximation is most valid when the signal width and conductor height are large. The validity range of the model will be explored in a later part of this paper. The approximation can also be thought of as placing a magnetic wall at the dielectric interfaces, as shown in Fig. 8. The topography and dimensions used in the model are defined in Fig. 8. The magnetic walls enable the CPW transmission line to be split into two transmission lines, parallel-plate waveguide and infinitely thin CPW, connected in parallel as shown in Fig. 8. This makes a closed-form analytical solution possible, because the circuit parameters of CPW can be evaluated by combining the already known circuit parameters of the parallel-plate and infinitely thin CPW. The equivalent circuit model of CPW comprises the circuit elements of two parallel-plate waveguides (represented by , and ) connected in parallel to the circuit elements of infinitely thin CPW (represented by , and ) as shown in Fig. 9. A. Parallel-Plate Element Equations Now that we have established that CPW is composed of parallel-plate and infinitely thin CPW circuit elements, we will list the formulas for these elements, based on geometrical and material parameters. Pozar gave equations for the elements of parallel-plate waveguides [22]. Based on these equations, it is

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Fig. 8. Dimensions and material property definitions for hicoplanar. The figure shows that, by placing magnetic walls at the dielectric interfaces, CPW can be split into two parallel-plate waveguides in parallel with infinitely thin CPW.

Fig. 9. Transmission-line circuit model of CPW comprising the combination of parallel-plate and infinitely thin CPW elements.

straightforward to show that the inductance, capacitance, resistance, and conductance of two parallel plates connected in parallel are respectively given by

(2) (3) (4) (5) where is the free-space permeability, is the free-space permittivity, is the relative dielectric constant, is the dielectric loss tangent, is the angular frequency, is the conductor height, is the dielectric gap width, is the skin depth of the conductor, and is the conductor surface resistivity. accounts for the self inductance caused by the skin effect by adding the skin depth to the dielectric gap width. Notice that the parallel-plate elements are strongly dependent on the height-to-gap-width aspect ratio of the dielectric . B. Infinitely Thin CPW Element Equations Wen introduced the transmission-line calculations for infinitely thin CPW by using conformal mapping techniques [23]. The conformal mapping of infinitely thin CPW results in an important function with elliptical integrals given by

(6) where is the complete elliptical integral of the first kind. This function with the argument equal to the signal-to-width

Fig. 10. Diagram of infinitely thin CPW conductor showing the regions used to calculate R using perturbation theory and Wheeler’s inductance rule. Also shown are the electric and magnetic field lines on the conductor surfaces.

, is used in the calculations of the ratio, given by infinitely thin CPW inductance, capacitance, resistance, and conductance and is constant and independent of frequency. The equations for infinitely thin CPW elements reported in this paper are similar to those introduced by Heinrich [25], except that a different approach is used for calculating the infinitely thin CPW resistance . is the most difficult parameter to analyze because neither perturbation theory nor Wheeler’s inductance rule can be used alone in its calculation for infinitely thin CPW. Perturbation theory cannot effectively calculate the resistance, because integrating the current density across the entire span of the transmission line results in singularities at the edges of the conductors. Wheeler’s inductance rule cannot be used alone in the calculation of the resistance, because retracting the edges of the conductors by only accounts for current that is within of the gap edges. Holloway and Kuester showed that the CPW resistance can be approximated using perturbation theory by integrating the current density to an appropriate stopping distance away from the gap edges [26]; this prevents the calculation from being singular. Finding the appropriate stopping distance using this method requires a lookup table, however, that is only applicable to CPW with finite thickness. We have found that combining perturbation theory with Wheeler’s inductance rule is effective in calculating the infinitely thin CPW resistance. Consider the diagram of the infinitely thin conductor of the CPW in Fig. 10. The idea here is that the current that exists within a skin depth of the conductor edges is due to magnetic fields that penetrate the conductor normal to the surface. Therefore, Wheeler’s incremental inductance rule can be used to calculate resistance in this regime. Current that exists everywhere else on the conductors past a skin depth from


the conductor edges is due to magnetic fields that penetrate the conductors tangent to the conductor surfaces. Therefore, perturbation theory can be used to calculate the resistance in this regime. The regions of the conductors where Wheeler’s incremental inductance rule and perturbation theory are used to calculate the resistance are shown in Fig. 10. Wheeler’s inductance rule is used calculate the resistance in the intervals from , and . Perturbation theory is used to calculate the resistance in the remaining intervals from , and . The part of the infinitely thin CPW resistance calculated using perturbation theory is found by using the equation provided by Holloway and Kuester [26], and is given by where the stopping distance is

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is the complete ellipat the bottom of this page, where tical integral of the second kind and . Now, we can calculate the contribution of the incremental inductance to the infinitely thin CPW resistance by evaluating , which yields (11), shown at the bottom of this page. The total infinitely thin CPW self inductance and resistance and are respectively given by . Now, we can list the circuit element parameters of infinitely thin CPW including inductance, capacitance, resistance, and conductance which are given, respectively, by

(7) There will be a contribution to the self inductance from the current in the perturbation region that is given by which yields

(12) (13)

(8) The remaining part of the infinitely thin CPW resistance is calculated by applying Wheeler’s inductance rule to the ideal conductor inductance. The ideal conductor inductance is the inductance of the infinitely thin CPW assuming perfect conductors and is given by

(14)

(9)

(15)

by differentiaApplying Wheeler’s inductance rule to tion yields the incremental inductance [27] given by (10), shown

is the relative dielectric constant of the substrate and is the loss tangent of the substrate. The model can predict transmission-line parameters before and after the silicon where

(10)

(11)

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substrate is removed underneath the transmission line. The caand conductance of the infinitely thin CPW pacitance region are the only parameters affected by the silicon substrate. When the substrate is removed, the infinitely thin CPW capacitance becomes , and the conductance be. comes zero Notice that all of the infinitely thin CPW elements are heavily and, thus, are mostly affected by the dependent on . signal to width ratio C. CPW Element Equations and Output Parameters Now that we have all of the elements of parallel-plate and infinitely thin CPW, we can calculate the element values for CPW by evaluating the transmission-line circuit in Fig. 9. Again, this derivation for CPW parameters is valid for hicoplanar because we consider the finite thickness of the conductors. The CPW inductance, capacitance, resistance, and conductance are, respectively, given by

small to have negligible effect on the inductance (i.e., The CPW characteristic impedance is found by evaluating

).

(21) is the intrinsic impedance of free space. where shown in (21) is found by evaluThe approximate form of and assuming the skin depth is ating sufficiently small to have negligible effect on the inductance ). The attenuation constant is given by (i.e.,

(22) and are the conductor loss and dielectric loss, rewhere spectively. The conductor loss can be approximated by evaluating , which yields (23)

(16)

The dielectric loss can be approximated by evaluating , which yields

(17)

(18)

(19) The output parameters of CPW transmission lines can be calculated using the CPW elements. The effective dielectric constant is found from the phase constant and is given by

(20) , shown in (20), is found by The approximate form of evaluating the approximate form of the phase constant and assuming the skin depth is sufficiently

(24) Again, all of these equations can be used for transmissionline parameters after the substrate is removed by simply setting and . The approximations of the output parameters are very simple and show that the output parameters are largely affected by the geometry ratios and . This is a very useful tool for optimizing CPW transmission lines because it is easy to see how the geometry affects the output parameters through these simple equations. D. Model Verification and Validity Range To verify the accuracy of the model, we have compared model calculations to HFSS simulations for a wide range of CPW geometries. We include geometries with thin conductors for conventional CPW and thick conductors for hicoplanar. In these comparisons, both the model calculations and simulations use CPW and hicoplanar with no substrate, gold conductors ( 3.5 10 S/m), and SiO dielectrics . The frequency is 30 GHz for all calculations and simulations. The output parameters are mostly affected by the height-to-gap ratio and the signal-to-width ratio . We use these ratios as the basis for comparing the calculations to the simulations. To evaluate how the lateral dimensions affect the device behavior, we sweep the signal-to-width ratio from 0.05 to 0.95, which is over most of its entire range from 0 to 1. To evaluate how the vertical dimensions affect the transmission-line behavior, we use different height-to-width ratios of 0.01, 0.5, and 2. The


Fig. 11. Calculations and simulations of effective dielectric constant versus signal-to-width ratio for height-to-width ratios of 0.01, 0.5, and 2 and transmission-line widths of 100, 300, and 1000 m.

height-to-width ratio is simply related to the height-to-gap ratio by

(25) We use the height-to-width ratio so that the overall size of the transmission line stays constant when we sweep the signal-towidth ratio. We also use a very small value of to represent a conventional CPW line to show that the model can successfully predict the parameters of conventional CPW. Finally, to evaluate the scalability of the model, we calculate and simulate the described geometry ratios at different transmission line widths of 100, 300, and 1000 m, covering a wide range of the overall size of the transmission line. Fig. 11 shows the effective dielectric constant versus signal-to-width ratio. The curves show that stays relatively constant as increases. This is because both the parallel-plate and infinitely thin CPW capacitance increase as increases, which mostly cancels any effect on the effective dielectric constant. At high , the effective dielectric constant increases because the inductance lowers to a point to where becomes comparable to . At this point, contributes to the phase constant, which lowers the velocity of the line and increases the effective dielectric constant. The effective dielectric constant increases as increases because a higher increases the relative contribution of the parallel-plate capacitance which brings closer to . has little effect on , meaning that is mostly scalable. The calculations and simulations match well for all values of and . When and , the effective dielectric constant deviates most substantially from the simulations. This is because the magnetic field approximation is less accurate for this particular geometry. Even in this range, however, the model matches the simulations quite well. Fig. 12 shows calculations and simulations of normalized characteristic impedance versus the signal-to-width ratio for the

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Fig. 12. Calculations and simulations of characteristic impedance versus signal-to-width ratio for height-to-width ratios of 0.01, 0.5, and 2 and transmission-line widths of 100, 300, and 1000 m.

and described above. We use nordifferent values of malized impedance so that the curves become valid for any combinations of dielectric constants that could be used in model. The plots show that decreases as increases. This is because a higher increases and and lowers and . Similarly, decreases as increases because a higher increases the parallel-plate capacitance and lowers the parallel-plate inductance. It is immediately noticeable that the curves for the different values of track each other almost exactly. This means that is almost solely dependent on the geometry ratios, and the transmission-line width has virtually no effect. Thus, the model is scalable for the characteristic impedance. The calculations match the simulations very well for all values except when and . As was the case with the effective dielectric constant, the deviation in this region is due to the magnetic field approximation becoming less accurate for this geometry. Nevertheless, the model matches the simulations quite well in this range and shows the same trends. The conductor loss is intrinsically not scalable and will decrease as increases. This is because, even though the characteristic impedance does not change with , the line will decrease as increases. However, resistance the conductor loss can be normalized to be mostly scalable by taking , as was described in Section II. This makes the attenuation constant mostly scalable with respect to width, frequency, conductor conductivity, and dielectric constant. Fig. 13 shows the normalized conductor loss versus signal-to-width ratio. Notice that there is a more substantial difference between the curves for different compared with the previous plots. This is because there are terms in in (14) that depend on the absolute value of , and . Fig. 13 shows that the model and simulations predict a minimum conductor loss at a certain for a given . Both the CPW resistance and impedance decrease as increases, so this minimum attenuation occurs when the ratio between resistance and impedance is minimum. The calculations match the simulations within 10% for all values except when

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Fig. 13. Calculations and simulations of normalized conductor loss versus signal-to-width ratio for height-to-width ratios of 0.01, 0.5, and 2 and transmission-line widths of 100, 300, and 1000 m.

Fig. 14. Effective dielectric constant versus frequency of a 1600-m-long line with 11-m-wide SiO before and after silicon removal (from [20]).

and . The reason why the model does not match the simulations well in this range is because this geometry encourages coupling between the conductor sidewalls and top surfaces and, therefore, makes the magnetic wall approximation less accurate. Nevertheless, even for values in this range, the model calculations come close to the simulation predictions and show the same trends. Therefore, the model provides a useful tool for analyzing all possible conventional CPW and hicoplanar geometries. The agreement of the conductor loss at small is especially noteworthy, because it verifies the ability of the model to predict the conductor loss of conventional CPW. The model is mostly scalable, with the only exception being the conductor loss. The scalability is important because it simplifies the input parameters that one has to consider when considering making a design. V. EXPERIMENTAL RESULTS Microwave measurements were conducted on the fabricated devices described in Section III and are described in detail in [20]. Microwave measurements were taken using an Agilent E8364A network analyzer, and simulations were conducted in HFSS. The measurement and simulation results were compared with the CPW transmission-line model. The transmission-line parameters were measured before and after silicon was removed underneath the substrate. The characteristic impedances of the transmission lines were measured by first performing short-open-load-thru (SOLT) calibrations using a 50- calibration substrate from 1 to 50 GHz. Next, parameters were measured from the hicoplanar lines and converted into parameters using the 50- reference impedance. The characteristic impedance of each line was calculated using . Thru-reflect-line (TRL) calibrations of the hicoplanar transmission lines were performed to extract the propagation constant from 1 to 50 GHz. After calibration, -parameters were measured in each line and converted to parameters; the propagation constant was calculated using , where is the attenuation constant, is the phase constant, and is the line length. The

Fig. 15. Characteristic impedance versus frequency of a thru line with 11-m-wide SiO before and after silicon removal (from [20]).

phase constant was used to extract the effective dielectric constant using , where is the vacuum speed of light. Figs. 14–16 show measurements, simulations, and calculations of effective dielectric constant, characteristic impedance, and attenuation versus frequency, respectively. Fig. 14 shows that the effective dielectric constant decreases after silicon is removed. After silicon is removed, the effective dielectric constant becomes lower because the fields are not exposed to the high dielectric constant of Si. The lower effective dielectric constant both raises impedance and lowers attenuation as shown in Figs. 15 and 16, respectively. The simulations and calculations match very closely for all parameters, further verifying the accuracy of the described model for predicting hicoplanar parameters. The measurement data are in relative agreement with the simulations and calculations, but do not match perfectly. In Fig. 14, the effective dielectric constant measurements do not cover the entire frequency range. The measurement data are only shown in the


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The accuracy of the model is most strongly verified by the agreement with HFSS simulations. The relative agreement of the measurement data to the model also support the accuracy of the model and verify its usefulness for predicting the hicoplanar transmission-line parameters. VI. CONCLUSION

Fig. 16. Attenuation constant versus frequency of a 1600-m-long line with 11-m-wide SiO before and after silicon removal (from [20]).

range where the TRL calibration is accurate, which is within the phase range of 20 –160 . The measured effective dielectric constant matches well with the predictions before silicon is removed but is slightly lower than the predictions after silicon is removed. After silicon is removed, the probe tips deflect the transmission line slightly during measurement because there is no solid substrate underneath for mechanical support. The deflection could change the topography of the transmission line enough to cause a slightly different measured effective dielectric constant than predicted. In Fig. 15, it is noticeable is that the measured impedance is higher than the simulated and calculated impedances before and after silicon is removed. A SOLT calibration was used for impedance measurements, so the discrepancies between the measurements and predictions could be caused by parasitics that exist between the probe tip and the transmission-line cross section that lead to a difference in the measured impedance. SOLT calibration has other problems, such as the different contact conditions between the calibration substrate and device under test that lead to inaccuracies in measurement data, especially at higher frequencies. For future measurements, a better calibration technique, such as the calibration comparison method, could be used to obtain more accurate impedance measurements [28]. The calibration comparison method eliminates inaccuracies due to parasitics and makes the measurement of impedance closer in accuracy to measurements obtained from TRL calibration. In Fig. 16, the attenuation constant was averaged using 21 data points over a span of 5 GHz for each value shown in Fig. 16. The error bars in Fig. 16 represent the range of one standard deviation greater and less than each point on the plot. The measured attenuation before silicon is removed matches the predictions well up to 30 GHz, but, after 30 GHz, the measured loss shows a peak. This peak is due to loss inaccuracy of the TRL measurement, as it occurs almost exactly where the phase of the measured line is 180 . The measured , after silicon is removed, follows the predictions but does not match as well. This could also be due to the probing deformation described previously.

A novel micromachining process has been developed to create high-aspect-ratio coplanar waveguides (hicoplanar) using a silicon substrate. The process combines DRIE, thermal oxidation, electroplating, and planarization to create hicoplanar with a planar surface. Hicoplanar transmission lines were fabricated where silicon was successfully removed underneath the lines using backside DRIE. The advantages of hicoplanar were demonstrated, including low conductor loss over a wide impedance range and low loss and high isolation in a given chip area. A new transmission-line model for CPW and hicoplanar was introduced and compared with simulations. The model was proven to be accurate for a wide range of conventional CPW and hicoplanar geometries and was verified experimentally. Hicoplanar arrays with characteristic impedances between were successfully fabricated. Attenuation constants 18–25 were measured to be 1.7–2.4 dB/cm at 30 GHz after silicon removal. The measurements of characteristic impedance, effective dielectric constant, and attenuation constant showed close agreement to the simulations and model calculations. ACKNOWLEDGMENT The authors would like to thank T. Bosch for help with electroplating and H.-W. Chen for help with microwave measurements. REFERENCES [1] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “Millimeter-wave CMOS design,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 144–155, Jan. 2005. [2] H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell, “Millimeterwave CMOS circuit design,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 472–477, Feb. 2005. [3] B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad, “Millimeterwave devices and circuit blocks up to 104 GHz in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2893–2903, Dec. 2007. [4] C.-S. Lin, P.-S. Wu, H.-Y. Chang, and H. Wang, “A 9–50-GHz Gilbertcell down-conversion mixer in 0.13-m CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 293–295, May 2006. [5] S. Gunnarsson, C. Karnfelt, H. Zirath, R. Kozhuharov, D. Kuylenstierna, C. Fager, M. Ferndahl, B. Hansson, A. Alping, and P. Hallbjorner, “60 GHz single-chip front-end MMICs and systems for multi-Gb/s wireless communication,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1143–1157, May 2007. [6] V. Milanovic, M. Ozgur, D. C. DeGroot, J. A. Jargon, M. Gaitan, and M. E. Zaghloul, “Characterization of broadband transmission for coplanar waveguides on CMOS silicon substrates,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 632–640, May 1998. [7] T. S. D. Cheung and J. R. Long, “Shielded passive devices for siliconbased monolithic microwave and millimeter-wave integrated circuits,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1183–1200, May 2006. [8] N. H. Tea, V. Milanovic, C. A. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid postprocessing etching for CMOS-compatible MEMS,” J. Microelectromech. Syst., vol. 6, no. 4, pp. 363–372, Dec. 1997. [9] C. Y. Chi and G. M. Rebeiz, “Planar microwave and millimeter-wave lumped elements and coupled-line filters using micromachining techniques,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 4, pp. 730–738, Apr. 1995.

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Ka

Shane T. Todd (S’03–M’09) received the B.S. (magna cum laude) and M.S. degrees in electrical engineering from the University of Florida, Gainesville, in 2003 and 2005, respectively, and the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, in 2010. He has authored or coauthored five journal papers and seven conference papers and has one patent pending. His current research interests include the design, modeling, fabrication, and characterization of microwave and microelectromechanical systems devices. He is currently a Senior Research Engineer with the Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Singapore.

Xiaojun T. Huang received the B.S. degree in physics from the University of Science and Technology of China, Hefei, China, the M.S. degree in physics from the University of Virginia, Charlottesville, and the Ph.D. degree in electrical engineering from Cornell University, Ithaca, NY. He is now an Associate Project Scientist with the University of California, Santa Barbaba (UCSB). Prior to joining UCSB, he held various industrial positions focusing on research involving RF, microelectromechanical systems, and optics. He has authored or coauthored 15 journal and conference papers and holds four patents. His current research involves the integration of sensors in nanochannels for the control and detection of biomolecules.

John E. Bowers (S’78–M’81–SM’85–F’93) received the M.S. and Ph.D. degrees from Stanford University, Stanford, CA. He is Director of the Institute for Energy Efficiency and a Professor with the Department of Electrical Engineering, University of California, Santa Barbara (UCSB). He holds the Fred Kavli Chair in Nanotechnology. He has authored or coauthored six book chapters, 350 journal papers, and 600 conference papers and holds 38 patents. His research interests include optoelectronic devices and energy efficiency. Prof. Bowers is a Fellow of the Optical Society of America and the American Physical Society and a member of the National Academy of Engineering. He was a recipient of the IEEE LEOS William Streifer Award and the South Coast Business and Technology Entrepreneur of the Year Award.

Noel C. MacDonald (S’61–M’67–SM’91–F’94) received the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1967. He is a Professor Emeritus with the Department of Mechanical Engineering, University of California, Santa Barbara (UCSB). He has authored or coauthored over 100 papers and several book chapters and holds 61 patents. Before joining UCSB, he held the Acheson/Laibe Professorship in Engineering at Cornell University, Ithaca, NY. From 1997 to 1999, he served as Director of the Microsystems Technology Office, Defense Advanced Research Projects Agency. His current research interests include micro/nano-electromechanical systems. Prof. MacDonald is a Member of the National Academy of Engineering.