Fabrication of ISFET microsensor by diffusion-based Al gate NMOS ...

Indian Journal of Pure & Applied Physics Vol. 50, March 2012, pp. 199-207

Fabrication of ISFET microsensor by diffusion-based Al gate NMOS process and determination of its pH sensitivity from transfer characteristics V K Khanna MEMS & Microsensors Group, Central Electronics Engineering Research Institute (CEERI) Council of Scientific and Industrial Research (CSIR), Pilani 333031 (Rajasthan), India E-mail: [email protected] Received 28 July 2011; revised 23 November 2011; accepted 16 January 2012 The present paper describes the fabrication of ISFET (Ion-Sensitive Field-Effect Transistor) by a four-mask, thermal diffusion-based process. The sequence of physical and chemical processes for ISFET fabrication has been elaborated. In the first photomasking step, the regions for source and drain diffusion have been opened. The second photolithography defined the gate area. In the third photolithographic step, contact windows have been opened, and in the fourth photolithographic step, the metal pattern has been delineated. After completion of the fabrication process, the wafer has been diced into chips, which have been mounted on ceramic substrates to provide electrical connections for source, drain and substrate. Except for the gate region, the whole chip and wire bonds have been protected with insulating epoxy. For process characterization, current-voltage characteristics of MOSFET test devices simultaneously fabricated on the same wafer have been measured for gate-source voltages from –5 to +5 V. These were found to be N-channel, depletion-mode devices indicating similar behaviour for ISFETs. The pH-response of ISFET has been evaluated by drawing its IDS−VGS characteristics after immersion in standard buffer solutions and applying the gate-source voltage through Ag/AgCl reference electrode. From these transfer characteristics, pH-sensitivity of ISFET has been determined by finding the gate-source voltage necessary to ensure constant IDS, VDS condition. Technological shortcomings of this work have also been pointed out, and necessary remedial measures have been suggested. Keywords: Chemical sensor, Ion sensor, pH sensor, ChemFET, ISFET, Analytical device

1 Introduction The field of micro-fabricated chemical sensors based on ion-sensitive field-effect transistors (ISFETs) has attracted the attention of researchers since Bergveld introduced the ISFET concept1-4 in 1970. ISFET is one of the three types of CHEMFETs (chemically-sensitive field-effect transistors) which derive their name from the type of interaction that governs their response5: (i) ISFET, which is a direct miniature equivalent of ion-selective electrode (ISE); (ii) enzymatically selective field-effect transistor (ENFET), which is equivalent of a potentiometric enzyme electrode; and (iii) the work function fieldeffect transistor (WF-FET), which has its macroscopic counterpart in Kelvin Probe. What makes field-effect transistors particularly suitable for miniaturization is the fact that the signal does not depend on the size of the sensing area. Moreover, the power (i.e., current × voltage) of the measured signal is very small. The initial motivation for ISFET originated from its advantages over conventional ion-selective electrode such as small size and solid-state nature, bulk manufacturing, short response time, high input impedance and low output impedance6,7. Other

features such as the integration of compensation and data processing circuits in the same chip offered new perspectives for these sensors. There has been a virtual deluge of research publications on ISFET during the last decade, a few of which are cited here8-15. An ISFET, electronically identical to a MOSFET (apart from the circuitry of the gate), is a microelectronic device, with the additional feature of the ability of chemically modifying the threshold voltage via the interfacial potential at the electrolyte/oxide interface. The threshold voltage of ISFET is expressed3 as:

VTh = E ref − ψ + χ sol −

° ( Q + Qss + QB ) ½° − ® ox ¾ + 2ϕf q ¯° Cox ¿° … (1)

ϕSi

where Eref is the constant potential of the reference electrode, −Ȍ+Ȥsol is the interfacial potential at the solution/oxide interface of which Ȍ is the chemical input parameter, a function of the solution pH and Ȥsol is the surface dipole potential of the solvent and thus

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having a constant value. ĭSi is the work function of silicon and q is the elementary electronic charge. The fifth term on right-hand side is due to accumulated charge in the oxide (Qox), at the oxide-silicon interface (Qss), and the depletion charge in the silicon (QB), with Cox representing the oxide capacitance per unit area, whereas the last term determines the onset of inversion depending on the doping level of silicon; it is given by: § kT © q

ϕf = ¨

· § NA · ¸ ¸ ln ¨ ¹ © ni ¹

… (2)

k is the Boltzmann constant, T is the temperature in kelvin scale, NA is the acceptor concentration of p-type wafer and ni is the intrinsic carrier concentration of silicon. The ion adsorption processes at the electrolyte-SiO2 interface are described by the well-known site-binding model. For silicon dioxide dielectric, the oxide surface (i.e. pH sensitive surface) contains three types of sites: Si−O−, Si−OH, and Si−OH+. Therefore, the oxide surfaces are amphoteric, meaning that the surface hydroxyl groups can be neutral, protonized (thus positively charged) or deprotonized (thus negatively charged) depending on the pH of the bulk solution; and the surface potential3 Ȍ is: § kT · β ½ ¾ p H pzc − pH ¸® © q ¹ ¯ ( β + 1) ¿

ψ = 2.3 ¨

(

)

… (3)

where pHpzc, known as the pH at the point of zero charge, is the value of the pH for which the oxide surface is electrically neutral and ȕ, the sensitivity parameter, determines the final sensitivity of the device. The value of ȕ is expressed in terms of the acidic and basic equilibrium constants of the surface reactions, for which a parameter [H+]s is introduced, which represents the surface concentration of H+ ions, being related to the [H+] bulk value by Boltzmann statistics. Figure 1 shows the cross-section of ISFET and the geometrical layout that produces this structure. Currently, pH-ISFET probes are commercially available from several companies all over the world. A large number of fabrication methods for ISFET sensors have been proposed during the last forty-two years. The self-aligned polysilicon gate process, Fig. 2, marked the beginning of modern16 MOSFETs. It is primarily based on ion implantation technique. It

Fig. 1 — (a) Schematic cross-section of ISFET and (b) Geometrical layout for producing the structure in (a); the channel may be configured vertically, horizontally or in interdigitated form by appropriate layout of source/drain regions, as shown in inset at the left. The ISFET chip is mounted on a ceramic substrate/PCB having conductor lines. Wires are attached for connecting the bonding pads on the chip with conductor lines on the substrate. The wire bonds and edges of the chip are covered with insulating epoxy to prevent short-circuiting of source and drain on immersion in analyte solution

Fig. 2 — (a) Simplified polysilicon gate NMOS process: (a) Starting silicon wafer, (b) Field oxidation, (c) Active area photolithography (Mask-1), (d) Silicon dioxide growth, and polysilicon deposition, (e) Polysilicon gate photolithography (Mask-2), (f) Phosphorous implantation and annealing, (g) CVD oxidation, (h) Contact window opening photolithography (Mask3), (i) Al metallisation and (j) Al patterning photolithography (Mask-4).

KHANNA: FABRICATION OF ISFET MICROSENSOR

offers the self-aligned structure obtained by using the gate as the mask for the source-drain implant. This self-aligned structure reduces the device size. A gate length reduction provides a shorter transit time and hence, a faster device with a good frequency response. In addition, it eliminates the large overlap capacitance between gate and drain, while maintaining a continuous inversion layer between source and drain. Ion implantation replaced diffusion primarily because of its superior control and uniformity. It allowed several flexibilities in the process, e.g., field implant is applied for building channel stopper regions. The field implant increases the doping density under the oxide and thereby, increases the threshold voltage of the parasitic transistor formed by the metal wiring on top of the isolation oxide. Also, boron-enhancement threshold-adjustment implant is done for threshold voltage control because positive charges in the gate oxide decrease the threshold voltage, making it negative. In an NMOS fabrication sequence employing the field and channel implants17, first a thin oxide (350Å) is grown followed by silicon nitride deposition (1500Å). After defining the active area by a photo resist mask, a boron channel stop is implanted through (photoresist+SiO2+Si3N4) layer. Etching of the nitride layer that is not covered by the photo resist, and stripping of the photo resist is followed by growth of thick field oxide. The composite oxide-nitride layer over the active area is then removed, and a thin oxide layer (thickness < 100Å) is grown according to the specified threshold voltage. For N-channel, enhancement mode device, boron implantation is performed in the channel region. Next polysilicon is deposited and heavily doped with phosphorous to 20-30 ohms/sq. Patterning the gate, phosphorous implantation is done for source and drain. This is ensued by phosphorous drive-in and oxidation. After depositing a phosphorous-doped oxide glass (p-glass) over the entire wafer, and smoothing the surface topography by heating, contact windows are opened. Then Al metallization and patterning are carried out as before. Fig. 3 shows the process flow. Although very versatile and widely adopted, the complex implantation-based process for NMOS ICs is not essential for ISFET fabrication because there is no polysilicon or aluminium layer on the gate, and the gate dielectric is free to interact with the analyte solution. Further, the ISFET is a long-channel device and such an intricate process is not required. In this

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paper, a process sequence employing aluminium gate NMOS technology (Fig. 4) and relatively inexpensive thermal diffusion (instead of ion implantation) is presented. Starting with p-type silicon wafer, thick field oxide has been grown. Photolithography by first source-drain diffusion mask has been done for opening the windows for phosphorous diffusion. To

Fig. 3 — Polysilicon gate process including field and channel implants: (a) Starting silicon wafer, (b) Thin SiO2+Si3N4, (c) Field area photolithography (Mask-1) and boron implantation, (d) Boron drive-in, (e) Field oxidation, (f) (Oxide+Nitride) removal (Mask-2), (g) Gate oxide growth, (h) Channel implantation, (i) Polysilicon deposition, (j) Polysilicon gate photolithography (Mask-3), (k) Source and drain implantation, (l) Phosphorous drive-in, oxidation and glass flow, (m) Contact window opening (Mask-4), (n) Al metallization (o) Metal patterning (Mask-5) and etching

Fig. 4 — Al gate NMOS process: (a) Starting silicon wafer, (b) Field oxidation, (c) Source/drain photolithography (Mask-1), (d) Phosphorous diffusion, (e) Gate oxide removal photolithography (Mask-2), (f) Silicon dioxide growth, and silicon nitride deposition, (g) Contact window opening photolithography (Mask-3), (h) Al metallisation and (i) Al patterning photolithography (Mask-4)

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prevent the formation of n+-p junction diode on reverse side, the backside oxide was protected by photo resist during etching. Second gate region definition mask was used to remove the field oxide from this area. Thin gate oxide has been grown by trichloroethane oxidation and covered by silicon nitride by low-pressure chemical vapour deposition; the Si3N4 layer is the pH-sensing layer of the device. Third mask has been used for contact window opening followed by reactive ion etching of nitride and oxide films. Aluminium sputtering was done on both sides of the wafer. The fourth mask was for metal pattern delineation on the front side with the backside metal protected by photo resist during Al etching. The resulting ISFET device behaves as an N-channel, depletion-mode device. All the unit processes used in ISFET fabrication are described in detail. Phosphorous diffusion and drivein are done in the same furnace in one step. Al-gate MOSFET devices are incorporated in the mask design for process evaluation at wafer level. Further, using an Ag/AgCl reference electrode, a bias has been applied to the insulating gate of packaged ISFET through the analyte solution. The pH sensitivity of ISFET has been extracted from IDS–VGS characteristics in different pH standard buffers. 1.1 ISFET Chip Layout and Mask Design

A primary design consideration is that the drain and source areas are often designed long enough to avoid metal contacts to be close to the gate area, which is exposed to the solution18-21. Operating voltage requirements impose constraints on resistivity of silicon wafer. Threshold voltage is determined by material resistivity in addition to gate dielectric thickness. Transconductance is mainly dictated by the channel aspect ratio (channel width/channel length). Four masks were designed for ISFET fabrication. Their functions are as follows: (i) Source/drain diffusion mask, (ii) Gate oxide removal mask; the channel length was 20 µm., (iii) Contact window opening mask, and (iv) Metal pattern definition mask.

2 Experimental Details 2.1 ISFET Chip Fabrication

The main process steps are shown in the block diagram of Fig. 5, and are briefly presented below: The p-type Czochralski (CZ) silicon wafers (resistivity=10-20 ohm-cm, orientation , diameter 100 mm, thickness 525 µm) were cleaned by RCA cleaning process, developed by the Radio

Fig. 5 — Detailed process flow chart for ISFET fabrication

Corporation of America comprising the following steps: (i) removal of insoluble organic contaminants with a 5:1:1 H2O:H2O2:NH4OH solution at 80°C for 10 min; (ii) etching of thin silicon dioxide layer using a diluted 50:1 H2O:HF solution at 25°C and (iii) removal of ionic and heavy metal atomic contaminants using the solution of 6:1:1 H2O:H2O2:HCl at 80°C for 10 min. All the steps were followed by rinsing in running deionised water resistivity=18 MΩ-cm). The oxidation cycle was 15 min dry [flow rate 6 SLM (standard litre per minute)] +7 h wet (1 SLM) +15 min. dry (6 SLM) at 1000ºC. In the wet part of the cycle, oxygen was bubbled through water at 95°C. Dry oxidation: Si (solid) + O2 (gas) = SiO2 (solid); wet oxidation: Si(solid) + 2H2O (vapour) = SiO2 (solid) + 2H2 (gas). Wafers were moisture-baked at 140°C for 1 h. Positive photo resist S1818 was coated at 2000 RPM for 30 s on both sides of the wafer. Soft baking was done at 90°C for 30 min followed by UV exposure for


3-3.5 s through mask-1, using MA6 Double Sided Mask Aligner (λ= 365/405 nm), developing for 25 s and post baking (hard baking) at 120°C for 30 min. Oxide etching was done from front side of the wafer in buffer HF for 9 min (etch rate~ 700Å-1000Å per min). The wafers were immersed in BHF, initially for 7 min, checked by optical microscope and again dipped for 60+60 s in buffer HF until they showed hydrophobic nature in water. Then thorough DI water rinsing was done. The wafers were dried in nitrogen. Photo resist was removed in acetone. After water rinsing, Piranha cleaning (98% H2SO4 and 30% H2O2 in volume ratios of 3:1 for 20-25 min) was done. Wafers were rinsed in deionised water. Phosphorous diffusion was done at 1050ºC for 30 min. N2=150 standard cubic centimetre (sccm) which served as the carrier gas; and O2=5 SLPM: 4POCl3 + 3O2 =2P2O5 +6Cl2; 2P2O5+5Si =4P + 5SiO2; Phosphosilicate glass (PSG) was formed on the surface of the wafer and acted as the impurity source. The junction depth was 1.2 µm. Phosphosilicate glass (PSG) was removed in dilute HF. The ratio HF: water was 1:10, etching time =90 s. Sheet resistance of N+ layer was found to be 1.64 Ω/square. Photolithography for gate oxide removal (Mask-2) was done, as with mask-1. Oxide was etched by wet method. Trichloroethane oxidation: Growth temperature was 1000ºC, time=60 min., N2 carrier flow=120 sccm, O2 flow = 400 sccm. Main O2 flow = 8 SLPM. This oxide improves the device characteristics by reducing the contaminations from furnace gases/ chemicals which are carried away in outgoing gas by combining with chlorine present during gate oxide formation. Nitridation by low-pressure chemical vapour deposition (LPCVD): Deposition time=23 min, temperature: 800ºC, 80 sccm ammonia (NH3) gas and 20 sccm dichlorosilane (DCS:SiH2Cl2) gas were introduced in vacuum=270 mtorr and reacted. Photolithography for contact window opening (Mask-3): Same procedure as with mask-1 above. Reactive ion etching (RIE) of silicon nitride and silicon dioxide: 40 sccm CF4 or SF6 and 4 sccm O2, were used, and etching was done for 4 min 30 s at 600W RF. The vacuum during this process was 10 Pa. The etch rate for this recipe is ~300Å per min. As this etching is anisotropic, there is less lateral etching, and near-to-exact pattern is formed. Aluminium sputtering on front and back sides of the wafer: Base pressure: 5.0×10-6 mbar, Ar gas pressure:

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5.0×10−3 mbar, target cleaning 400 W for 1 min., sputter deposition: 400 W for 32 min. Sputtering provides good adhesion and thickness control. Photolithography for aluminium pattern delineation (Mask-4): As with mask-1 above. Aluminium etching from front side: 2-4 min at 50-55ºC in commercial Al etchant. Backside of the wafer was coated with photo resist for protecting aluminium during etching. Aluminium sintering: 450ºC, 30 min., forming gas (10% H2 + 90% N2). Besides improving the metalsemiconductor contact, this also reduces the surface state density at the semiconductor/gate-oxide interface. MOSFET testing: A Keithley 4200-SCS Semiconductor Characterization System was used for measuring the I-V curves of MOSFETs fabricated on the ISFET wafer. This was necessary for process characterization because ISFET devices cannot be tested before packaging. Wafer dicing: The wafer was cut into chips by a dicing saw. 2.2 ISFET Packaging

Conductor lines were made on ceramic substrates by screen printing20,21. The chip was mounted by silver epoxy and cured. Wires were bonded connecting the source and drain pads with conductor lines on ceramic substrate. The wires, contact pads and periphery of the chip were covered with insulating epoxy which was hardened by curing. The epoxy was applied carefully with a dispenser; the viscosity and flow of the epoxy were controlled to prevent its spreading over the gate area. Details are published elsewhere20,21. In some devices, the ISFETs were mounted on PCB strips for cost-effectiveness.

3 Results and Discussion Measurement of thickness of field oxide by Dektak 6M surface profiler: Fig. 6 shows the surface profiler plot of field oxide. The field oxide thickness is 0.872 µm. Surface profiler plots for thickness of gate oxide and nitride layers: The thickness graphs for oxide and nitride films on gate are shown in Figs 7[(a) and (b)], respectively from which it is evident the gate oxide thickness = 532Å and gate nitride thickness = 834Å. Thus, the ISFET has a dual-layer gate dielectric. Current-voltage characteristics of MOSFET test devices on the wafers: Fig. 8 shows the output characteristics of MOSFET test devices fabricated on the ISFET wafer. It is clear that the MOSFET conducts appreciably without applied gate bias

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Fig.6 — Field oxide thickness plot generated by surface profiler, thickness = 0.872 µm

Fig. 8 — Output characteristics of MOSFETs fabricated on the same wafer and by the same process as the ISFET: (a) wafer 1 and (b) wafer 2.

Fig. 7 — Stylus profiler plots for (a) gate oxide thickness (532 Aº) and (b) gate nitride thickne(834 Aº).

indicating that the ISFET is an N-channel, depletionmode (normally ON) device. This is expected in absence of threshold voltage adjustment implant. But depletion-mode, operation does not in any way impair ISFET functioning. It was also possible to operate the MOS transistor in enhancement mode by making the gate positive instead of negative. The positive voltage on the gate attracted more free electrons into the conducing channel, while at the same time repelling holes down into the p-type substrate. The more positive the gate potential, the deeper was the channel and lower was its resistance. Increasing positive bias therefore, increased current flow. IDS-VGS characteristics of packaged ISFETs in buffer solutions and determination of pH sensitivity of the device: A simple method was adopted for determining the pH sensitivity of ISFET, as shown in the circuit diagram of Fig. 9. Suppose, the ISFET is biased at fixed drain-source voltage VDS. Immersing the ISFET in a high pH solution (alkaline), a given gate-source bias VGS is applied through an Ag/AgCl reference electrode, and the drain-source current IDS is


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Fig. 9 — Circuit connection for measuring the pH sensitivity of ISFET

Fig. 10 — pH response characteristics of ISFET in various buffer solutions

measured. If now the ISFET is cleaned and dipped in a lower pH solution (acidic), the drain-source current IDS will increase. But it can be brought back to the original IDS value in preceding pH solution by decreasing VGS. The necessary change in VGS to bring IDS to initial value, i.e., to ensure constant IDS, VDS condition, is the voltage difference accounting for the pH difference between the two solutions. Then the change in VGS, i.e., ∆VGS, divided by the difference in pH values of solutions used gives the pH sensitivity of ISFET. Based on the above principle, drain-source voltage VDS =0.5 V was applied to the ISFET. The substrate terminal was grounded. The ISFET was first immersed in pH=10 buffer solution. Gate-source voltage VGS =0.1 V was applied through Ag/AgCl reference electrode dipped in the same solution. The corresponding drain-source current IDS was noted. The gate-source voltage VGS was successively raised in steps to 0.2, 0.3, 0.4 and 0.5 V, and the resulting IDS values were recorded. A plot of IDS-VGS values was generated from these readings in pH=10 solution (Fig. 10). Then, the sensor was cleaned by rinsing in deionised water and immersed in pH=9 solution. The IDS values for different VGS values were noted, as before. The associated IDS-VGS curve was drawn for pH=9 solution. The same experiment was repeated with pH=7, 5, 4, 3, 2 solutions and the resulting IDS-VGS graphs were plotted. In these experiments, standard buffer solutions from ReAgent/Scharlab/ Oakton (Cole-Parmer) were used. A horizontal straight line intersecting the IDS-VGS plots in solutions of different pH values gives the VGS difference pertaining to a given pH difference, e.g.,

from pH=10 and pH=2, the pH sensitivity was calculated as (500-90) mV/(10-2) pH= 410 mV/8 pH =51.25 mV/pH. Approximately, the same result was obtained by selecting any other pair of pH values, e.g., for pH=4 and pH=7, the sensitivity was found as (305-160) mV/ (7-4) pH =145/3 mV/pH=48.33 mV/pH. The mean sensitivity was calculated as (51.25+48.33)/2 = 49.79~50 mV/pH. Technological Shortcomings and Proposed Remedial Measures: Two shortcomings of the present work must be highlighted, namely, the use of silicon nitride gate dielectric and the cumbersome packaging technique. Silicon nitride was used preferably as membrane material due to its compatibility with MOSFET device fabrication. In comparison to silicon nitride-gate ISFET sensors reported in this paper, which exhibit a sub-Nernstian response (50-55 mV/pH), aluminium oxide and tantalum pentoxide gate ISFETs have a higher pH-sensitivity (58-59 mV/pH) and lower drift22-27 (less than 80 microvolt/hour in pH=7); the same for Si3N4 ISFET is 0.5-1 mV/hour in pH=7. In addition, the Ta2O5 film does not suffer from the surface deterioration caused by hydration of the film. Ito25 studied the long-term drift mechanism of Ta2O5 gate pH-ISFETs; Kwon et al.26 fabricated a Ta2O5 gate pHISFET with high sensitivity (58-59 mV) over a wide pH range (pH 2-12) and low long-term drift (0.03-0.05 pH/day); and Grüger et al27. investigated the effects of heat treatment on Ta2O5 sensing membrane for fabricating low drift and high sensitivity pH-ISFET. Therefore, the more suitable Ta2O5 dielectric must be adopted in order to overcome the limitations of

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Fig. 11 — Proposed Wafer-bonding based ISFET packaging approach

Si3N4. Then, the gate structure of pH-ISFET will be a multilayer structure: Ta2O5/Si3N4/SiO2. This highquality tantalum oxide film is deposited by physical vapour deposition, i.e., R F reactive sputtering using tantalum target in oxygen ambient. The necessity of sputtering arises from the requirement to increase the number of O-sites, which improves the pH-sensitivity of ISFET. From these considerations, in future, technology for fabricating low-drift, high-sensitivity ISFETs will be developed by using reactive sputtering technique for gate dielectric film deposition followed by appropriate thermal annealing to control the film properties for achieving the desired pH response27. Furthermore, in the ISFET packaging method followed in this work, the electrical feed throughs connecting the sensor to the electronic circuits were buried under the epoxy. A drawback of this packaging is that, the process being done manually, is dependent on operator skill and is also time consuming. Further, the epoxy-covered sensor cannot be kept continuously immersed in analyte solution for long periods of time due to adsorption of water by the bulk epoxy as well as at the interface between silicon nitride and epoxy, resulting in leakage problems and device failure. A proposed alternative packaging solution involves the eutectic bonding of a silicon wafer on the processed ISFET wafer before dicing using aligned wafer bonding. This wafer has holes situated in alignment with the sensing gate area and contact pads for wire bonding. After wire bonding, the gate area will remain exposed to the analyte within an enclosed cavity while a stainless steel cap will be fixed to cover the wire bonds (Fig. 11). Thus, epoxy-free encapsulation will be achieved. Another packaging scheme being tried is backside-contacted ISFET technology using the MEMS techniques based on bulk micromachining of silicon28-32. Packaging of the ISFET structure with contact pads located on the passive backside of the structure will considerably

facilitate its protection against chemically aggressive environment. Incorporation of new packaging approaches, as outlined above, combined with Ta2O5 gate dielectric, and optimising the semiconductor processing, will result in a high-sensitivity, rugged ISFET sensor with performance up to the glass electrode benchmark.

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