IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 4, APRIL 2010
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Fast All-Transparent Integrated Circuits Based on Indium Gallium Zinc Oxide Thin-Film Transistors Arun Suresh, Patrick Wellenius, Vinay Baliga, Haojun Luo, Leda M. Lunardi, and John F. Muth
Abstract—We describe the fabrication and characterization of visible transparent small-scale indium gallium zinc oxide (IGZO) integrated circuits. The IGZO channel and indium tin oxide (ITO) contacts and interconnects were pulsed laser deposited at room temperature. Low-temperature (200 ◦ C) atomic-layer-deposited Al2 O3 was used as the gate dielectric in bottom-gated thin-film transistors with field-effect mobility near 15 cm2 /V · s. Logic inverters and ring oscillators were fabricated and characterized, with operations at frequencies as high as 2.1 MHz, corresponding to a propagation delay of less than 48 ns/stage with a supply voltage of 25 V. To the best of our knowledge, these are the fastest all-transparent oxide semiconductor circuits reported to date. Index Terms—Indium gallium zinc oxide (IGZO), oxide semiconductors, ring oscillators (ROs), thin-film transistors (TFTs), transparent circuits.
I. I NTRODUCTION
I
N 1996, Hosono et al. [1] reported on a new class of inorganic oxides, amorphous oxide semiconductors (AOS), based on multicomponent combinations of heavy-metal cations with an outer shell electron configuration of (n − 1)d10 ns0 (n > 4). Apart from transparency in the visible spectrum, the most attractive characteristic of these oxides is their relatively high electron mobility in the amorphous state. AOS-based thin-film transistors (TFTs) exhibit several advantages, most notably the high current density stemming from relatively high mobilities of 10–40 cm2 /V · s, making them well suited for active-matrix backplanes in current-driven OLED displays. In addition, the amorphous nature and low processing temperature make AOS devices compatible with flexible substrates, potentially enabling flexible transparent display technologies [2]. The transparency of these devices would allow significantly higher pixel fill factors, reducing the overall power consumption of a display by simultaneously reducing current densities and operating voltages. Transparent display elements with transparent driving circuits are also expected to usher in numerous applications [3]. Although there has
Manuscript received December 15, 2009. First published February 22, 2010; current version published March 24, 2010. The review of this letter was arranged by Editor A. Nathan. A. Suresh is with Intel Corporation, Hillsboro, OR 97124 USA (e-mail:
[email protected]). P. Wellenius, V. Baliga, H. Luo, L. M. Lunardi, and J. F. Muth are with the Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695 USA (e-mail:
[email protected];
[email protected];
[email protected];
[email protected]; muth@ ncsu.edu). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2010.2041525
been substantial interest in developing oxide semiconductors for device applications, the literature has primarily focused on discrete devices [4], [5]. Evaluating the dynamic performance and the ability to fabricate integrated circuits using AOS TFTs is an important step for circuit and display applications. Here, we investigate visible transparent circuits based on room-temperature pulsed-laser-deposited (PLD) indium gallium zinc oxide (IGZO) bottom-gated TFTs on transparent glass substrates. The literature reports on integrated circuits based on transparent oxide semiconductor TFTs [6]–[8] with varying results. Five-stage AOS-based ring oscillator (RO) circuits have been previously demonstrated up to 410 kHz [8], although polycrystalline ZnO has been used in seven-stage oscillators up to 2.3 MHz [7]. Recent literature describes ZnObased ROs with delays of less than 10 ns/stage [9] as well as discrete ZnO TFTs exhibiting gain up to ∼7 GHz [10]. However, these reported circuits have made use of metallic contact layers and interconnects. In order to further the development of IGZO-based technology for display applications, fully visibletransparent circuits are desired. To the best of our knowledge, we report here the fastest all-visible-transparent TFT circuits to date. II. E XPERIMENTAL A plan-view optical micrograph of a fabricated seven-stage RO is shown in Fig. 1(a). Glass substrates coated with ∼ 60 nm of sputtered indium tin oxide (ITO) were patterned by photolithography, followed by dry etching to form the gate electrodes. The deposition of the gate dielectric, 120-nm-thick Al2 O3 , was performed by atomic layer deposition (ALD) at 200 ◦ C from the trimethyl aluminum precursor and water. Contact holes to the gate electrode were opened by photolithography and dry etching. Utilizing liftoff photolithography processes, the 40-nm-thick IGZO channel, as well as the 200-nm-thick ITO contact and interconnect layers, was room temperature deposited by PLD in oxygen ambient to complete the circuits. A cross section of a single TFT is shown in Fig. 1(c). These circuits where characterized as-grown. No annealing steps were used during or after fabrication of the circuits. Passivation layers were not included in this circuit design as we have not observed substantial device degradation due to exposure to atmosphere. This is likely due to the use of a bottom-gated design, where the conductive channel forms near an interface not exposed to atmosphere. A more common form of degradation among IGZO TFTs is that due to charge trapped at the dielectric/channel interface. Use of an ALD
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IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 4, APRIL 2010
Fig. 1. Plan-view photograph of a seven-stage IGZO ring oscillator as fabricated (LDrive = 10 μm, WDrive = 200 μm, LLoad = 10 μm, WLoad = 40 μm, beta ratio = 5, and 2.5-μm source-/drain-gate overlap). (b) Glass substrate containing several ring oscillators, inverters, and discrete transistors. Note the highly transparent nature of the circuits where the label below is clearly visible. (c) Illustration of single TFT device cross-section.
√ Fig. 2. IGZO TFT log(IDS )−VGS , log(IG )−VGS , and IDS versus VGS characteristics for VDS = 20 V. (W/L = 100 μm/20 μm and Cdi ∼ 60 nF · cm−2 ). (b) DC transfer curve for a transparent IGZO inverter measured under a supply voltage of VDD = 20 V. The beta ratio = 10 (LDrive = 20 μm, WDrive = 400 μm, LLoad = 20 μm, and WLoad = 40 μm), and the source-/ drain-gate overlap is 2.5 μm.
Al2 O3 dielectric here has greatly reduced the threshold voltage shift associated with interface-trapped charge in these devices as compared to previous devices, utilizing an ATO or SiNx dielectric [11], [12]. Changes in performance of these circuits were not readily observed during testing, although long-term circuit performance was not extensively evaluated. An image of the processed chip with several ROs, inverters, and discrete transistors is shown in Fig. 1(b). Owing to the high transparency of the films, the circuits are difficult to discern on the substrate. The RO consists of an odd number of NMOS inverter stages connected in series where each inverter stage comprises a load and a drive transistor with identical channel lengths but different channel widths. Device dimensions such as length, source-/drain-gate overlap, and beta ratio βR = [(W/L)Drive /(W/L)Load ] were varied to investigate their effect on circuit performance. The voltage supplied to the gates of the load (VG ) was always set to the same values as the drain (VDD ). Without output buffer, the signal was extracted directly from the last inverter (stage) using an EG&G PARC Model 181 current preamplifier. III. R ESULTS AND D ISCUSSION The dc transistor characteristics of a typical 10 μm × 100 μm (L × W √) IGZO TFT were extracted from log(ID ) versus VGS and IDS versus VGS curves as shown in Fig. 2(a). At VDS = 20 V, a saturation field effect mobility μsat of 15 cm2 /V · s, a threshold voltage of 3.5 V, a subthreshold slope less than 130 mV/decade, and a current on/off ratio larger than 108 were measured. The maximum OFF-state current was
Fig. 3. (a) Output waveform of a five-stage ring oscillator (LDrive = 20 μm, WDrive = 400 μm, LLoad = 20 μm, WLoad = 80 μm, beta ratio = 5, and 2.5-μm source-/drain-gate overlap) operating at 645 kHz (propagation delay of 155 ns/stage) with a supply voltage of VDD = 25 V. (b) Oscillation frequency and propagation delay as a function of VDD for (solid) measured and (hollow) SPICE simulation results.
less than 1 pA, mainly due to the gate leakage current. The transfer characteristics of IGZO TFTs indicate an enhancement mode device, which allows realization of simple circuits without the necessity of level shifting. Hoffman explains the VGS -dependent mobility observed in TFTs [13], and a similar behavior has been observed in IGZO TFTs [14] due to the nonlocalized states in the bulk of the semiconductor and/or interfacial trap states. A typical voltage-transfer function of an IGZO inverter with a 20 μm × 400 μm drive TFT and a 20 μm × 40 μm load TFT at a supply voltage of VD = 20 V is shown in Fig. 2(b). At the inversion voltage, a gain of 2.3√was extracted, which is smaller than the theoretical value of βR = 3.33. This can be explained by the imbalance in the channel conductance due to the VGS -dependent μsat between the drive and the load TFTs in the inverter at the inversion voltage. Good logic level conversion is observed from the inverter transfer function. The output waveform of a five-stage IGZO RO without any level shifter circuitry or an output buffer for 20-μm devices and a source-/drain-gate overlap of 2.5 μm is shown in Fig. 3(a). The widths of the drive and load transistors were 400 and 80 μm, respectively, giving a beta ratio of 5. The oscillation frequency and propagation delay per stage as a function of supply voltage VDD are shown in Fig. 3(b). For VDD = 25 V, the circuit operated at a frequency of 645 kHz, corresponding to a propagation delay of 155 ns/stage. It is worth mentioning that the ROs are observed to oscillate at a supply voltage as low as 5 V as a result of low threshold voltage and small subthreshold slope of the transistors. A comparison between simulation and
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tion delay less than 48 ns/stage (corresponding to 2.1-MHz oscillation frequency) at a supply voltage of 25 V. To the best of our knowledge, these are the fastest all-visible-transparent oxide semiconductor circuits reported to date. R EFERENCES
Fig. 4. (a) Propagation delay per stage as a function of supply bias, channel length (10 and 20 μm), and number of stages (five- and seven-stage) of an IGZO ring oscillator (LDrive /WDrive = 20 μm, LLoad /WLoad = 4 μm, beta ratio = 5, and 2.5-μm source-/drain-gate overlap). (b) Output waveform of a five-stage ring oscillator with a channel length of 10 μm.
experimental results for the same five-stage RO circuit is also shown in Fig. 3(b). AIMSPICE was used to fit the measured dc characteristics of IGZO TFTs and subsequently simulate inverter and RO circuits. A good agreement between the measured and simulated results indicates that, to first order, the parameters used to model the TFT dc characteristics describe well the dynamic characteristics of IGZO TFTs. TFT device geometry plays an important role in determining RO operation, so the effects of the TFT channel length, source-/drain-gate overlap, and beta ratio were also studied. As expected, the oscillation frequency increased, and the propagation delay decreased for circuits with shorter channel lengths, smaller overlap capacitance, and lower beta ratios. Fig. 4(a) compares the five- and seven-stage ROs with 10- and 20-μm channel lengths. The propagation delays are virtually identical for the 10-μm channel length RO, particularly at higher supply voltages. The output waveform of the five-stage RO with 10-μm TFTs is shown in Fig. 4(b). The circuit operated at a frequency of 2.1 MHz at a supply voltage of 25 V, corresponding to a propagation delay less than 48 ns/stage. IV. C ONCLUSION IGZO TFTs with measured field effect mobility ∼ 15 cm2 / V · s were fabricated and employed in fast optically transparent circuits, including ROs on glass substrates. The IGZO channel was room temperature deposited onto substrates by PLD. The TFT gates were isolated using an Al2 O3 gate dielectric deposited by ALD at a low temperature of 200 ◦ C. The fastest measured performance was for a five-stage RO with propaga-
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