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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Fault-Tolerant Voltage Source Inverter for Permanent Magnet Drives Rammohan Rao Errabelli and Peter Mutschler, Member, IEEE

Abstract—In this paper, a two-level fault-tolerant voltage source inverter (VSI) for permanent magnet drives is systematically designed and tested. A standard two-level inverter consists of three legs. In this case of fault-tolerant inverter, a redundant leg is added that replaces the faulted leg. Faulted leg isolation and redundant leg insertion are done by using independent back-to-back-connected thyristors. The proposed inverter provides tolerance to both shortcircuit and open-circuit faults of the switching devices. The postfault performance is the same as the normal prefault operation and fault compensation is fast enough such that there is negligible disturbance in the drive operation. The fault tolerance of the inverter is verified using field-oriented control of a permanent magnet synchronous motor. Index Terms—Fault tolerance, permanent magnet synchronous machine (PMSM), reliability, voltage source inverter (VSI).

I. INTRODUCTION YPICALLY, a modern industrial drive consists of a power electronic converter, a digital controller for implementing the control algorithms, feedback sensors, and a motor. Several faults can affect the motor drive and a fault in any of the aforementioned will stop the drive running or at least it affects the drive performance [1]. There are some critical applications such as power plants, aerospace, railway locomotives, automobiles, chemical plants, etc., where the fault tolerance of the drive is very important. For an interlinked production process, as in modern industrial processing plants, a fault in a single drive can result in tremendous damages of materials and machines. Follow-up costs due to faults with drives in modern production plants can amount to huge sums. So the fault tolerance of adjustable speed drives is the area of great interest for modern drive solutions. So far, redundant or conservative design has been used in every application, where the continuity of operation is a key feature. Nevertheless, some applications accept short-torque transients and even permanently reduced drive performance after a fault, under the condition that drive continues to run. A survey was done by Thorsen and Dalva on the reliability of voltage source inverter (VSI) for industrial drives [2]. According

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Manuscript received September 16, 2010; revised January 17, 2011 and February 22, 2011; accepted March 18, 2011. Date of current version January 9, 2012. This work was supported by the Deutsche Forschungsgemeinschaft DFG under Grant MU 1109/17-1, “Fehlertolerante Antriebsumrichter und deren Regelung.” Recommended for publication by Associate Editor A. A. Consoli. The authors are with Institute for Power Electronics and Control of Drives, Technische Universit¨at Darmstadt, 64283 Darmstadt, Germany (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2011.2135866

to the results of their survey, 50% of all failures are in the control circuits, 7.7% in the cooling fans, and 37.9% are in the power circuits. So faults in the power circuit share a large proportion of the total converter set and large percentage of the inverter faults are switch short-circuit faults. However, according to Schwab et al. power switches pose more failure rates than any other component in the inverter [3]. They evaluated the reliability of a permanent magnet synchronous machine (PMSM) drive for automotive applications. Their results show that the failures of the power transistors represent approximately, according to the RDF2000 [4], 63% of the electronic parts failures for a three-single-phase inverter topology and 50% for a three-phase full-bridge topology. For the failures in the field, this quotient becomes 56% and 40%, respectively. The difference in the results can be attributed to application specific and insufficient field data available from the customers. Several fault-tolerant topologies are available in the literature [5]; some of them reconfigure the standard inverter topology and reformulate the current references so that the rotating MMF generated by the armature currents do not change, even if one phase is open circuited after fault occurrence. For proper operation with some topology, the neutral point of the motor or faulted leg has to be connected to the midpoint of the dc voltage link, created using the use of two capacitors [6]. In this type of control, the inverter should be over-rated so as to produce the rated torque output. A valid alternative that does not require the availability of the dc link midpoint is proposed in [7], at the cost of using additional components. Though it needs additional components, it gives 100% output at postfault operation, without overloading the inverter. However, this topology uses auxiliary capacitors and fast-acting semiconductor fuses to isolate the faulted leg. The rating and the size of the capacitors increase with the rating of the inverter. The presence of fuses increases the cost of the inverter and also dc bus parasitic inductance. A simplified version of [7] has been developed in [8], where only fast-acting semiconductor fuses are used to isolate the fault leg. In the case of an IGBT short, complementary IGBT is turned ON in order to blow the fuses connected in series with leg. But these fuses should have low i2 t rating compared to the IGBTs and such fuses are very expensive. In this case also, the inverter should be over-rated in order to avoid blowing the fuses for any over current and also as said earlier they add parasitic inductance in the dc bus. In some cases, it is also possible that only one of the fuses is blown and the faulted IGBT is still connected to the phase of the machine. An alternative fault-tolerant motor drive configuration is developed in [9], where fault tolerance is achieved by separating all the phases of the motor and driving each phase of the machine with an independent

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ERRABELLI AND MUTSCHLER: FAULT-TOLERANT VOLTAGE SOURCE INVERTER FOR PERMANENT MAGNET DRIVES

single-phase converter. In case of a fault in converter or machine, the remaining motor can continue to operate. Reduction of torque in case of a fault in one phase of the drive can be compensated by over-rating the remaining healthy phases. A modular parallel redundant system has been proposed in [10], where two complete setup of drive systems are arranged on a common shaft and all the motor phases are driven by independent singlephase inverters. A fault in any set of the drive reduces the output power to 50%. A fault-tolerant inverter topology similar to [7] has been proposed in [11] but using the back–to-back-connected IGBTs for isolating the faulted leg. These IGBTs increase the cost of the inverter and also losses in the inverter are increased due to on-state resistance of the isolating devices. The redundant leg of this topology is connected to the neutral point of the motor, which means that this topology necessitates the availability of the neutral point in the machine, and also it cannot provide full-rated output unless the inverter is over-rated. The postfault control scheme is not the same as the prefault control scheme and is based on two-phase motor control. A topology similar to [7] is proposed in [12]. Electromechanical relays are used to isolate the faulted leg and connect the redundant leg. Postfault performance of this inverter is the same as prefault but electromechanical relays have considerable amount of delay in opening or closing and by this time motor may come to stop or in some cases may rotate in the reverse direction. This paper proposes some relevant modifications to the existing topologies such that there is no compromise between the cost and performance of the inverter. Back-to-back-connected thyristors are used in place of electromechanical relays used in [12]. Adequate control measures are taken to bring the machine postfault current to zero in the case of IGBT short circuit. Experimental results are presented for both the cases of IGBT short-circuit and open-circuit fault. This paper is organized as follows. In Section II, the system description of inverter topology and its control is presented. In Section III, experimental results in the case of IGBT open-circuit fault, for an uncompensated case, which is a standard inverter without fault tolerance and compensated cases where the fault-tolerant inverter is used, are presented. In Section IV, experimental results in the case of IGBT short-circuit fault, for both standard inverter and faulttolerant inverter cases are presented. In Section V, conclusion of this paper is given.

II. SYSTEM DESCRIPTION OF THE FAULT-TOLERANT INVERTER Fig. 1 shows the proposed fault-tolerant two-level VSI. A standard two-level three-phase inverter consists of only three legs but the fault-tolerant inverter of this topology consists of four legs, with one leg as redundant. The redundant leg is normally not used when the standard three legs are working without any fault. Back-to-back-connected thyristors (ISa , ISb , and ISc ) are connected between output terminals of the inverter (Va , Vb , and Vc ) and corresponding motor phases. These thyristors are used as isolating switches of faulted leg. Additional three thyristors (THa , THb , and THc ) are connected between the output terminal of redundant leg (Vr ) and motor phases as shown

Fig. 1.

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Proposed fault-tolerant VSI topology.

in Fig. 1. These thyristors are used for inserting the redundant leg in the place of faulted phase. The rating of the thyristors is the same as that of the IGBTs. During the normal operation, isolating thyristors (ISa , ISb , and ISc ) are always turned ON, which may cause undesired conduction losses. Usually, thyristors have very less on-state voltage drop compared to IGBTs so the reduction in efficiency is not significant when compared the total losses of the inverter. For example, when considered of the almost equal rating of the IGBT (SK40GB123) and thyristor (SK25UT), on-state voltage drop of the IGBT, VCE(sat) = 3 V max (at Tj = 25◦ , ICnom = 30 A) and for thyristor VT = 1. 9 V max (at Tj = 25◦ and Inom = 30 A). As reported in [1], different faults that can affect the drive’s operation are as follows: 1) single-IGBT open-circuit fault, 2) phase-leg open-circuit fault, 3) single-IGBT short-circuit fault, 4) phase-leg short-circuit fault. As usual, simultaneous faults in different legs are not considered here. The aforementioned topology can be used for tolerance of all the aforementioned faults except the last one, as this would be an unlikely simultaneous fault in two switches. If necessary, inserting a fast-acting semiconductor fuse in series with each leg is sufficient to address the phase-leg short-circuit fault [12]. The remaining fault compensation procedure is explained later. A. Inverter Operation and Fault Compensation for the Single-IGBT Open-Circuit Fault An open-circuit fault in the IGBT may be due to the fault in the gate drive or the break of bond wires in the IGBT. Fig. 2

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Fig. 2.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Three-phase two-level inverter in the case of the IGBT Sa p open fault.

shows the standard three-phase two-level VSI with an open switch fault (Sap open) controlling an ac machine. When one of the IGBT does not turn ON, in the case of motor operation, current in that phase is zero for a half-cycle, either positive or negative half-cycle depending on whether it is upper IGBT or lower IGBT. For example, in this case, IGBT “Sap ” is having a switch open fault. When the current is in the positive half-cycle, the phase “a” current is always zero. As a consequence of this, a dc current offset is caused in the faulty phase and this offset is equally divided between the healthy phases. Moreover, the current dc component generates unequal current stress in the upper and lower transistors in the inverter, which may cause thermal defects in the transistors [1]. Different methods for detecting the open-circuit fault of the IGBT are available in the literature [13]–[16]. Some methods are based on the using voltage sensors [14] and some are based on software techniques without using any additional hardware [15], [16]. According to [14], the open-circuit fault of the IGBT can be detected by inserting voltage sensors at desired locations. Depending on the location of the voltage sensor inserted, the fault detection techniques can be classified as follows: 1) inverter pole voltage measurement, 2) machine phase voltage measurement, 3) system line voltage measurement, 4) machine neutral voltage measurement. Though these methods have short fault-detection time, they need extra voltage sensors for fault detection. To overcome the aforementioned problem, in some papers, software-based techniques have been suggested. Peuget et al. [15] suggested the open switch fault detection by analyzing the current vector trajectory and of the instantaneous frequency in the faulty mode. With this method, it is easy to detect the fault, but it causes time delay for the fault detection while it needs to save the current vector trajectory of one cycle. As this method needs to save current vector trajectory of one cycle, a lot of memory is needed in the digital controller, and, especially, this is worse when the machine is working at low speed. Jung et al. [16] proposed a different method for detecting an open switch fault based on comparing the estimated terminal voltage of the inverter and reference terminal voltage of the inverter. In the case of open switch fault, there is a considerable difference between these two. This method of fault detection is fast but terminal voltage is estimated using machine parameters. So any variation in the parameters should not affect the fault detection. In this paper, no special fault detection method is adopted. In order to test the

Fig. 3.

Three-phase two-level inverter in the case of the IGBT Sa p short fault.

inverter performance, a worst case is assumed where it takes at least one current cycle to detect the fault. As soon as the open-circuit fault in any IGBT is detected, gate signal to the corresponding leg and isolating thyristors (ISa , ISb , or ISc ) are blocked. The gate signals of the faulty leg are transferred to the redundant leg and its corresponding thyristors (THa , THb , or THc ) are turned ON. The same procedure can also be applied in the case of the phase-leg open-circuit fault. B. Inverter Operation and Fault Compensation for the Single-IGBT Short-Circuit Fault For a fault-tolerant drive, it is essential to isolate the faulted phase as fast as possible and to activate the redundant leg (see Fig. 1) in order to resume normal operation. A short-circuit fault in the IGBT may be due to the malfunctioning of the gate drive or permanent damage in the IGBT. Fig. 3 shows the standard VSI with an IGBT short-circuit fault (Sap shorted). A standard Vce desaturation-based fault detection is used for the IGBT short-circuit fault detection [17]. As soon as the IGBT short-circuit fault is detected, all the IGBTs are turned OFF by hardware protection. Now for the case of IGBT permanent damage, corresponding phase is permanently connected to the dc link positive bus or negative bus depending on upper IGBT or lower IGBT is damaged. As long as the machine is running, current flows through the shorted IGBT and remaining free wheeling diodes of the inverter. Fig. 3 shows the standard VSI after the upper IGBT (Sap ) is short circuited and hardware protection turns OFF all the other IGBTs. Depending on the instance of fault in a current cycle, fault current in that corresponding phase may take a lot of time to reach zero crossing in order to isolate the faulted phase leg. Depending on the parameters of drive, load, and operating point, sometimes this short-circuit current could be unidirectional [18]. But for disturbance-free operation or for negligible disturbance of drive operation, the isolation of the faulted phase should be fast. In order to achieve the aforementioned requirement, a turn-OFF command is also issued to all the isolating thyristors (ISa , ISb , and ISc ), which facilitates in bringing the short-circuit current to zero. In what follows, the provided theoretical analysis shows that by giving a turn-OFF signal to all the isolating thyristors, current in the faulted phase reaches zero crossing. With the short-circuit fault on the IGBT Sap , phase “a” is permanently connected to dc link positive bus. If current is in the negative half-cycle when the fault occurred, as the phase is permanently connected to the positive dc bus after the fault, current tend to

ERRABELLI AND MUTSCHLER: FAULT-TOLERANT VOLTAGE SOURCE INVERTER FOR PERMANENT MAGNET DRIVES

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Fig. 4. Machine currents in the normal condition with positive half-cycle of current ia is divided into three sections.

increase in the positive direction with certainly having a zero crossing. So it is enough to consider only the positive half-cycle for the analysis. Fig. 4 shows the machine currents under a healthy condition. The positive half-cycle of phase current ia is divided into three sections, where the border of the sections is defined by the zero crossing of machine’s phase current. The analysis for the section three (sec3) is presented here as it is worst case of the results presented. For the remaining two sections, the same approach is valid. Fig. 5(a) shows the simplified PMSM and the current paths of the inverter after IGBT Sap short-circuit fault and turn OFF of all healthy IGBTs. The back EMFs of the machine are ea , eb , and ec and the phase inductance of the PMSM is L; the stator resistance is neglected in this analysis. For a nonsalient PMSM, the d-axis current in the pre fault state is controlled to be zero and consequently all current is in the q-axis. Therefore, the stator current is assumed to be in phase with the back EMF when the fault occurs. An analysis for arbitrary phase angles is possible too, but needs several pages. When the Sap short-circuit fault occurs in sec3, initially, ia and ib are positive, and ic is negative. After turning OFF all healthy IGBTs by hardware protection, the remaining current paths are shown in Fig. 5(a). For a symmetrical machine, we get L·

2Vdc dib = −eb − . dt 3

(1)

The slope of ib is strongly negative and ib will reach zero fast. As the gate signals for thyristor “ISb ” are blocked, the current remains at zero. After this, the current path shown in Fig. 5(b) exists and the equation is 2·L·

dia = ec − ea . dt

(2)

In Sec3, ea is positive and ec is negative so the slope of ia is negative, which brings ia to zero, i.e., all currents are zero. But for high current at low speed (standstill) with low or zero EMFs,

Fig. 5.

Postfault inverter topology in the case of the IGBT Sa p short fault.

the time to reach zero current will be long until the energy stored in the inductances of the machine is dissipated. Usually, thyristors will have turn-OFF time of around 80 to 150 μs. In order to turn OFF the thyristor, the load current must be reduced below its holding current for sufficient time to allow all the mobile charge carriers to vacate the junction. After the short-circuit current has reached zero, to make sure that isolating thyristors are fully turned OFF and can withstand forward voltage, some time delay (around 500 μs) is provided before the new leg is inserted and the reset command is issued to hardware protection. After the time delay, gate signals to the faulted leg are disabled and redirected to the redundant leg by the controller. At the same time, the corresponding thyristor (THa , THb , or THc ) is also turned ON. Gate signals to remaining legs are also enabled. As soon as the IGBT short-circuit fault is detected, all the integrators in the controller are stopped from further integrating and they are enabled only after fault compensation is completed. III. EXPERIMENTAL RESULTS FOR THE IGBT OPEN-CIRCUIT FAULT A laboratory prototype has been built for testing the faulttolerant inverter driving a field-oriented controlled PMSM. The PMSM is coupled with another PMSM, which is used as a load machine. A three-phase variable resistance is connected at the output terminals of the load machine which provides the required load torque. The control algorithm is implemented in a Texas Instruments based F2812 fixed-point digital signal processor (DSP) evaluation board. A fault-tolerant controller was presented in [19], but this is not the subject of this paper. Generation of command signals for the converter, data acquisition, fault insertion, and fault compensation is done through software written in “C” language. All necessary variables are stored in

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TABLE I PMSM PARAMETERS

Fig. 7. q-axis current and speed response to an uncompensated IGBT Sa p open fault.

Fig. 6.

Current response to an uncompensated IGBT Sa p open fault.

the external memory of the DSP during control implementation and are later plotted using MATLAB. IGBTs are used as main switching devices and thyristors are used for isolating the fault leg. Results are produced for both the uncompensated fault and the compensated fault case. The uncompensated fault case explains the behavior of the standard two-level inverter after the fault and the compensated case is the fault-tolerant inverter’s response to different faults. PMSM parameters are presented in Table I and a picture of the experimental setup is included in the appendix. A. Uncompensated IGBT Open-Circuit Fault An open-circuit fault is created by turning one of the IGBT gate signals permanently OFF. As explained earlier no separate fault detection method is used. A worst case of fault detecting time is assumed in order to verify the inverter performance. Figs. 6 and 7 show the current, torque producing q-axis current, and speed response of the PMSM to an open-circuit fault in the upper IGBT of phase leg “Va ”. A case of upper IGBT opencircuit fault in phase leg “Va ” is shown in Fig. 2. In the case of upper IGBT (Sap ) open-circuit fault, the positive half of the corresponding phase current is zero. In the case of IGBT opencircuit fault, the machine continues to rotate with oscillations

Fig. 8.

Current response to a compensated IGBT Sa p open fault.

as a consequence of the huge oscillations in the q-axis current, which can be observed in Fig. 7.

B. Compensated IGBT Open-Circuit Fault Figs. 8 and 9 show the current, torque producing the q-axis current, and speed response of the PMSM to a compensated IGBT open-circuit fault in upper IGBT (Sap ) of the leg “Va ”. Toc is the point in time where the fault is inserted and after one fundamental cycle of current, the gate signals to complementary IGBT is stopped and also the corresponding isolating thyristors. The gate signals of the faulted leg are transferred to the redundant leg and corresponding redundant leg inserting thyristors are turned ON. From the speed response of the machine, it can be observed that, in the worst case, there is little disturbance in the machine speed and after that machine continues to run the same as the prefault situation. The disturbance during the fault can be further reduced if the fault detection is fast, which is possible with methods explained earlier.

ERRABELLI AND MUTSCHLER: FAULT-TOLERANT VOLTAGE SOURCE INVERTER FOR PERMANENT MAGNET DRIVES

Fig. 9. fault.

q-axis current and speed response to a compensated IGBT Sa p open

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Fig. 12. Current response to an uncompensated IGBT Sa p short fault when the current is at −1.5 A with negative slope.

Fig. 13. q-axis current and speed response to an uncompensated IGBT Sa p short fault when the current is at −1.5 A with negative slope. Fig. 10. Current response to an uncompensated IGBT Sa p short fault when the current is at +1.5 A with negative slope.

IV. EXPERIMENTAL RESULTS FOR THE IGBT SHORT-CIRCUIT FAULT Short-circuit faults are inserted by the DSP by turning the gate signal permanently ON. Special individual drivers are used for short-circuit insertion. These drivers will not block their gate signals even in the case of short circuit but indicate the fault status. A. Uncompensated Upper IGBT Short Fault

Fig. 11. q-axis current and speed response to an uncompensated IGBT Sa p short fault when the current is at +1.5 A with negative slope.

Figs. 10–17 shows the PMSM response to an upper IGBT fault of the leg “Va ” in the case of the standard inverter. As soon as the short-circuit fault in one of the IGBTs is detected, hardware protection disables the gate signals to all the remaining IGBTs. The machine’s response depends on the current at the instant of failure, machine parameters, and load. In order to analyze the machine response, the short-circuit fault is created at four instances of a fundamental current cycle. Two are in the positive half-cycle and two are in the negative half-cycle with current having positive and negative slopes. Tsc is the point in time, where the short circuit occurred at the upper IGBT of phase leg Va . As the phase Va is always

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Fig. 14. Current response to an uncompensated IGBT Sa p short fault when the current is at −1.5 A with positive slope.

Fig. 15. q-axis current and speed response to an uncompensated IGBT Sa p short fault when the current is at −1.5 A with positive slope.

connected to positive dc bus, phase current ia increases in the positive direction until it is compensated by the back EMF of the machine. The results are presented for the four cases. Case 1 is when the current is at +1.5 A with negative slope; case 2 is when the current is at −1.5 A with negative slope; case 3 is when the current is at −1.5 A with positive slope; and case 4 is the when the current is at +1.5 A with positive slope. From the results of case 1, it can be observed that current takes at least one fundamental cycle of current to reach the zero crossing. For this case, it can be observed that at the time when current reaches its first zero crossing, speed almost fell down to one-third of its reference value, which is 2000 r/min. In all the other cases, the zero crossing of the current is early compared to the first case.

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Fig. 16. Current response to an uncompensated IGBT Sa p short fault when the current is at +1.5 A with positive slope.

Fig. 17. q-axis current and speed response to an uncompensated IGBT Sa p short fault when the current is at +1.5 A with positive slope.

Fig. 18. Current response to a compensated IGBT Sa p short fault when the current is at +1.5 A with negative slope.

B. Compensated Upper IGBT Short Fault As soon as the short circuit is detected in one of the IGBTs, hardware protection disables the gate signals to all IGBTs and to all isolating thyristors. The fault is further reported to the controller. The controller monitors the phase currents of the machine and as soon as all the currents become zero, it provides further a delay of around 500 μs to make sure that the fault

leg isolating thyristor is turned OFF and can withstand forward voltage. After this, the new leg is inserted and gate signals of the faulted leg are transferred to the new leg. Figs. 18–22 shows the machine response to compensated short-circuit fault. The short-circuit fault is created at the same four instances as in the uncompensated case in order to show that thyristors

ERRABELLI AND MUTSCHLER: FAULT-TOLERANT VOLTAGE SOURCE INVERTER FOR PERMANENT MAGNET DRIVES

Fig. 19. q-axis current and speed response to a compensated IGBT Sa p short fault when the current is at +1.5 A with negative slope.

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Fig. 22. Current response to a compensated IGBT Sa p short fault when the current is at +1.5 A with positive slope.

V. CONCLUSION This paper has presented a fault-tolerant VSI that can compensate both short-circuit and open-circuit faults in the switching devices. It is simple in construction, modular, and easy to control. Experimental results show that the compensation strategy is fast enough such that there is negligible disturbance in the drive operation. Results show that thyristors can successfully isolate the faulted leg in all the fault cases. The postfault performance of the machine is the same as the prefault, and the postfault control algorithm is the same as prefault. The achieved results show that this inverter can fit in much safety critical and industrial applications where fault tolerance is of prime importance. Fig. 20. Current response to a compensated IGBT Sa p short fault when the current is at −1.5 A with negative slope.

APPENDIX

Fig. 21. Current response to a compensated IGBT Sa p short fault when the current is at −1.5 A with positive slope. Fig. 23.

can successfully isolate the faulted leg. The q-axis current and speed response is presented only for case 1 as the response to all the remaining cases is almost similar. From all the responses mentioned in what follows, it is clear that fault compensation is fast and there is negligible disturbance in the machine response.

Fault-tolerant VSI.

REFERENCES [1] D. Kastha and B. K. Bose, “Investigation of fault modes of voltage fed inverter system for induction motor drive,” IEEE Trans. Ind. Appl., vol. 30, no. 4, pp. 1028–1038, Jul./Aug. 1994.

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Rammohan Rao Errabelli was born in Warangal, India, in 1979. He received the B.Tech. degree from Jawaharlal Nehru Technological University, Ananthapur, India, and the M.Tech. degree from the Indian Institute of Technology Kanpur (IITK), Kanpur, India, both in electrical engineering, in 2003 and 2005, respectively. Since 2007, he has been working toward the Ph.D. degree in the Department of Power Electronics and Control of Drives, Technische Universit¨ate Darmstadt, Darmstadt, Germany. From 2005 to 2006, he was a Research Associate in the Department of Power Electronics, Indian Institute of Science (IISc), Bangalore, India. His research interests include fault-tolerant drives, renewable energy sources, and hybrid electric vehicles.

Peter Mutschler (M’88) was born in 1944. He received the degree of Diplom-Engineer and the Ph.D. degree in 1969 and 1975, respectively, from the Darmstadt University of Technology, Darmstadt, Germany. In 1975, he switched to Brown, Boveri, later Asea Brown Boveri Company, Mannheim, Germany, where he was in the R&D department. He developed microprocessor-based control and protection equipment for a large variety of applications, including HVDC, converter-fed drives for railways and trams, motor control and battery management for electric cars, and OEM converters for general industrial applications. In 1988, he became a University Professor and took over the chair of power electronics and drives at Darmstadt University of Technology. His research activities include control methods for linear drives, for servo drives, soft switching, and matrix converters as well as communication systems for drives. Dr. Mutschler is a member of VDE-ETG (Power Electronics Committee).