Forecasting of Advanced Electronic Packaging ... - IEEE Xplore

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PhD Students. Engineering and Technology Management Department. PSU. USA. ** Master Student. Engineering and Technology Management Department.

Forecasting of Advanced Electronic Packaging Technologies Using Bibliometric Analysis and Fisher-Pry Diffusion Model

Nasir Sheikh* Fredy A Gomez* Yonghee Cho* Jayanth Siddappa** * PhD Students. Engineering and Technology Management Department. PSU. USA ** Master Student. Engineering and Technology Management Department. PSU. USA

Abstract Forecasting advanced or emerging technologies by determining their technology diffusion rates is a science and an art because of lack of experiential data. One method to assist in forecasting is data mining and analysis of bibliometric data from a variety of sources such as patents, journal citations, and science awards. This information can then be used in well-known technology diffusion models such as Fisher-Pry where emerging technologies substitute older ones. This paper uses global bibliometric analysis to forecast the growth of advanced or next-generation electronic packaging technologies relying on analogous technology growths.

978-1-890843-23-6/11/$26.00 ©2011 IEEE

Agenda

1. Problem Statement 2. Forecasting Methodology 3. Results Growth Curves 4. Results: Compilation of Growth Curves 5. Lessons Learned 6. Conclusion and Recommendations

1. Problem Statement Importance Effects Chip Reliability, Costs, Density, and Integration

1. Problem Statement: Electronic Packaging Evolution

Source: [9]

Upstream Chip Production

Downstream References: [1], [8], [9], [10], [11]

Chip Assembly

1. Problem Statement Forecast advanced electronic packaging technologies (EP) using bibliometrics such as patents, journal papers, and science research awards. Use Fisher-Pry Forecasting Method (S-Curves) for diffusion of emerging technologies [2]. Observe relationship between the different types of bibliometrics – lagging and leading S-Curves.

2. Forecasting Methodology Assumption Advanced/Emerging EP Technologies follow Fisher-Pry Diffusion Model Methodology Use of established databases (data sources) and keywords for bibliometric information – e.g. patents /year from 1990 to 2009 (later information may be incomplete) Determine % cumulative penetration for each EP technology and for each type of bibliometrics Fit Fisher-Pry curves to existing data and extend to 2020 to forecast penetration rates Fisher-Pry Diffusion Model: Represents substitution technologies (when substitution is driven by superior technology and new product presents some technological advantage over the old one)

2. Forecasting Methodology Data Sources Application

Data Sources

Research Award

National Science Foundation NSF funding data

Journal Papers

Science Citation Index SCI

Patents

United States (USPTO) International (PCT) Europe (EPO) Japan (JPO) Korea (KIPO) INPADOC (INPADOC)

2. Forecasting Methodology Keywords Search SiP



BGA –

“System-in-package” “Ball Grid Array Packaging”

MEMS – “MEMS Packaging” and “Microelectromechanical Systems Packaging” 3DIC –

“3-D Integrated Circuit Packaging”

WLP –

“Wafer Level Packaging”

2. Forecasting Methodology Working Example MEMS Cumulutive Max L 100% Penetration

37,667 100 38,000

Assumption: L=100% is represented by 38,000 patents (MEMS Analogy)

Cumulative

34,243

Predicted % Pen. Fisher-Pry Curve (FP) Intercept=A -346.7588

log(Y/L‐Y)

Slope=-B

1.50000

0.1729

1.00000

Error Stats SUMSQ

y = 0.1729x ‐ 346.76 R² = 0.9862

0.50000 0.00000 ‐0.500001985

182.53

1990

1995

2000

2005

‐1.00000

Mean Sq Err

‐1.50000

9.61

‐2.00000

2010

log(Y/L‐Y) Linear (log(Y/L‐Y))

‐2.50000 ‐3.00000

% MEMS Patent Forecast 120.00 100.00 80.00 60.00 % MEMS Patent Penetration 40.00

MEMS Fisher‐Pry Curve

20.00

Year

2020

2018

2016

2014

2012

2010

2008

2006

2004

2002

2000

0.00 1998

FP-Error -0.01381 0.07947 0.18550 0.25781 0.23292 0.10944 -0.01106 -0.37952 -0.82627 -1.76935 -3.12183 -4.53726 -4.08881 -3.44586 -3.38546 -2.64519 -0.70308 1.81417 4.35968 8.84454

1996

log(Y/L-Y) -2.67578 -2.38209 -2.16351 -1.99795 -1.87155 -1.75464 -1.61267 -1.48891 -1.34440 -1.21715 -1.08275 -0.92243 -0.68863 -0.47663 -0.29148 -0.10066 0.10617 0.32720 0.57040 0.95973

1994

{L*10^(A-Bt)}/{1+10^(A-Bt)} 0.22434 0.33369 0.49608 0.73692 1.09340 1.61951 2.39263 3.52163 5.15522 7.48777 10.75604 15.21620 21.08881 28.46691 37.20914 46.87677 56.78466 66.17793 74.44821 81.26861 86.59625 90.58415 93.47497 95.52213 96.94799 97.92966 98.60014 99.05558 99.36380 99.57186 99.71208

1992

MEMS - Patents Pat/Yr % Pen. Y 80 0.21 77 0.41 102 0.68 119 0.99 126 1.33 153 1.73 248 2.38 289 3.14 451 4.33 528 5.72 728 7.63 1157 10.68 2402 17.00 3048 25.02 3345 33.82 3955 44.23 4503 56.08 4526 67.99 4110 78.81 4296 90.11

1990

t 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

% MEMS  Patent Penetration

Year

3. Results Growth Curves

1. Awards 2. Journal 3. Patents

3. Results Growth Curves Research Awards Methodology employed: 5 Keywords :

3D Integrated Circuit, Wafer Level Packaging, Ball Grid Array, System in Package, MEMS

Search approach: Keywords in all the document Database

:

NSF funding data

Date

:

Feb 10, 2011

Assumption : Maximum value of research awards is represented by 1500 cumulative Analogy

3. Results Growth Curves Cumulative Graph

3. Results Growth Curves MEMS Awards Forecast 120.00

80.00 60.00 40.00 20.00

BGA Awards Forecast

0.00

30 25 % Penetration

% Penetration

100.00

20 15 10 5 0

Year

3. Results Growth Curves 3DIC Awards Forecast 40

40

35

35

30

% Penetration

% Penetration

WLP Awards Forecast 45

30 25 20 15 10

25 20 15 10

5

5

0

0

Year

Year

SiP Awards Forecast 18

% Penetration

16 14 12 10 8 6 4 2 0

Year

3. Results Growth Curves

1. Awards 2. Journal 3. Patents

3. Results Growth Curves Science Citation Index Methodology employed: Keywords

: “3D Integrated Circuit Package”, Wafer Level Packaging, Ball Grid Array, “System in Package”, MEMs

Search

: Topic=(Keyword) Timespan=All Years

Databases : SCI-EXPANDED, SSCI, A&HCI Date

: Feb 3 2011

3. Results Growth Curves Cumulative Graph

3. Results Growth Curves

3. Results Growth Curves

3. Results Growth Curves

1. Awards 2. Journal 3. Patents

3. Results Growth Curves Patent Boliven Methodology employed: Keywords

Search Databases

: “3D Integrated Circuit Package”, Wafer Level Packaging, Ball Grid Array, “System in Package”, MEMs : General=(Keyword) : United States (USPTO) International (PCT) Europe (EPO) Japan (JPO) Korea (KIPO) INPADOC (INPADOC)

3. Results Growth Curves

Cumulative and Non-cumulative graphs

3. Results Growth Curves

3. Results Growth Curves

4. Results:

Compilation of Growth Curves

4. Results: MEMS Packaging • Research Awards Lead • Journal Citations and Patents Close

Max 5 Year Lag

4. Results: BGA Packaging • Patents Lead • Journal Citations Close • Research Awards Lag Significantly Max 1 Year Lag

4. Results: 3DIC Packaging • Patents Lead • Journal and Research Awards Lag Significantly

7+ Year Lag

4. Results: WLP Packaging • Journal Citations Lead Initially • Patents Lead After 50% Growth • Research Awards Lag Significantly

High Variation

4. Results: SiP Packaging • Journal Citations Lead Initially • Patents Lead After 10% Growth • Research Awards Lag Significantly

Max 5 Year Lag

5. Conclusions • BGA and MEMS are very close to the maturity level for commercial application. There is a drastic reduction of patents related with these two technologies. • SiP, 3DIC and WLP are in earlier stages of their growth curves. High levels of maturity are expected by 2020. • For advanced EP technologies, research awards are not reliable leading indicators. • Fisher-Pry growth curves for research awards, journal papers, and patents did not follow completely the expected sequence. • Journal papers and patents growth curves are close for mature technologies like MEMS and BGA implying strong industry adoption.

6. Recommendations • Strong industry adoption of WLP and SiP. Hence government research awards are nominal. • For advanced technologies that are closely tied to industrial applications such as electronic/ semiconductor chip manufacturing it may be better to use more industry oriented data mining such as patents, trade shows, number of companies or startups, etc. • Another step for forecasting could include using industry experts and a Delphi model for forecasting (and further validation). • More specific keywords are needed in order to come up with more applicable results.

Thanks! Q&A

BGA The BGA is descended from the pin grid array (PGA), but in this case, the pins are replaced by balls of solder stuck to the bottom of the package. The device is placed on a Printed Circuit Board PCB that carries copper pads in a pattern that matches the solder balls. The assembly is then heated, causing the solder balls to melt. Surface tension causes the molten solder to hold the package in alignment with the circuit board, at the correct separation distance, while the solder cools and solidifies.

SiP Also known as a Chip Stack MCM, is a number of integrated circuits enclosed in a single package or module. SiP dies are stacked vertically. SiP connects the dies with standard off-chip wire bonds or solder bumps, unlike slightly denser three-dimensional integrated circuits which connect stacked silicon dies with conductors running through the die

3D Integrated Circuit It is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit.

WLP Wafer-Level Packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level. WLP is essentially a true chip-scale packaging (CSP) technology, since the resulting package is practically of the same size as the die

MEMs (MicroElectroMechanical Systems) Miniature mechanical devices built onto semiconductor chips and have dimensions in the micrometer range. Uses pressure, temperature, chemical and vibration sensors light reflectors and switches accelerometers for airbags vehicle control Pacemakers Games inkjet print heads microactuators for read/write heads

References [1] Bolanos, Mario A, Texas Instrument, “Electronics Market and Packaging Technology Trends: Applied Research Opportunities”, 2007. [2] T.U. Daim, G. Rueda, H. Martin, and P. Gerdsri, “Forecasting emerging technologies : Use of bibliometrics and patent analysis,” Technological Forecasting and Social ChangeSocial Change, vol. 73, 2006, pp. 981 - 1012. [3] G. Deptuch, J. Hoff, F. Khalid, M. Trimpl, A. Shenai, and T. Zimmerman, “3D-IC technology for future detectors,” 2009, pp. 1-32. http://www-ppd.fnal.gov/EEDOfficeW/ASIC_Development/Assets/Presentations/3D_fnal_gd.pdf [4] X. Gagnard and T. Mourier, “Microelectronic Engineering Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration,” Microelectronic Engineering, vol. 87, 2010, pp. 470-476. [5] P. Leduc, “What is 3D IC integration and what metrology is needed ? Outline Challenges of advanced interconnects 3D integration for Integrated Circuits (3D ICs) Applications for 3D ICs 3D IC technologies: Integration approaches and main players Metrology needs,” conference on Frontiers of Characterization and Metrology for Nanoelectronics, 2007, pp. 1-28. [6] L. Porter, A.T. Roper, T.W. Mason, F.A. Rossini and J. Banks, “Forecasting and Management of Technology”, Wiley, New York (1991). [7] International IOR Rectifier, “Wafer Level Package Technology”, pp. 0-4. [8] ITRS, International Technology Roadmap for Semiconductors, “Assembly and Packaging”, 2009 [9] ITRS, Assembly and Packaging Technical Working Group. “The Next Step in Assembly and Packaging”, 2008. [10] iNEMI, International Electronic Manufacturing Initiative, “Packaging Roadmap Overview”, 2005 [11] VTI. Technologies, “WHAT IS AHEAD IN THE PACKAGING ROADMAP OF MEMS?”, 2006, pp. 1-3. [12] Ho-Ming Tong, “Microelectronics packaging: present and future,” Materials Chemistry and Physics, 1995. [13] Yole-Developpemente, 3DIC & TSV Report: Cost, Technologies & Markets, 2007

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