Foreword special issue on device integration technology ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003

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Foreword Special Issue on Device Integration Technology for Mixed-Signal SOC

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HE LAST 10 to 15 years have witnessed a rapid increase in the use of the Internet and mobile communications. This has resulted in a proliferation of electronic Internet products and cellular phones. Today, these applications share the dominant position held exclusively by the personal computer for several decades as the driver for semiconductor device technology. Personal computers are built around a microprocessor and memory. Their computing speed and cost continually improve with a Moore’s Law scaling of MOS transistors. In contrast, most Internet products depend on digital signal processors (DSPs) together with analog functionality, and are required to perform according to preset standard specifications. Thus, for most Internet products, shrinking transistor size alone is insufficient. It becomes necessary to integrate the DSP and analog functions into a mixed-signal “System-on-a-Chip” (SOC) to maintain a competitive pace of improvement in system cost and performance. This means that in today’s “Internet Era” the driver’s seat for silicon device technology is shared together by Moore’s Law and SOC integration. One important application driving SOC integration is the cellular phone. Inside a typical cell phone there are only a few integrated circuits but numerous passive components that are used for functions such as transmit/receive radio frequency (RF) signals and analog-to-digital conversions. Therefore, there is a potentially significant cost and performance benefit with integrating many of these functions as a part of an existing digital baseband chip. Several papers in this issue deal with device technology for integration of passives, particularly inductors. As the cell phone technology moves from 2G to 2.5G/3G (third generation) phones with enhanced Internet access, the push for more integration of digital and analog/RF functions will intensify. Another area that is driving this integration is short distance wireless applications such as Bluetooth, HomeRF, and Wireless LAN. Here, mainly for cost reasons, it becomes necessary to integrate RF functions into a digital chip. In this case, the performance requirements for RF/analog blocks are not as demanding as for cellular phones. Nevertheless, the different device requirements for RF/analog functions compared to digital logic functions make the integration of these functions a challenge for process integration, device/component design and circuit design. A number of authors here have discussed the issues in integrating RF/analog with digital CMOS. Successful co-optimization of devices for digital and RF/analog functions requires understanding and modeling multiple aspects of the devices. To that purpose we have several papers discussing device noise. Traditionally, integrated circuit process and transistor/component designs for digital, RF/analog functions, and battery power

management have been done separately since they are on separate chips and done with considerably different process flows. Now the SOC integration of these functions requires new thinking and innovative approach to satisfy often-conflicting requirements with a single integrated flow. Devices with widely varying characteristics may be needed, leading to complex process integration to allow for multiple gate oxide thickness, high performance bipolar, high-resistivity substrate and triple well. One of the questions for the flow design is the choice of technology for the specific application at hand. Here, the cost/performance tradeoff between Si CMOS, BiCMOS, and SiGe BiCMOS becomes an important factor. We include a number of papers that present the recent advances in these technologies and discuss the tradeoffs for various device and process technologies. In conclusion, increased demand for broadband Internet access, high-speed networks, versatile mobile phones, and shortrange wireless have fueled research in recent years in SOC integration that targets cost reduction for high-volume production of these new applications. We hope that the papers in this special issue will bring to the reader a flavor of that research and development activity. We acknowledge the dedicated help from Ms. Jo Ann Marsh in preparing this special issue, invaluable advice and help from Prof. Hiroshi Iwai and initial encouragement from Prof. Rajendra Singh, Prof. Krishna Shenai, and Dr. Doug Verret.

Digital Object Identifier 10.1109/TED.2003.810463 0018-9383/03$17.00 © 2003 IEEE

AMITAVA CHATTERJEE, Guest Editor Texas Instruments, Inc. Dallas, TX 75243–1108 USA [email protected] JOHN D. CRESSLER, Guest Editor Georgia Institute of Technology School of Electrical and Computer Engineering Atlanta, GA 30332-0250 USA [email protected] DIRK B. M. KLAASSEN, Guest Editor Philips Research Laboratories 5656 AA Eindhoven, The Netherlands AKIRA MATSUZAWA, Guest Editor Matsushita Electric Ind. Co., Ltd. Osaka 570-8501, Japan [email protected] HISASHI (SAM) SHICHIJO, Guest Editor Texas Instruments, Inc. Dallas, TX 75243–1108 USA [email protected]

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Amitava Chatterjee (SM’91) received the Ph.D. degree in electrical engineering in 1985 from Rensselaer Polytechnic Institute, Troy, NY, the M.S. degree in electrical engineering in 1980 from Louisiana State University, Baton Rouge, and the B.Tech. degree in electronics and electrical communications engineering from Indian Institute of Technology, Kharagpur, in 1978. Since 1985, he has worked on silicon research and development at Texas Instruments, Dallas. Currently, he is Distinguished Member of Technical Staff responsible for process integration for digital and analog functions in 0.13- m and 65-nm CMOS technology. He has contributed over 75 technical papers and 30 patents in diverse areas of CMOS VLSI. His contributions include discovery of a drain barrier lowering mechanism unique to halo MOSFETs, development of the replacement metal gate MOSFET, and inventions contributing to manufacturable shallow trench isolation technology. Several of his patents on electrostatic discharge protection and shallow trench isolation technology have received patent usage incentive awards from Texas Instruments. Dr. Chatterjee is on the editorial board of IEEE ELECTRON DEVICE LETTERS and was a member of the CMOS Devices subcommittee of IEDM (1999–2000). He is a member of Sigma Xi.

John. D. Cressler (S’86–A’91–SM’91–F’01) received the B.S. degree in physics from the Georgia Institute of Technology, Atlanta, in 1984, and the M.S. and Ph.D. degrees in applied physics from Columbia University, New York, in 1987 and 1990, respectively. From 1984 to 1992, he was a Member of the Research Staff at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, working on high-speed Si and SiGe bipolar devices and technology. In 1992, he joined the faculty at Auburn University, Auburn, AL, where he remained until 2002. When he left Auburn, he was Philpott-Westpoint Stevens Distinguished Professor of Electrical and Computer Engineering and Director of the Alabama Microelectronics Science and Technology Center. In 2002, he joined the faculty at the Georgia Institute of Technology, Atlanta, where he is currently Professor of electrical and computer engineering. His research interests include SiGe devices and technology, Si-based RF/microwave/mm-wave devices and circuits, radiation effects, noise and linearity, cryogenic electronics, SiC devices, reliability physics, device-level simulation, and compact circuit modeling. He has published over 250 technical papers related to his research, and is the co-author, with Guofu Niu, of the book Silicon-Germanium Heterojunction Bipolar Transistors (Norwood, MA: Artech House, 2003). Dr. Cressler was an associate editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS (1998–2001), and has been recently appointed assistant editor of the IEEE TRANSACTIONS ON NUCLEAR SCIENCE. He served on the Technical Program Committees of the IEEE International Solid-State Circuits Conference (1992–1998, 1999–2001), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (1995–1999), the IEEE International Electron Devices Meeting (1996–1997), and the IEEE Nuclear and Space Radiation Effects Conference (1999–2000, 2002). He was the Technical Program chairman of the 1998 International Solid-State Circuits Conference (ISSCC). He currently serves on the Executive Steering Committee for the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, as International Advisor for the IEEE European Workshop on Low-Temperature Electronics, and on the Technical Program Committee for the IEEE International SiGe Technology and Device Meeting. He was appointed an IEEE Electron Devices Society Distinguished Lecturer in 1994, and was awarded the 1994 Office of Naval Research Young Investigator Award for his SiGe research program, the 1996 C. Holmes MacDonald National Outstanding Teacher Award by Eta Kappa Nu, the 1996 Auburn University Alumni Engineering Council Research Award, the 1998 Auburn University Birdsong Merit Teaching Award, the 1999 Auburn University Alumni Undergraduate Teaching Excellence Award, and an IEEE Third Millennium Medal in 2000.

Dirk B. M. Klaassen received the Ph.D. degree in experimental physics from the Catholic University of Nijmegen, The Netherlands, in 1982. He joined Philips Research Laboratories, Eindhoven, The Netherlands, where he has worked on various subjects in the fields of luminescence from the solid state and modeling for silicon device simulation. Currently, he is involved in compact transistor modeling for circuit simulation.


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Akira Matsuzawa (F’02) received the B.S. and M.S. degrees in electronics engineering from Tohoku University, Sendai, Japan, in 1976 and 1978. He received his Ph.D. in 1997 from the same university in high-precision and ultra-high-speed A/D converters. In 1978, he joined Matsushita Electric Industrial Co., Ltd, Osaka, Japan. Since then, he has been working on research and development of analog and mixed signal LSI technology, ultra-high speed ADCs, intelligent CMOS sensors, RF CMOS circuits, digital read-channel technology for DVD systems, ultra-high-speed interface technologies for metal and optical fibers, testing, boundary scan technology, and CAD technology. He also is responsible for the development of low-power LSI technology, ASIC libraries, analog CMOS devices, SOI devices and circuits, and the specification of advanced CMOS devices. Currently, he is a General Manager in the advanced LSI technology development center and is a part-time teacher at Osaka University and Tohoku University. He has published 19 technical journal papers and 39 international conference papers, and is co-author of eight books. He holds 34 registered Japan patents and 65 U.S. and EPC patents. Dr. Matsuzawa twice served as guest editor-in-chief for special issues on analog LSI technology of the IEICE Transactions on Electronics in 1992 and 1997, vice-program Chair for the International Conference on Solid-State Devices and Materials (SSDM) in 1999 and 2000, and was co-Chair of the Low-Power Electronics Workshop in 1995. He serves on the program committee for analog technology at ISSCC and as guest editor for special issues of the IEEE TRANSACTIONS ON ELECTRON DEVICES. He has received the R&D100 award in 1994. He is an IEEE Fellow since 2002.

Hisashi (Sam) Shichijo (F’92) received the B.S. degree in electronic engineering from University of Tokyo, Tokyo, Japan, in 1976 and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign in 1978 and 1980, respectively. He joined Texas Instruments, Dallas, in 1980 as Member of the Technical Staff. He has since been involved in various projects including MOS SRAM process technology, submicron MOS devices, device scaling studies, SOI polysilicon FETs for DRAMs and 3-D ICs, trench transistor DRAM cell for 4 Mbit DRAM, device and circuit design for 64 Mbit DRAM, and 1 Gbit DRAM process development. He was with the Central Research Laboratories for three years working on GaAs MESFET high speed SRAMs and memory/logic integration, and GaAs-on-Silicon devices before returning to Semiconductor Process and Design Center (Silicon R&D center) in 1989. He is currently a Texas Instruments Fellow at TI’s Silicon Technology Development Group and has been involved in analog and RF integration in TI’s 180 nm, 150 nm and 90 nm CMOS technologies in the last five years. Dr. Shichijo served as the conference chairman at the 1992 Device Research Conference.