DC Bias AnaIysis and Small-Signal Characteristic of Active-Clamp Forward-Flyback DC-DC Converter with a Current DoubIer Rectifier Yangyang Wen", Hong Mao**, and Issa Batarseh*
Department of Electrical and Computer Engineering University of Central Florida Orlando, Florida 32816, USA Absrracr: The paper presents the steady-state and
dynamic small-signal models for the active-clamp forward-flyback DC-DC converter with a current doubler rectifier. Based on the established models, several issues, such as inductor current sharing, transformer DC bias o f magnetizing current and converter design, are discussed.
I. INTRODUCTION Active-clamp forward converter is one of the most attractive soft-switching topoIogies and is found in applications of low-voltage high-frequency dc-dc converters. The advantage of the topology is that the leakage and magnetizing inductance is utilized for ZeroVoltage-Switching (ZVS) and the primary-side ringing is eliminated, which allow a converter to operate at higher switching frequencies [ 1]-[3]. For isolated low-outputvoltage converters, secondary-side power losses are dominant, and hence they have the major effect on the conversion efficiency. The secondary-side Current-Doubler rectifier (CDR) can minimize the transformer secondarywinding rms current and has better thermal management for the output inductors 14-51.Moreover, the CDR minimizes the number of high-current interconnections that simplifies the secondary layout and firther reduces the layout-related losses [5]. CDR is usually employed with conventional symmetric topologies such as full-bridge, push-pull and half-bridge. As a matter of fact, the CDR can also be utilized with active-clamp forward, which is named forward-flyback DC-DC converter [6]-[7]. In 161, the steady-state design was provided with the analysis of operation modes. However, the literature assumes the two inductors evenly share the output current and replace the two inductors by current sources. However, in fact, the two inductors carry unequal currents, and the DC bias of magnetizing current exists and varies with duty cycle. Even with the primary-side current mode control, current sharing between two inductors cannot be achieved because only single-ended current i s sensed and controlled. In high current rectification applications, the current sharing in CDR has significant impact on the converter thermal balance and rectifier efficiency [SI.Moreover, unbalanced DC currents may lead to failure of the magnetic cores due to saturation [3][8]. It is very important to estimate the DC
Astec Power Advanced Technology Andover, MA 0 1810, USA
[email protected] currents in the transformer so that the DC bias can be considered in the original magnetics design. Due to the CDR structure, the dynamic small-signal model of fonvardflyback converter is essentially different from conventional forward converter, however few literature investigates the modeling issues of the forward-flyback converter, In the paper, the steady-state DC currents analysis is provided employing the state-space averaging concept. Many important design and layout rules are presented based on state-space averaging modeling. Moreover, Smallsignal model based on the state-space averaging is established to investigate the converter dynamic performance. Simulation results are presented to verify theoretical analysis. Next section establishes the unified steady-state model and finds out the DC solutions. Section I11 addresses current-unbalance issues and design rules. In Section IV, Simulation results are presented to verify the analysis. Conclusion is given in Section V. 11. AVERAGED STATE-SPACE MODEL OF
FORWARD-FLYBACK DC-DC CONVERTER The active-clamp forward-flyback dc-dc converter with a CDR is shown in Fig. l(a). Neglecting the leakage inductance and transient commutation, and considering the converter operating at CCM mode due to the synchronous rectifier, the converter has two typical modes as shown in Fig. l@) and (c), where the load are assumed as a constant current source since the voltage ripple is ignorable. RLI,Ru are equivalent DC resistance of the inductor L1 and Lz, respectively. Rc is the ESR of output capacitors. RT is the transformer winding equivalent DC resistance reflected to secondary side. Assuming all DC resistance values mentioned above are zero, the converter steady-state voltage stress and current are shown in Table 1 and 2, respectively. The voltage gain ratio and voltage stress in components are the same as in the conventional active-clamp fonvard converter, thus the transformer turn ratio is the same for both topologies. From Table 2, it is observed that the inductor current ripples are determined on filter inductance values and duty cycle. The output current ripple is derived in Table 2, where the equivalent filter inductance value Leq is:
If LI=L2=L, the equivalent filter inductance value Leq becomes:
The Equation (2) is plotted in Fig. 2. As it is shown, in , the equivalent inductance value Leq i s larger than individual inductance value L. In other words, in a large range of duty cycle operation, the current ripple cancellation can be achieved and the output current ripple is reduced compared to conventional active-clamp forward converter. Especially, when the duty cycle is close to 0.5, zero output current ripples can be achieved. Compared with active-clamp forward converter, the forward-flyback dc-dc converter has duty cycle range centering on 0.5 while keep small output ripple. By design asytnmetric inductances of L, and L2, better current ripple caricellation is expected. the duty cycle range of 0 < 0 < 2 / 3
Fig. 1. Forward-flyback dc-dc converter 5
Fig. 2. Equivalent inductance V.S. duty cycle Table 1: Steady-state voltage stresses
L1
L2
I
Output current
(b) S2 is on
(a) SI is on
Fig. 3 Operation modes
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As shown in Fig.3, there are two operation modes. In a switching period, the converter can be denoted using two linear state-space equations, respectively, and two corresponding equations are expressed as equation (I), where X is the vector of state variables, U is the vector of independent sources; A , , B l ,A, and B, are respective system matrices in each of the two switched networks. AI , Bl,A2and 3, can be derived from operating modes in Fig. 1 (b) and Fig.l(C). During the on time of switch S1, the corresponding matrices AI and BI are derived in Equation (3), During the on time of switch S2, the corresponding matrices A2 and Bz are derived in Equation (3).
X = A,x + B,u (m= 42) y=Cx+Dzr where x = [im x. = - dx dc
.
zL1
where the equivalent matrices are defined by
.
The steady-state solution, with DC values indicated by capital letters, is obtained by setting x
(3) (4)
I, =
RLl + DRT
' L l + RL2 -k T'
ILI =
y=v,
u = [ s lor
(7)
Through equation (3)-(7), points can be obtained:
vc0 vcr]
iL2
0 :
x =-A-'Bu
T
,
=:
the steady-state DC quiescent
10
RL2 + (1 - DIRT
(9)
RLl + RL2 + RT
I,,
=
RL1 + DRT RL1 + RL2 RT
I*
0
O
Ol
111. STEADY-STATE AND DC ANALYSIS OF 1 -
1 -
CO
CO
0
0
FORWARD-FLYBACK CONVERTER
From the derived Equation (8)-(1 l), one can generally observe that: (1) Only DC resistance values and steady-state duty cycle have effect on the DC bias of the converter, the capacitance and inductance values have no impact on DC bias. (2) On-resistances of primary-side switches and secondaryside synchronous rectifiers have no effect on the converter DC current bias. (3) The transformer DC bias of magnetizing current always exists and is positively proportional to the output current. (4) The transformer DC current value is equal to one of the average inductor current value. Assuming I,, = IL2 in Equation (9) and (1 0), one can obtain:
O0 0 OJ
4
-
0
0
(RL2 RLI ) + (1 - 2D)RT = 0 The following cases can satisfy Equation (12): Case 1: R,, =RLz and D=O.5
-
Case2: R,, = RL2 and RT = 0
0 -4
4 = 0
4 4 4
Case3: RL1-RL, = (1 - 2D)RT (where R,, RLz,Rr # O , D # O S ) For Case 1, RL, = R~~ can be satisfied with symmetric DC inductor resistance. In that case, even indictor current sharing can be achieved only a t d = 0 . 5 . However, at most of cases, d # 0.5 due to variable input voltage. Therefore, even current sharing cannot be achieved even at symmetric inductor design. Case 2 cannot be satisfied because the transformer DC resistance is not negligible compared with inductor DC resistance. Due to the fact that duty cycle vanes with the input voltage and load, Case 3 cannot be satisfied. In conclusion, even current sharing cannot be achieved in a regulated
I
0 --
CO
0
(12)
0
The matrices C and D is derived as follows: R, 1 01 D=[D -41 Assuming the duty cycle of the switch S I and Sz are
C=[O R,
d and I - d , respectively. The key concept in state-space averaging is the replacement of the two sets of state-space equations by a single united equivalent set 1533
magnetics design. The worst case occurs at highest CSC value and full load.
forward-flyback dc-dc converter. Due to the transformer DC resistance RT,the two inductors cany unequal currents, which has significant impact on the converter thermal balance and rectifier efficiency. This must be considered in the transformer and inductors magnetics design. Assuming R~~= RL2= R,, , rewrite Equation (a)-( 10):
05
0.4
1
CSCI
(D) 03
0.2
0.1
0
D DutyCyck
It can be seen that the smaller the RT value compared with RL value, the better current sharing can be achieved. To evaluate the current sharing, we define the current difference between two inductors as:
CSCl (D)----RJR&.S;
CSCZ (D)----RJRr=l; CSC3 (D)----RJRFZ
Fig. 4. CSC value V . S . duty cycle
IV. SMALL SIGNAL ANALYSIS OF FORWARD-FLYBACK CONVERTER
From the above equaxion, defining the Current Sharing Coefficient (CSC) as:
Based on the unified average model in Equation (5) and (6), the small-signal dynamic model of the forward-flyback converter with a current doubler can be derived using the averaging small-signal technique. Perturbing the state-space average equations as follows:
From definition above, we can see the current sharing depends both duty cycle and the DC Resistance (DCR) ratio of inductors to transformer. When the duty cycle value is closer to O S , and the higher the 1)CR ratio of RJRT, the smaller CSC coefficient and h e better the current sharing are achieved, CSC value versus duty cycle under different DCR ratios are plotted in Fig. 4. Therefore, the converter design should center the duty cycle 0.5 to achieve good current sharing and smaller output current ripples as indicated in Section 11. In term of CSC, Equations (13-15) can be rewritten in the following form:
I
1
1
2
2
1
1
2
2
I,,, =-I,--CSC*I,
I4 =-I,+-CSC*I,
Then we can derive the linear small-signal model based on small-signal assumption and liberalization:
The output-to-control transfer function is expressed as follows:
Under the following parameter condition: {OSDSO.S)
(18) (OSD10.5)
The output-to-control transfer function can be derived and the corresponding bode diagram is plotted in Fig. 5 at various duty cycles. It should be noticed that the phase delay are so different with different duty cycles. If the duty cycle is smaller than 0.5, the largest phase delay of the system is less than 180 degree, and the system behave like a second-order system. When the duty cycle is larger than 0.5, the system phase delay increases and the looks like a 4" order system. So the design should consider the largest duty cycle as the worst case. In other words, low-line input is the worst case for the design consideration.
It is shown that inductors and transformer carry half the output current when good current sharing is achieved. CSC and output current are crucial in converter design, especially
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Fig. 5. Bode diagram at various duty cycles
V. SIMULATION VERIFICATION Simulation results show that the previous DC model and analysis is accurate. To-be close to real converter, the leakage inductance is added in the simulation. The converter parameters are same as in Section IV. Assuming the converter operates at D=0.3, substituting R ~ l = l . 5 mOhm, R t ~ = l S m Ohm, R ~ 2 m Ohm and D-0.3 into Equation (17), we obtain: CSC= 0.16. From Equation (lS), at full load I,=40A, the DC currents are: tm=16.3A, 1~,=23.2A,IL2=16.8A.From Fig. 6 (a), it is observed that two inductors do not evenly share load current and the simulated average currents are very close to the calculated results. When the converter operates at D4.5, from Equation (I7), we obtain CSC=0, which means good current sharing can be achieved between inductors at D-0.5. From Fig. 6@), it i s clearly shown that the average currents I,= 1~1=1~2=20A. At duty cycle of 0.7, from Equation (17), we obtain CSC=O.16,substituting CSC into Equation (19), we Iu=23.2A7which is very close to obtain Im-23.2A, 1~1=16.8A, the simulation results shown in Fig. 6(c). Based on the Pspice simulation model, frequency sweep is manually added to the modulated DC signal point by point. The resulted bode diagram at Dz0.3 is plotted in Fig. 7, which is very close to the theoretical bode diagram plotted in Fig. 5 from the established small-signal dynamic model in Section IV.
(a) Duty cycle D=0.3A
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[4] K.O’Meara, “A new output rectifier configuration optimized for high frequency operation”, in Proceeding of High Frequency Power Conversion canference, HFPC 1991, pp.219-225. [5] Y. Panov and M. Jovanovic, “Design and Performance Evaluation of Low-Voltagemigh-Current DClDC On-Board Modules”, IEEE Transaction on Power Electronics, Vol. 16,No.1, pp.
. . .
26-33,2001. [6] Laszlo Huber and Milan M. Jovanovic, “Forward-flyback
Converter with Current-Doubler Rectifier:Analysis, Design and Evaluation Results”, IEEE Transactions on Power Electronics, Vol. 14,No. 1, pp.184-192. [7] N Frohleke, J Richter, P. Wallmeier and H Grotstollen, “Soft switching forward-flyback converter with one magnetic component and current doubler rectification circuit”, Industry Applications Conference, TAS 1996. pp. 161- 1168. [XI Nong Mao,Songquan Deng, Yangyang Wen and Issa Batarseh, ”Unified DC Model and Analysis of Half Bridge DC-DC Converters with Current Doubler Rectifier“, The 19‘ Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2004, pp786-791.
(C) Duty cycle D=0.7 Fig. 6. Simulation results with different duty cycles
0 000
i -200
Frequency(k)
Fig. 7. Bode diagram at D=0.3 VI. CONCLUSION Forward-flyback dc-dc: converter is a candidate topology
for high switching-frequency, high-current and low-voltage dc-dc conversion. The paper presents both steady-state and dynamic small-signal models and relative design issues in the converter. A series of design guidelines are provided based on the mathematical work.
ACKNOWLEDGMENT The authors would like to thank Mr. Geof Potter and Mr. Brad Higgins at ASTEC Rower for their technical support and helpful discussion. REFERENCE [l] P. Vinciarelli, “Optimd resetting of the transformer core in Single ended forward converter ””,U. S. Patent, No. 4,441,146, April
1984. [2] 3. Andreycak, “Active clamp and reset technique enhances forward converter performance”, Unitrode Power Supply Design Seminar, SEM-1000, 1994. [3] Qiong Li and Fred C. Lee, “Design Consideration of
Transformer DC Bias of Forward Converter with Active-Clamp Reset”, Applied Power Electronics Conference and Exposition, APEC ‘99. pp. 553 - 559. 1536
