FPGA-Based Combined PWM-PFM Technique to ... - IEEE Xplore

FPGA-Based Combined PWM-PFM Technique to Control DC-DC Converters Prashant Agnihotri, Student Member, IEEE, Naima Kaabouch, Member, IEEE, Hossein Salehfar, Senior Member, IEEE, and Wen-Chen Hu1, Member, IEEE Department of Electrical Engineering, University of North Dakota, Grand Forks, ND 58202-7165 1 Department of Computer Science, University of North Dakota, Grand Forks, ND 58202-9015 Department of Electrical Engineering, University of North Dakota, Grand Forks, ND 58202-7165 Abstract- This paper describes a combined Pulse Width Modulation (PWM)-Pulse Frequency Modulation (PFM) technique implemented in a Field Programmable Gate Array (FPGA) to control DC-DC converters. This technique changes the mode of operation from PWM to PFM with the change in the load condition. The efficiency of the proposed technique is determined by implementing a DC-DC converter and calculating the conduction losses, switching losses, and ripple voltages at different load values. Furthermore, the efficiency of the converter based on the proposed technique is compared to the efficiency of processor-based implementation. The results show that the efficiency of the converter with the FPGA-based technique is higher than the efficiency of the converter with processor based technique. Index Terms- DC-DC converters, FPGA, Pulse Width Modulation, Pulse Frequency Modulation, VHDL language. I. INTRODUCTION DC-DC converters, such as boost and buck converters are commonly used in portable devices to scale up and down the output DC voltages. In these converters, the switches are used to transmit the appropriate power to the load. The duration of the ON time (duty cycle) of the switch is achieved through a control pulse in order to maintain the output voltage constant with the change in the load conditions. Modulation techniques such as Pulse Width Modulation (PWM) are used to generate these control pulses [1]-[3]. However, PWM cannot maintain the required voltage at wide load ranges [4]-[6]. In boost converters, at low load conditions, when the duty cycle of the control pulse goes above a threshold, Dmax, the conduction losses increase and, hence, the required voltage is not achieved [7].

Similarly, in buck converters, at high load conditions if the duty cycle is below a minimum value, D min, the effective current through the inductor goes below zero and the required voltage is not achieved [8]-[9]. Therefore, PWM technique can only be used at limited load values. To increase the efficiency of DC-DC converters at wide load ranges, a new technique, Pulse Frequency Modulation (PFM), was introduced [10]. In this technique, the switching frequency of the control pulse is modulated to regulate the output voltage at different load conditions. However, due to the high switching frequency, the switching losses are high in the PFM technique [11]. This problem was addressed by changing the PWM to PFM mode by sensing the current at the output [12]-[13]. However, the current sensing circuitry has an additional power requirement, which is an overhead in low power devices [14]-[17]. Furthermore, the generation of the control pulse through the combined PWM-PFM technique was implemented using processor and analog components which have their own power requirements and losses [18]-[21]. This paper proposes a voltage sensing method to control switches in DC-DC converters. This modulation technique does not require any external sensing circuitry. The technique is tested at wide load ranges (40Ω to 550Ω) in which the converter needs to operate beyond duty cycle limitations. The logic of the PWM-PFM is implemented in a Field Programmable Gate Array (FPGA) chip which uses less power, thus reducing the power dissipation due to the use of analog components and processors. II. METHODOLOGY The block diagram of the proposed technique is described in Fig. 1. The output voltage of the DC-DC converter is converted to a digital signal using an Analog to Digital converter (ADC). The selection between PWM and PFM modes is achieved through a block Selector Mode. This block measures the duty cycle (D), and if D is

within the range [Dmin, Dmax], PWM is used to generate the control pulse. Otherwise, the PFM technique is used. A 2-to-1 multiplexer is used to select the control pulse from either PWM or PFM, depending on the enable signal, E. As one can see in Fig. 1, this Enable signal turns on either the PWM or PFM block depending on the duty cycle value. The Select signal (Sel) is used to select the control pulse between Vcon1 through PWM or Vcon2 through PFM.

In this figure, a triangular signal, Vtp, and an error voltage, Verr, are used to generate the control pulse. The error voltage (Verr) is calculated as the difference between the output voltage (Vout) and a reference voltage (Vref). As can be seen, the control pulse (Vcon) is high when Vtp>Verr and low when Vtp