FPGA BASED VME BOARDS FOR INDUS-2 TIMING CONTROL SYSTEM Nitin Lulani#, K. Barpande, P. Fatnani, Y. Sheth Raja Ramanna Centre for Advanced Technology (RRCAT), Indore Abstract FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards.
INTRODUCTION With the advent of reasonably priced programmable logic devices (FPGAs), which combines tremendous computing power, re-configuration feature and I/O capability, the design of complex digital logic has found a new direction. Availability of tools to develop logic has also provided the capability to test the functional as well as timing behaviour of the logic even before the development of hardware. Control system of Indus-2 is a three-layered architecture where timing control system plays very crucial role for successful injection of beam. Timing control system of Indus-2 requires complex digital logic to generate coincidence clock board outputs and programmable coarse-fine delays. Discrete digital logic ICs based earlier boards were not capable of incorporating more than four coarse delay channels with the limitation of fine delay generation on separate board for same channel.
in Indus-2, synchronization is needed for precise extraction of bunches from booster to fill desired bucket of Indus-2 ring. Coincidence clock generator board generates coincidence clock (fc) to achieve this synchronization. Coincidence clock is derived from Indus-2 RF clock as follows: Indus-2 RF, fI-2=16XfB (Booster RF) Revolution frequency of I-2 = Revolution frequency of Booster =
fI-2/291 fB/3
If NI-2 and NB are number of revolution of bunches in Indus-2 and Booster respectively then, NI-2 X (291/ fI-2) NI-2 X 97
= NB X (3/ fB) = NB X 16
It implies that during the time when a bunch makes 97 turns in booster, bunch in Indus-2 will make 16 revolutions. So the coincidence time is 16X(291/ fI-2) = 9.205 µsec. Apart from generating fc, coincidence clock generator board also generates reference trigger for other delay generator boards. Reference trigger is generated by delaying input trigger with specific delay value to fill a particular bucket of Indus-2. For ‘single bucket filling’ mode this delay remains fixed as every time same bucket has to be filled, but for ‘multiple bucket filling’ and 3symmetrical bucket’ modes, delay to generate reference trigger changes during each consequent injection. Delay count for next injection is changed by CPU board of VME every second. Earlier controlled filling of Indus-2 ring was not possible because high noise levels of kicker power supplies were affecting the RF clock at 505.8 MHz and ECL noise margin was low. In order to have more reliable operation, new FPGA based coincidence board was developed. This board has an additional feature of programmable division of input clock. Presently coincidence clock generator board works with 63.225MHz clock (Indus-2 RF/8), giving resolution of the order of 15ns for jitter in output with respect to input. Read-back feature is also provided in new coincidence generator board.
COINCIDENCE GENERATION Coincidence clock generator board for timing control system of Indus-2 is designed for controlled filling of buckets in the ring in three selective modes, viz. 'Single Bucket', 'Three Symmetric Buckets' and 'Multiple Buckets' filling mode. Booster ring (at 31.6MHz RF clock) delivers e- bunches to Indus-2 ring (at 505.8MHz RF) every one-second. Booster ring has 3 bunches separated by 33ns, however Indus-2 ring has 291 buckets separated by ~2ns. To achieve controlled filling of beam #
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DELAY GENERATION Timing control system is also designed to generate triggers for pulsed power supplies of one booster extraction septum, one booster extraction kicker, two Indus-2 injection septum and four Indus-2 injection kicker magnets. These magnets are responsible for extraction of beam from booster and its injection in Indus-2. Delay generator boards of timing control system generates these triggers as per delays (coarse & fine) set by operator in
control room. Control systems of Indus-2 operates in noisy environment, the need is to provide maximum noise immunity by control system. In old configuration, outputs of coarse delay board were routed to separate fine delay board through FRC connector. Limitation of old boards: 1. Separate boards for coarse and fine delay generation 2. Coarse delay resolution was restricted to ~33 ns due to the use of TTL logic ICs. 3. Use of obsolete part for fine delay generation. 4. Possibility of less number of channels on coarse delay board due to use of discrete logic ICs and limited space on 6U sized VME boards. 5. Non-availability of space on board for implementation of readback logic of all channel count value. 6. Prone to noise because of FRC routing between coarse and fine delay boards.
LE0 Latch signals for fine delay lines
LE4
16-bit latches
1.
Fully customized VME board is designed for coarse and fine delay generation. Features of the board are listed below:
Figure 1: FPGA based delay generator board at I-2 timing control system. 2.
Reconfiguration: logic on FPGA is re-configurable through JTAG port given on board. 3. Clock option: board is provided with the option to use with any one of 1) on-board clock, 2) Indus-2 RF clock, 3) Booster RF clock selectable through jumpers All the three regulated voltages required for FPGA are derived on-board. Figure 1 shows the photograph of this new delay generator VME board installed at Indus-2 timing control system.
16-bit Comparators 16 O/P1
D0-D15 16
Ch#1
Ch#1 16
CS* DS0* DS1*
Channel address decode and read/ write logic
Ch#2
Ch#2
O/P2
16 O/P3 Ch#3
Ch#3 16
RD/WR*
O/P4 Ch#4
Ch#4 16 O/P5
Ch#5 4
Ch#5 16
Clock
Delay generator board: hardware & logic
LE2 LE3
A1-A4
XC3S50-4VQ100 FPGA (Spartan-3 family from Xilinx) based newly developed delay generator board helped to eliminate all these limitations.
LE1
16-bit Counter
Trig In
Figure2: Schematics of delay generation logic implemented in FPGA VHDL code is written to implement the digital logic. Address bus, Data bus and control signals from VME bus are interfaced to FPGA. CPU board writes new count value on specific channel address through VME bus. FPGA has five 16-bit latches to keep the delay counts of 5 channels. RD/WR*, CS*, DS0* and DS1* signals of VME are interfaced to FPGA for implementing VME write and read command from CPU board. Single 16-bit counter, which starts counting with rising edge of input trigger, and five 16-bit comparators are instantiated inside FPGA as shown in the figure 2. Only coarse delays are generated by FPGA and fine delays with 500 ps resolution are generated by DS102350 programmable delay line IC. This is an 8-bit programmable delay line IC with total range of 128 ns. Eight LSBs of VME data lines are interfaced to these 5 ICs and their LE (latch enable) signal to write data are generated by FPGA. This way FPGA decodes 10 addresses from address lines of VME, five for coarse and five for fine delays. Effective number of channels is five because for every channel both coarse and fine adjustments are needed. XC3S50-4VQ100 (FPGA ) device from Xilinx Inc. was selected to implement the hardware logic. Master serial mode is used to program platform flash, XCF01S from Xilinx Inc, which keeps the configuration data. FPGA gets configuration data from this platform flash after power up or RESET. Xilinx ISE8.1 tool gives detailed FPGA implementation report along with device utilization summary (Table 1).
Figure 3a: Single bucket filling mode
Figure 3b: 3-Symmetrical bucket
Device utilization summary (Table 1) shows that there is enough scope to accommodate future enhancement & modification needs. Table 1: Device utilization summary Logic Utilization Number of occupied Slices Total Number 4 input LUTs Number of bonded IOBs Number of GCLKs
284 out of 768 36% 409 out of 1536 26% 38 out of 63 60% 4 out of 8 50%
TESTS & RESULTS Figures 3a, b and c show the three-bucket filling modes achieved successfully after the installation of FPGA based coincidence generator board. During each injection process two out of three bunches (separated by ~33 ns) from booster are injected, which occupy 1st and 17th buckets of Indus-2 as shown in figure 3 above. Figure 3c shows the result of multi bucket filling with start bucket: 1 and end bucket: 15, bucket numbers 17th to 31st are filled by second bunch associated with every injection.
Figure 3c: Multi bucket filling start bucker: 1 and end bucket: 15 delay generator board gave excellent improvement in channel-to-channel jitter as shown in figure 4. Jitters observed were of the order 1 ns.
CONCLUSION AND PERSPECTIVE Testing, debugging and future enhancements or modifications are always done with ease and better understanding in software as compared to be in hardware. FPGAs have provided this powerful feature of software implementation to hardware design. Previously, there were five 2-channel coarse and two 4channel fine delay generator boards in use, introduction of single 5-channel coarse-fine delay generator board reduced the total number boards to four now. In the present configuration, we have one 5-channel coarse-fine, two 2-channel coarse and one 4-channel fine delay generator boards. Design for new board has already started which will replace rest three delay generator boards (two coarse and one fine).
REFERENCES [1] D. Angal-Kalinin and G. Singh, “Beam lifetimes and filling schemes for synchrotron radiation source Indus-2”, EPAC 2002, Paris, France, TUPLE049, p. 641 (2002); http://epaper.kek.jp/e02/PAPERS/TUPLE049.pdf. [2] A. A. Fakhri*, A.D. Ghodke & G. Singh, “Injection into Indus-2”, APAC 2004, Gyeongju, Korea, MOP15030, p. 146 (2004).
Figure 4: Channel-to-Channel jitter for delay generator board Digital logic for coarse delay generation is coded in VHDL language, so functional and timing simulation tests were done with Xilinx ISE8.1 and ModelSim5.8d tools. Lab and field-testing were also done extensively before finally deploying the two boards. Field-testing of
