Frequency Compensation for Multistage Amplifiers ... - IEEE Xplore

2 downloads 0 Views 346KB Size Report
and slew rate of the AFCB amplifier are also improved due to the much smaller compensation capacitors. Moreover, the presence of a left-half-plane zero in the ...
Frequency Compensation for Multistage Amplifiers Using Active-Feedback Current Buffers Zushu Yan, Qiang Bian, Yuanfu Zhao, Senior Member, IEEE and Suge Yue Beijing Microelectronics Technology Institute E-mail:[email protected]

Abstract-A frequency compensation scheme based on an active-feedback current buffer (AFCB) is presented in this paper. With an active-feedback mechanism, the proposed AFCB offers quite low input impedance across wide frequency spectrum, which greatly reduces the power consumption of AFCB amplifiers employing the AFCB as frequency compensation. The bandwidth and slew rate of the AFCB amplifier are also improved due to the much smaller compensation capacitors. Moreover, the presence of a left-half-plane zero in the AFCB amplifier enhances the stability and settling behavior of the amplifier. A three-stage AFCB amplifier is implemented by a standard 0.18-µm CMOS process. When driving a 120-pF capacitive load, the AFCB amplifier achieves over 100-dB dc gain, 8.5-MHz gain-bandwidth product (GBW), 65° phase margin, and 3.4-V/µs average slew rate with total 1.2-pF compensation capacitances, while only dissipating 88-µW power at a 1.5-V supply.

I.

INTRODUCTION

With the rapid scaling down of transistor sizes and supply voltages in advanced CMOS technologies, multistage amplifiers are becoming more and more essential since single-stage cascode or telescopic amplifiers are no longer suitable for lowvoltage applications. However, all multistage amplifiers suffer from the closed-loop stability problems due to the presence of multiple poles. Therefore, many frequency compensation topologies have been proposed [1]-[8]. The structure shown in Fig. 1(a) adopting a current buffer in series with a compensation capacitor is widely used in the frequency compensation of two-stage amplifiers as it is efficient for gain-bandwidth product (GBW) [9] and power sup- ply rejection ratio performance [10]. A novel active-feedback frequency compensation (AFFC) technique exploited by H. Lee et al. [5] tactfully deploys this structure to compensate multistage amplifiers. In contrast to other compensation topologies [1]-[4], the AFFC amplifier achieves high gain and wide bandwidth simultaneously. However, the current buffer in the AFFC amplifier consumes much more power to ensure stability of the amplifier and maximize the bandwidth. In order to further improve performance of the amplifier, an improved frequency compensation technique based on an active-feedback current buffer (AFCB) is proposed. Due to the rather low input impedance of the AFCB, the power consumption and compensation capacitances of the proposed AFCB amplifier are considerably reduced, while the GBW and largesignal performance are not compromised. In addition, the design equations are also simplified.

1-4244-0417-7/06/$20.00 ©2006 IEEE

VDD

VDD

IB1

IB2

VB2

VB1

M2

M1

VB4

M6

M5

Ca M4

zin

VB3

GND

M3

Ca zin

GND (a)

(b)

Fig. 1. (a) Simple current buffer. (b) Active-feedback current buffer.

II. THE PROPOSED AFCB The realization of a simple current buffer is shown in Fig.1 (a). The impedance zin seen from the source of M2 is roughly equal to the reciprocal of M2’s transconductance, which is not sufficiently small compared to an ideal current buffer with zero input impedance. To reduce the input impedance of the simple current buffer, we need to enlarge the transconductance of M2. However, increasing the small-signal transconductance by increasing the biasing current drastically increases its power consumption (transconductance scales proportional to the square root of biasing current). Therefore, alternate impedance reduction techniques should be explored. Fig.1 (b) modifies the basic topology using transistor M4 in feedback to decrease the input impedance of AFCB. The small-signal model of AFCB is shown in Fig. 2. Cp is extra lumped parasitic capacitance when the AFCB is used for frequency compensation. The input impedance zin of AFCB is shown by (1), at the bottom of the next page. During the derivation of (1), we have assumed some reasonable approximations. Specifically, C1, C2, C3>>Cgd5, C3 >>C2, Cdb4 (for large Cp) and gdsiC(1-2); 3) CL>> Ca, Cm. The transfer function is derived as

⎛ (gmf − gm2 )Cm ⎞ Adc ⎜⎜1 + s ⎟⎟ gm2 gm3 ⎝ ⎠ Av (s) = ( g g ) C − ⎞ ⎛ CC C s ⎞⎛ m2 m ⎜⎜1 + ⎟⎟⎜⎜1 + mf s + 1 m L s 2 ⎟⎟ gm2 gm3 gm2 gm3Ca ⎠ ⎝ p−3dB ⎠⎝

(2)

where Adc=gm1gm2gm3R1R2R3 is the dc gain, and P-3dB=1/(Ca gm2gm3 R1R2R3) is the dominant pole of the amplifier. Equation (2) shows that a LHP zero ZLHP is created in the amplifier, which increases the phase margin of the amplifier and the GBW is controlled by the size of Ca.

⎛ g ds 4 C3 + g m5 C gd 5 C (C + C db 4 ) 2 ⎞ g ds 4 ( g ds 5 + g ds 6 )⎜⎜1 + s+ 3 2 s ⎟ g ds 4 ( g ds 5 + g ds 6 ) g ds 4 ( g ds 5 + g ds 6 ) ⎟⎠ vt ⎝ (1) z in = = it ⎛ C3 ⎞⎛ g m 4 C 2 + g m5 C db 4 + g mb5 (C db 4 + C 2 ) (C1 + C 2 )C db 4 + C1C 2 2 ⎞ g m 4 g m5 g ds 6 ⎜⎜1 + s ⎟⎟⎜⎜1 + s+ s ⎟⎟ g m 4 g m5 g m 4 g m5 ⎝ g ds 6 ⎠⎝ ⎠

86

Feedforward stage VDD

1.6/0.4 Vb1 M10

Vi-

M11

gm1

5µA

M12

0.8/0.2 2.5µA

M17

Vi+

M18

2.5µA 2.5µA Vb2

0.8/0.2 2.5µA

0.8/0.4

M15

M21

0.8/0.4

gm2

M13

0.8/0.4

3.2/0.4 M31

M14

First stage

M23

0.4/0.4

Cm =

4 g m1C1C L g mf − g m 2

(3)

g m 2 g m3 Ca 2 g m1 ( g mf − g m 2 )

(4)

In the AFFC amplifier [5], gm1 is required to choose in the same order of magnitude as gm3 and gmf to stabilize the amplifier, which is the main limitation to further reduce the size of Ca. However, this limitation does not exist in the AFCB amplifier. Moreover, quite small gm2 is usually selected. Thus, much smaller Ca and Cm can be achieved by setting small gm1 and gm2 in the AFCB amplifier. In multistage amplifiers, most of the chip area will be occupied by the compensation capacitors, especially when driving large capacitive loads. Therefore, the AFCB amplifier can be made more compact than the AFFC amplifier. The GBW of the AFCB amplifier can be expressed as

GBW =

g m1 Ca

(5)

The GBW of the AFCB amplifier is not sacrificed as compared with that of the AFFC counterpart since gm1 and the size of Ca reduce simultaneously. By taking the LHP zero in (2) and the dimension conditions in (3)-(4) into consideration, the phase margin of the AFCB amplifier is written as

⎛ GBW PM ≈ 60° + arctan⎜⎜ ⎝ Z LHP

gm3

gma2

Ca 0.9pF 20µA

MA2 MB2

Vb3

0.8/0.2

0.4/0.4

Third stage

AFCB stage

Circuit diagram of a three-stage AFCB amplifier

B. Stability Criteria, GBW, and Phase Margin The stability of the AFCB topology is achieved by considering only the poles of the AFCB amplifier in unity-gain feedback configuration having a third order Butterworth frequency response [1], [4]. Then the dimension conditions of Ca and Cm are obtained as

Ca =

M24

Second stage

Fig. 5.

0.4/0.2

Cm 0.3pF

Vb3

GND

MA1

Vo

2.5µA

0.8/0.4 MB3

gma12.5µA

M32

M16 0.4/0.2

gmf

2.5µA MB1

6.4/0.4

2.5µA

Vb5

0.8/0.4

0.8/0.4 Vb4 M22

⎞ ⎟ ≈ 86.6° ⎟ ⎠

(6)

C. Slew Rate and Settling Time The slew rate of the AFCB amplifier with push-pull output stage is given by

⎛I I ⎞ SR = min⎜⎜ a , 2 ⎟⎟ ⎝ Ca Cm ⎠

(7)

where Ia and I2 represent biasing current in the AFCB stage and HGB stage, respectively. As the size of Ca and Cm is reduced, the slew rate of the AFCB amplifier is improved at fixed biasing current. Because the pole-zero doublet does not exist in the passband of the AFCB amplifier, the settling time solely depends on the phase margin. As indicated in (6), the phase margin of the AFCB amplifier is much larger than 60°. The AFCB amplifier can thereby settle within short time in the quasi-linear region. D. Low-Power Design Considerations The second stage transconductance gm2 can be set to a small value in the AFCB amplifier in order to have a larger bandwidth and reduce the size of Cm. Besides, the first stage gm1 can also be made smaller. Moreover, the AFCB achieves low input impedance under much less biasing current in contrast to the AFFC amplifier. Thus, the AFCB amplifier is more suitable for low-power designs. IV. CIRCUIT IMPLEMENTATION AND SIMULATION RESULTS The circuit implementation of a three-stage AFCB amplifier is illustrated in Fig. 5. In the AFCB amplifier, the first gain stage is a classical folded cascode OTA. It consists of transistors M11-M19, which ensure that the common mode input range can reach lower rail voltage. The second noninverting gain stage and the last stage are implemented by transistors M21-M24 and M31, respectively. The AFCB stage is composed of MA1 and MA2 while transistor M32 realizes the FTS. Transistors MB1, MB2 and MB3 are utilized to bias transistors MA1 and MA2. In order to verify the functionality of the proposed AFCB amplifier and reveal the availability of the AFCB block, both 1.5-V three-stage AFCB and AFFC amplifiers have been designed and simulated in a standard 0.18-µm CMOS process. For reasonable comparison, all the circuit parameters of the AFFC amplifier are chosen the same as the AFCB amplifier. To optimize the values of the compensation capacitors in the AFCB amplifier, Ca and Cm are fine tuned by virtue of previo-

87

55µm

Rbias Ca

Cm

64µm

Fig. 6. Frequency responses of AFFC and AFCB amplifiers

us analysis and the tradeoffs between the bandwidth and phase margin. For a 120-pF capacitive load, the optimized values of capacitors Ca and Cm are 0.9pF and 0.3pF, respectively. Fig. 6 demonstrates the simulated open-loop frequency responses of the AFCB and AFFC amplifiers with a 0.5 V input common-mode voltage. The AFCB amplifier achieves a GBW of 8.8 MHz with 65° phase margin, while the phase response of the AFFC amplifier greatly deteriorates because of a LHP zero existing before unity-gain bandwidth frequency. This LHP zero is created by the large input impedance of the simple current buffer and Ca in the AFFC amplifier. The transient responses of AFCB and AFFC amplifiers are simulated in unit-gain noninverting configuration with a 0.5-V step input. Fig. 7 illustrates these results. The slew rates of the AFCB amplifier are almost the same as the AFFC counterpart. However, it can be observed in Fig. 7 that significant oscillations occur in the step response of the AFFC amplifier owing to the limited phase margin. These oscillations indicate that the AFFC amplifier can not settle to the desired voltage. Instead, the AFCB amplifier has sufficient phase margin due to the LHP zero in (2). The AFCB amplifier can therefore settle within a short duration. There are overshoots for the up-going signal in AFCB and AFFC amplifiers, which is induced by the variance of operating points of the transistor in the circuit for the low voltage and high voltage [7]. The layout of the AFCB amplifier is shown in Fig. 8. The detailed post layout simulation results of the AFCB amplifier are summarized in Table I.

Fig. 7. Transient responses of AFFC and AFCB amplifiers

88

Fig. 8.

Layout of the AFCB amplifier

TABLE I POST LAYOUT SIMULATION RESULTS OF THE AFCB AMPLIFIER CL

120pF

Adc

>100dB

GBW

8.8MHz

Phase margin

65°

Power

88µW

Gain margin

12dB

Vdd

1.5V

Idd

58µA

SR +/-

2.84/3.96V/µs

TS +/- (to 1%)

0.45/0.21µs

V. CONCLUSION A multistage amplifier with an active-feedback current buffer compensation scheme is proposed. A three-stage AFCB amplifier is analyzed, designed and simulated in the paper. Both theoretical analysis and simulation results show that remarkable improvements of small-signal and large-signal performances have been accomplished in the designed low-power AFCB amplifier. REFERENCES [1]

R.G.H Eschauzier and J.H. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers. Boston, MA: Kluwer, 1995. [2] R.G.H Eschauzier, L.P.Kerklaan, and J.H. Huijsing,, “A 100-MHz 100dB operational amplifier with multipath nested Miller compensation structure,” IEEE J. Solid-State Circuits, vol. 27, pp. 1709-1717, Dec. 1992. [3] F. You, S.H.K. Embabi, and E. Sánchez-Sinencio, “Multistage amplifier topologies with nested Gm-C Compensation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2000-2011, Dec. 1997. [4] K.N. Neung, P.K.T. Mok, W.H. Ki, and J.K.O. Sin, “Three-stage large capacitive load amplifier with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol. 35, pp. 221-230, Feb. 2000 [5] H. Lee, and P.K.T. Mok, “Active-feedback frequency-compensation techniques for low-power multistage amplifiers,” IEEE J. Solid-State Circuits, vol. 38, pp. 511-520, Mar. 2003. [6] X. Peng and W. Sansen, “AC boosting compensation scheme for lowpower multistage amplifiers,” IEEE J. Solid-State Circuits, vol. 39, pp. 2074-2079, Nov. 2004. [7] X. Fan, C. Mishra, and E. Sánchez-Sinencio, “Single Miller capacitor frequency compensation techniques for low-power multistage amplifier,” IEEE J. Solid-State Circuits, vol. 40, pp. 584-592, Mar. 2005. [8] X. Peng and W. Sansen, “Transconductance with capacitances feedback compensation for multistage amplifiers,” IEEE J. Solid-State Circuits, vol. 40, pp. 1514-1520, July. 2005 [9] R. Read and G. Kovacs, “An unconditionally stable two-stage CMOS amplifier,” IEEE J. Solid-State Circuits, vol.30, pp. 591-594, May. 1995 [10] B. Ahuja, “An improved frequency compensation technique for CMOS operational amplifiers,” IEEE J. Solid-State Circuits, vol. 18, pp. 629633, Dec. 1983.