APPLIED PHYSICS LETTERS 97, 172106 共2010兲
Fully transparent InGaZnO thin film transistors using indium tin oxide/graphene multilayer as source/drain electrodes David Seo,1 Sanghun Jeon,2,a兲 Sunae Seo,2 Ihun Song,2 Changjung Kim,2 Sungho Park,2 James S. Harris,1 and U.-In Chung2 1
Solid State and Photonics Laboratory, Stanford University, Stanford, California 94305, USA Semiconductor Devices Laboratory, Samsung Advanced Institute of Technology (SAIT), Mt 14-1, Nongseo-ri, Kihung-up, Yongin-si, Kyungki-do 446-712, Republic of Korea
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共Received 1 April 2010; accepted 13 August 2010; published online 27 October 2010兲 Demonstration of a transparent InGaZnO thin film transistor using a graphene composite as the transparent source/drain electrode is presented. Graphene growth was confirmed by Raman spectroscopy, showing all associated peaks at 1350, 1580, and 2700 cm−1. The graphene composite showed a sheet resistance reduction of 15% while losing only 1.2% transparency when compared to the reference indium-tin oxide only electrode. Device characteristics of the composite device were on similar levels to those of the reference indium-tin oxide only device reaching a peak saturation mobility of nearly 30 cm2 v−1 s−1 indicating that graphene integration did not degrade InGaZnO transistor performance. © 2010 American Institute of Physics. 关doi:10.1063/1.3490245兴 As consumer electronic devices push toward lighter and more functional applications, several materials properties such as flexibility, transparency, low cost, and room temperature processing have been sought out.1,2 With the growth of display and imaging in the past few years such new materials are highly sought after. Currently indium tin oxide 共ITO兲 remains high cost due to excess in demand of indium. To address these concerns alternative transparent conducting oxides such as ZnO:Al 共Ref. 3兲 and SnO2 : F,4 have recently been researched extensively. Meanwhile several different materials such as carbon nanotubes,5 graphene,6 and organics,7 have also been studied for their possibility in transparent conductor applications. Due to its high optical transparency8 and relatively low sheet resistance,9,10 graphene may be an ideal candidate for transparent electrodes. Like the one-dimensional carbon nanotube, two-dimensional 共2D兲 graphene promises superb electrical, mechanical, and thermal characteristics,11 however there is no need for separation or alignment.12,13 Through recent breakthroughs in graphene growth: methods such as chemical vapor deposition 共CVD兲,9,14 SiC decomposition15 and even a solution based method16 are available for fabrication of graphene films. Studies have shown that even low mobility graphene provide benefits for transparent electrodes in solar cells.10 Though several works have investigated the optical and electronic properties of graphene,8,17–20 only a few exists where it has been successfully integrated as part of a mature device structure. Here we report on a transparent InGaZnO 共IGZO兲 thin film transistor using CVD grown graphene as part of the source/drain electrode. By demonstrating the graphene integrated transparent thin film transistor 共TFT兲 we show that indium layer thickness can be reduced without sacrificing performance. We fabricated fully transparent TFT structures on glass using mostly standard semiconductor processes in a 150 mm facility. We defined an ITO gate by depositing ITO on glass followed by photolithography and dry etching. Next a 1000 a兲
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Å SiO2 gate oxide is deposited and the IGZO active layer is deposited and patterned. The source-drain composite electrodes are then formed by first depositing a 50 nm layer of ITO, then transferring our CVD grown graphene film using techniques similar to other reports.9 A final ITO layer of 50 nm is deposited above the graphene layer to complete the composite electrode material. Photolithography and dry etching were used to define the source-drain regions. A cross sectional view of the TFT structure is shown in Fig. 1共a兲. Transfer and output characterization of a-IGZO TFT were carried out on a probe station using a Keithely 4200 measurement system. The threshold voltage, VT, was defined at the gate voltage which induced a drain current of W / L ⫻ 10 nA at a VDS of 1.1 V. The saturation mobility, sat, is extracted from postpinch-off data. Thus problems associated with contact and other series resistance effects can be minimized. An estimate of sat is obtained from the slope of the straight line section of an IDS0.5 versus 共VGS−VT兲 curve and the following equation:
sat =
2共IDS0.5/VGS − VT兲2 , W · Cg L
where W and L are the channel width and length, and Cg is the dielectric capacitance. For transparency and sheet resistance measurements we fabricated two additional samples: a 50 nm ITO with graphene film and a reference 50 nm ITO only film. A UVvisible spectrophotometer was utilized in measuring optical transmittance. Additionally, Raman spectroscopy of just the graphene layer was performed with a Renishaw’s MicroRaman System with laser wavelength of 514 nm on an identically prepared CVD graphene sample transferred onto SiO2 substrate. Graphene transfer is achieved through a multistep process in order to protect the graphene film. We begin by spin coating a polymethyl methacrylate 共PMMA兲 sacrificial/ protective layer. Next a thick adhesive layer is applied to
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FIG. 2. 共Color online兲 共a兲 The transfer curves of fully integrated graphene TFT with a gate length of 20 m and width of 30 m. The left y-axis is shown on a log-linear plot, while the right axis shows a linear-linear plot to better observe performance above threshold. 共b兲 The output curves of fully integrated graphene TFT with a gate length of 20 m and width of 30 m. FIG. 1. 共Color online兲 共a兲 Cross-sectional schematic of thin film transistor with ITO/graphene/ITO source/drain electrodes. 共b兲 Before removal of the Poly共PMMA兲 protective layer, and 共c兲 after removal of the PMMA layer in acetone, the photo image of fully transparent amorphous oxide thin film transistor utilizing a-IGZO semiconductor, ITO/graphene/ITO contact, and corning glass substrate. 共d兲 Raman spectroscopy data of CVD grown graphene transferred onto SiO2. Each line represents a different spot on the wafer, there are a total of five black lines from near the center and five red lines from wafer edges 共top left, top right, bottom, left, and right兲.
maintain graphene film in the absence of a rigid substrate. We etch the substrate away and are left with a free standing graphene-PMMA-adhesive film which is attached to a target substrate. The adhesive layer is removed prior to the sacrificial layer which is removed last and protects the graphene. The transfer of graphene is shown in Fig. 1共b兲 before removal of the PMMA protective layer, and in Fig. 1共c兲 after removal of the PMMA layer. The images in Fig. 1共b兲 shows the PMMA layer to be intact after removal of the adhesive layer, so we assume that the graphene between the substrate and PMMA layers remains intact. Raman shift spectra of the sample transferred onto SiO2 is shown in Fig. 1共d兲. We can identify three peaks associated with graphene. The D peak at 1350 cm−1 is associated with disorder.21 The G peak at 1580 cm−1 shows the E2g vibration modes, while the 2D peak demonstrates the abundance of hexagonal ring A1g breathing modes.21 Black lines are from five random points taken near the center of the 150 mm wafer, while red lines are from five random points taken near the edges. The relative intensity between the 2D and G peaks was about 1.8 and the 2D peak has a full width at half maximum of ⬃55 cm−1 establishing the growth and transfer of graphene as reported by others.22 Back to the integrated device, the transfer and output device characteristics for the TFT with a gate length of
20 m and width of 30 m are shown in Fig. 2. In Fig. 2共a兲, we measured the drain source current as a function gate voltage at varying source drain voltages. The threshold voltage was ⫺0.6 V and the subthreshold swing was 187 mv/ dec. The source drain current was measured with respect to source drain voltage with VGS − VTH from 0 to 15 V in 1 V increments. The saturation mobility reached a peak of nearly 30 cm2 / v s for VDS = 15 V and VG − VTH = 11 V. In addition, as shown in Fig. 2共b兲, a clear pinch-off and draincurrent saturation indicates that the electron transportation in active channels is controlled by the gate and drain voltages. This shows that graphene integration did not impact device performance, and the mobility values are in the range of well performing a-IGZO TFTs.23 For transparency and sheet resistance measurements we deposited 50 nm of ITO on glass, and transferred graphene as above. Measurement of sheet resistance across 25 points on the wafer as shown in Fig. 3共a兲 were performed using 4 point probe on the graphene-ITO共50 nm兲 wafer and compared to a reference 50 nm ITO wafer. Despite the relatively large disorder in graphene as indicated by the Raman spectrum, we were able to achieve a 15% decrease in the sheet resistance from ⬃600 ⍀ / sq for the reference samples to ⬃450 ⍀ / sq for the graphene-ITO共50 nm兲 wafers. Finally, we measured the transparency of a reference glass wafer, ITO on glass wafer, and graphene-ITO共50 nm兲 on glass wafer to determine the loss in transparency due to the graphene layer. As demonstrated in Fig. 3共b兲, the majority of transmittance is lost due to ITO. At the center of the visible spectrum of 550 nm, the graphene layer decreases transmittance by only 1.2%. We attribute the decrease in sheet resistance to be from the graphene layer which was measured by atomic force microscopy to be approximately 7–8 nm by rms. It would im-
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FIG. 3. 共Color online兲 共a兲 The sheet resistance data across 25 points on the wafer using 4 point probe on the graphene-ITO共50nm兲 wafer and a reference 50 nm ITA wafer. 共b兲 The optical transparency of a reference glass wafer, ITO on glass wafer, and graphene-ITO共50nm兲 on glass.
ply that the in-plane resistivity of the graphene layer was approximately 1.4– 1.6⫻ 10−3 ⍀ cm, the value is larger than those reported by other groups.9,10 There are several factors which we must consider for the integrated graphene. First is that our graphene layer is composed of a mixture of thicker graphite islands in a thin graphene matrix which reduces resistance while maintaining transparency. Next is that a similar mechanism as reported by thin silver layers between ITO plays a role here as well with surface plasmons.24 Finally, the nature of the contact between the ITO layer and graphene layer should be considered. We have demonstrated a fully transparent TFT with graphene integrated as transparent source/drain electrodes without loss of performance. The minor decrease in transpar-
