GaN HEMT Power

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We report the simulation of the large-signal performance of mm-wave FET power amplifiers obtained for the first time through Full Band Monte Carlo ...

Large-signal mm-wave InAlN/GaN HEMT Power Amplifier Characterization through Self-consistent Harmonic Balance / Cellular Monte Carlo Device Simulation D. Guerra, F. A. Marino†, D. K. Ferry, S. M. Goodnick, M. Saraniti , and R. Soligo Center for Computational Nanoscience, Arizona State University, 551 E Tyler Mall, Tempe, AZ, 85287, USA † also with: Department of Information Engineering, via Gradenigo 6/B, 35131, Padova, Italy Tel: +1 480 9652650, Fax: +1 480 9653837, Email: [email protected] Abstract

Harmonic Balance / Cellular Monte Carlo Self-consistently coupled Circuit-Device Simulations

We report the simulation of the large-signal performance of mm-wave FET power amplifiers obtained for the first time through Full Band Monte Carlo particle-based device simulation self-consistently coupled with a Harmonic Balance (HB) frequency domain circuit solver. Due to the iterative nature of the HB algorithm, this FET simulation approach is possible only due to the computational efficiency of our Cellular Monte Carlo (CMC), which uses pre-computed scattering tables. On the other hand, a frequency domain circuit solver such as HB allows the simulation of the steady-state behavior of an external passive reactive network without the need for simulating long transient time (i.e. RC, L/C time constants) typical of time domain solutions. By exploiting this newly developed self-consistent CMC/HB code, we were able to time-efficiently characterize the mm-wave power performance of a state-of-the-art 30-nm gate-length InAlN/GaN HEMT. Introduction Small-signal AC analysis fails to analytically predict large-signal device performance, which must be assessed by simulating the device within the full range of actual operating conditions. Thus, the power amplifier high-Q (i.e. highly selective in frequency) matching network must be included in order to properly simulate the dynamic load-line seen at the device output. A time domain solution of these matching networks including large reactive elements implies long transient times. However, this issue can be overcome by connecting a sinusoidal voltage generator, tuned at the fundamental frequency, at the device output [1] (i.e. an active load-line). This emulates the load-line drain voltage swing at the fundamental harmonic, and presents a short-circuit at the other harmonics, effectively emulating a high-Q matching network as shown in Fig.1. The actual synthesized load impedance is determined in post-processing through Fourier transform. The magnitude and phase of the complex load can be also adjusted, by changing magnitude and phase of the voltage generator, and the simulation and the subsequent impedance analysis can be iterated until the desired load impedance is obtained. In such way, we can emulate a constant load for different input powers, and characterize a device under large-signal operations as shown in Fig. 2, 3, and 4.

978-1-4577-0505-2/11/$26.00 ©2011 IEEE

The iterative procedure described in the previous paragraph is a particular one-harmonic case of the general frequency-domain circuit solver known as Harmonic Balance (HB) [2]. An automated version of the described procedure has been implemented, self-consistently coupled with our Cellular Monte Carlo (CMC) [3] device simulator, and extended to a variable number of harmonics allowing us to emulate any kind of impedance and network connected to any of the device contact as shown in the example in Fig.5, 6, and 7. In this figure, a Finite Difference Time Domain (FDTD) solver was also developed and self-consistently coupled to the CMC in order to compare this time-domain circuit solution with the frequency-domain circuit solution of HB. Unlike previously MC codes only coupled with time-domain circuit solvers used for FET power analysis [4], our CMC/HB simulator allows a time-efficient simulation of devices connected to high-Q matching networks (required to suppress undesired harmonics generated due to non-linearity) typical of mm-wave band power amplifier classes such as -AB, -B, -F, and hard-driven Class-A. In general, the frequency domain circuit solution provided by HB allows including the effect of those passive structures that are more easily characterized in the frequency domain than in the time domain. For instance, the HB algorithm can include the effect of a transmission line by using the S-parameters characterization, which still holds even under large-signal operations for a passive and bias independent structure with a linear response. InAlN/GaN HEMT Power Amplifier Characterization Using this approach, we characterized the RF power performance of a state-of-the-art InAlN/GaN HEMT recently reported by Lee et al [5]. We first performed a fit of the experimental DC characteristics as show in Fig.8. Then, the RF small-signal performance were obtained through CMC/AC simulations (by applying small step perturbations to extract the Y-parameters), and the agreement with the experimental fT is shown in Fig.9. This device has a relatively low experimental fMAX value of 13 GHz due to the high gate resistance, RG, of the rectangular gate. On the other hand, Lee et al. also reported that a mushroom-shaped gate structures or multifinger devices with rectangular gates can significantly improve this fMAX value. The effect of RG cannot be directly taken into account

34.2.1

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by the solely Monte Carlo device simulator. However, RG, modeled as a lumped series resistor, can be included in our characterization by using different techniques. In particular, small-signal analysis allows to analytically embedding in post-processing the impact of RG in the small-signal two-port network characterization of the device through the Y-parameters. The impact of RG on fMAX can be seen in Fig. 9. On other hand, the HB and/or the FDTD solver, self-consistently coupled with the CMC, allows including the effect of RG under large-signal operations, where an analytical parameterization is not available, through self-consistently coupled circuit-device simulations. Thus, in our simulated characterization we used different values of gate resistance, simulating in such way what the performance of this device would be if a low resistance gate structure were used. In general, parasitic elements can be simulated in the time-domain due to the fact that the reactive values are in general small, resulting in small transient time. Therefore, an iterative circuit solver such as HB is not essential in this case. The large-signal RF characterization was performed in the Ka-band with a 35 GHz single-tone continuous-wave with the device biased for Class-A operations, and a 50 load was emulated as example. The actual load that maximizes the output power can be obtained from experimental load-pull measurements as well as by computational load-pull that can be readily obtained through the active load-line technique [1]. Finally, we proceeded with the CMC/HB simulations including some real device issues such as parasitic elements (gate resistance, Fig.10), and material defects/reliability such as threading dislocations (Fig.11) and surface traps (Fig.12). The gate resistance was included by combining the HB and the FDTD circuit solvers. HB time-efficiently took into account the effect of the high-Q output matching network and load-line, while FDTD simulated the impact of RG. The surface traps were modeled by using a sheet of negative charge depleting the 2DEG. This approach cannot take into account the time-varying trapping/de-trapping process, but corresponds to the worst-case where all the traps are filled with electrons.

References [1]. O. Bengtsson, L. Vestling, and J. Olsson, “A computational load-pull method with harmonic loading for high-efficiency investigations,” Solid-State Electronics, vol. 53, no. 1, pp. 86 – 94, 2009. [2]. S. A. Maas, Nonlinear Microwave and RF Circuits, 2nd ed. Norwood, MA: Artech House, 2003. [3]. M. Saraniti and S. Goodnick, “Hybrid full-band Cellular Automaton/Monte Carlo approach for fast simulation of charge transport in semiconductors,” IEEE Transactions on Electron Devices, vol. 47, no. 10, pp. 1909–1915, October 2000. [4]. H. I. Fujishiro, S. Narita, and Y. Tomita, “Large signal analysis of AlGaN/GaNHEMT amplifier by coupled physical device-circuit simulation,” Physica Status Solidi (a), vol. 203, no. 7, pp. 1866 – 1871, 2006. [5]. D. S. Lee, J. Chung, H. Wang, X. Gao, S. Guo, P. Fay, and T. Palacios, “245-GHz InAlN/GaN HEMTs with oxygen plasma treatment,” IEEE Electron Device Letters, vol. 32, no. 6, pp. 755–757, June 2011.

Conclusions

VDD

Class-B

vD = VDD + vd vTH

id: f1, f2, f4, ...

freq

vL: f1 ZL’

= vd: f1

vG: f1 ZL’

VDD

+ _

Figure 1: Example of a Class-B amplifier (i.e. conducting only for half of the input cycle) with high-Q matching network emulated by an active load-line technique. f = 25 GHz Class-B

drain current [mA/mm]

ZL'= 50 Ω

3500

POUT=6.1 W/mm

3000

POUT=5.6 W/mm POUT=4.7 W/mm

2500

POUT=3.2 W/mm

2000

POUT=1.7 W/mm

1500 1000

POUT=0.6 W/mm

500 0

Acknowledgment

0

Work supported as part of the Air Force Research Laboratory (AFRL) National High Reliability Electronics Virtual Center (HiREV) under Wyle Laboratory Contract #DD-8192 (Monitor: S. Tetlak).

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ZL

High-Q Matching Network

DC BIAS: Vg= -6 V, Vd=18 V

In summary, we demonstrated that the self-consistent combination of a frequency domain circuit solver such as Harmonic Balance with the Full Band Cellular Monte Carlo device simulator allowed us to successfully perform for the first time the large-signal RF characterization of high-Q matched power amplifiers by using a particle-based device simulator. The same set of simulations with time-domain and/or conventional Monte Carlo (MC) (Fig.13) techniques would have required a prohibitive simulation time.

id: f1

vG: f1

vD = VDD + vd

vTH

f1 f2 f3 f4 f5

S11

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10

20

30

40

time [ps]

50

60

70

Figure 2: Resulting simulated drain current wave-forms obtained for a Class-B power amplifier by performing an input power sweep with constant emulated load impedance.

2500

f = 25 GHz Class-A

DC BIAS: Vg= -2 V, Vd=18 V

Pout [dBm], Gain [dB]

2000

1500

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0

5

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drain voltage [V]

25

vG

i : f , f , f , ... = v : f , f , f , ...

GND

S

1

2

S

1

2

20 15

GND

iS: f1, f2, f3, ... vS: f1, f2, f3, ... f1

3

f2

LS

10

5

5 5

10

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20

0

25

CMC current HB current

Class-B

0.05

vG

3

15

Gain

10

Pin [dBm] Figure 4: Typical large-signal figures of merit of the power performance of the test device of Fig.3 obtained through CMC/HB. vD 0.1

iD f1

25

20

0

Figure 3: Example of the CMC/HB simulated dynamic load-lines of an AlGaN/GaN HEMT test device biased as Class-A power amplifier with increasing input power. vD

f1

30

PAE

P1dB

25

30

iD

out

-1dB

source current [A]

0

30

0 0

source voltage [V]

drain current [mA/mm]

35

[6].

IdVd: Vg = -6.0 : 0.5 : 1.0 V WG = 100 um

f = 25 GHz Class-A 40 WG = 100 um 35 P

ZL'= 100 - j20 Ω

PAE [%]

DC BIAS: Vg= -2 V, Vd=18 V ZL'= 100 - j20 Ω

20

0.1

60

80

60

80

FDTD/CMC voltage HB/CMC voltage

0.05

f3

40

time [ps]

0

-0.05 0

20

40

time [ps]

HB: 3 harmonics HB current HB harmonics

Class-B

0

0.1

20

40

time [ps]

60

0.05 0 -0.05 20

40

time [ps]

60

Figure 6: Sinusoidal waveforms of the first three harmonics generated by the Harmonic Balance algorithm.

Class-B

0.05 0.04

0.03

0.03

0.02

0.02

0.01

0.01 0

50

100 frequency [GHz]

150

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0

80

ZS (0, 50, 100, 150 GHz ) = 0, 1, 2, 3 Ω

0.04

0

80

HB voltage HB harmonics

0

f = 50 GHz, LS = 1 pH

0.05

0.05

0

source voltage [V]

f = 50 GHz, LS = 1 pH

|current [A]|

0.1

|voltage [V]|

source current [A]

Figure 5: Example of the general HB algorithm: the source inductor is emulated by generating the voltage sinusoids at each harmonic. A Finite-Difference Time-Domain (FDTD) circuit solver also self-consistently coupled with the CMC is used for comparison. The FDTD solver uses a moving average filter that reduces the noise but adds a phase delay in the solution.

0

50

100 frequency [GHz]

150

0

Figure 7: Harmonic content of the analyzed source current, and of the voltage waveform generated by the Harmonic Balance algorithm. 34.2.3

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SOURCE

635 nm 30 nm

2000

635 nm

GATE

Al2O3 In0.17Al0.83N AlN

10 nm 4.5 nm 1 nm

20

CMC simulations Experimental

DRAIN

2500

fmax= 25, 52, 97, 143, 192 GHz

UPG

GaN

300 nm

SELF-HEATING

Gain [dB]

1500

1000

fT=268GHz

10

5

500

Increasing RG:

0

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2

3

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6

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8

9

40, 70, 150, 500, 2K Ω 0 0 1 10 10

10

drain voltage [ V ]

Figure 8: Layout of the InAlN/GaN HEMT simulation domain and agreement between the DC simulated (without thermal correction) and experimental results [5]. DC BIAS: Vg= -2 V, Vd=15 V WG = 100 um ZL'= 50 Ω

f = 35 GHz Class-A 30

RG=0, 40, 70 Ω

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15 increasing RG

Gain

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Pout [dBm], Gain [dB]

increasing RG

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increasing RG

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-

160 ps of simulated time 4 sine periods at 25 GHz = one HB iteration 50000 -15 particles 2.5x10-16s Poisson step 2.0x10 s Free Flight

100

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CMC 0

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Field Plate Length [nm]

Pin [dBm] Figure 12: Effects of surface traps on the Class-A RF power amplifier performance of the device. The traps were located in the gate-drain region (GD) and in both the source-gate and gate-drain regions (SG&GD) IEDM11-796

Gain

5

5 5

15

increasing NDIS

10

25

CPU time [hours]

20

20

MC PAE [%]

Pout [dBm], Gain [dB]

PAE

no, GD, SG&GD

25

PAE

increasing NDIS

200

Pout

25

Pout

Figure 11: Effects of threading dislocations on the Class-A RF power amplifier performance of the device.

f = 35 GHz Class-A 30

NT=3x10-12 cm-2

15

NDIS=1, 50, 150,300,500 x109 cm

Pin [dBm]

Figure 10: Effects of the gate resistance on the Class-A RF power amplifier performance of the device. DC BIAS: Vg= -2 V, Vd=15 V WG = 100 um Z L'= 50 Ω

f = 35 GHz Class-A 30 -3

25

0

25

Pin [dBm]

30

DC BIAS: Vg= -2 V, Vd=15 V WG = 100 um Z L'= 50 Ω

Pout

25

2

Figure 9: AC small-signal Monte Carlo simulations. The experimental fT is 245 GHz [5]. RG was analytically embedded in the Y-parameters by post-processing.

PAE [%]

Pout [dBm], Gain [dB]

30

10

Frequency [GHz]

PAE [%]

0

|h21|

15

2DEG

Figure 13: MC and CMC simulation time (1HB iteration) vs increasing field plate length (i.e. decreasing peak electric field, peak scattering, and number of scattering events to mange). HB average number of iterations is 4. 34.2.4