GaN HEMT processing on 200 mm

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Jun 7, 2012 - Abstract— Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates using a typical CMOS tool set.

Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs 3-7 June 2012 - Bruges, Belgium

Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates B. De Jaeger, M. Van Hove, D. Wellekens, X. Kang, H. Liang, G. Mannaert, K. Geens, S. Decoutere imec, Kapeldreef 75, 3001 Leuven, Belgium [email protected] buffer stack of 400 nm Al0.75Ga0.25N, 400 nm Al0.50Ga0.50N and 1800 nm Al0.25Ga0.75N, a 150 nm GaN channel and a 10 nm Al0.25Ga0.75N barrier layer. The barrier is capped with a ~2nm GaN capping layer, to protect the AlGaN barrier from cracking during the cool down after epitaxial growth. On the GaN epilayer, a 120 nm low pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer is deposited at 750°C. This structure results in reproducible and uniform two-dimensional electron gas (2DEG) characteristics over the 200 mm wafers. The 2DEG sheet resistance (Rsh) measured on Van-der-Pauw structures on 18 wafers with identical epilayer stack is 360 Ω/sq, with a 1σ standard deviation of 5% (24 of 48 dies measured over the wafers), see figure 1. Hall data show a 2DEG carrier density nS of ~ 8.9e12 cm-2 and a carrier mobility µS of ~ 1950 cm2V-1s-1.

Abstract— Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates using a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc.. An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator, and yielded fully functional power devices. 200 mm, GaN-on-Si, CMOS-compatible, Au-free, AlGaN/GaN HEMT, e-mode

I.

INTRODUCTION

GaN HEMT (high electron mobility transistor) technology offers perspectives for power device performance beyond the Si limitations. However, these devices are today fabricated on small diameter wafers, and often on sapphire or SiC substrates. Although the high switching speed of these devices can realize a cost reduction at the system level by reducing the size and hence the cost of the passives, the high cost of the component itself remains a limitation. To reduce the fabrication cost of GaN power devices, the authors believe that such process should run on 200 mm silicon wafers, and in a highproductivity CMOS fab.

450

R 300

The latter requires that the process is Au-free, and that the flow and substrates are compatible with the typical CMOS tool set and contamination status. This paper will discuss how the challenges of processing a Au-free CMOS-compatible AlGaN/GaN HEMT on 200 mm Si wafers have been addressed, with respect to the AlGaN/GaN epitaxy, the processing in typical CMOS tools of thick 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, the evolution of the wafer bow throughout the process, etc.. An enhancement mode (e-mode) AlGaN/GaN metal-insulatorsemiconductor HEMT (MISHEMT) process based on barrier recess is used as demonstrator, and yielded fully functional power devices. II.

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18

250

Figure 1. Reproducibility and uniformity of AlGaN/GaN 2DEG sheet resistance for 18 epilayers grown on 200 mm Si substrates

B. GaN-on-Si wafer handling on CMOS tool set 1.15 mm thick Si wafers are used instead of the commonly used 0.725 mm thick Si wafers. On the one hand, the thickness of 1.15 mm results in acceptable wafer bow ( 4 Ω⋅mm without barrier recess.

A. E-mode MISHEMT demonstrator device architecture The chosen device architecture for the demonstrator devices is an e-mode MISHEMT with barrier recess and gate dielectric. E-mode operation is obtained by sufficiently recessing the AlGaN barrier in the gate areas, thereby locally reducing the polarization charge [6]. To recess the Al0.25Ga0.75N barrier, a BCl3 plasma at low bias power is used. Figure 4 shows the threshold voltages (Vth), extracted with the maximum transconductance method for BCl3 barrier recess etch times of 0, 30 and 60 s, corresponding to barrier recess depths of ~ 0, 5 and 10 nm respectively [3]. Positive Vth values of 1.0 V ± 0.2 V are measured over the full 200 mm wafer for the longest BCl3 barrier recess etch time. Gate leakage current of power devices can be effectively suppressed by creating a MISHEMT structure, where a gate dielectric is inserted between the metal gate electrode and the AlGaN barrier to avoid the creation of a Schottky gate contact. The choice of the gate dielectric is however critical to obtain devices with both low gate leakage current and high breakdown voltage. In figure 5, breakdown characteristics of GaN MISHEMT devices with different gate dielectrics are compared to buffer breakdown characteristics. With a single layer of 15nm atomic layer deposition (ALD) Al2O3,

Figure 2. Transmission Electron Microscope (TEM) pictures of ohmic areas with and without 2min BCl3/SF6 barrier recess etch

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gate area patterning including barrier recess, followed by gate dielectric deposition. The gate dielectric is annealed at 650°C for 1 min in forming gas (10% H2, 90% N2). The gate electrode is a TiN/Ti/Al/Ti/TiN stack, with TiN as the work function metal, and is patterned by RIE with a Cl2/BCl3/N2 plasma. After ohmic contact formation as described previously, the MISHEMT processing is finalized by Al and Cu interconnect metallization layers, encapsulated by a Si3N4 scratch protect layer.

breakdown values below the 600V target are measured. With a bilayer of 5nm 650°C LPCVD Si3N4 and 10nm ALD Al2O3, breakdown values higher than 600V, close to the buffer breakdown values, are obtained. The improved breakdown behavior is believed to be related to the higher-quality semiconductor / dielectric interface obtained with the Si3N4 / Al2O3 bilayer, as we have recently argued in [7].

TABLE I.

D

I (A/mm)

-2

10

-3

10

-4

10

-5

10

-6

10

-7

10

-8

10

-9

10

5/10nm Si N /Al O 3

15nm Al2O3

4

2

1. GaN epilayer growth

6. Gate electrode definition

2. Si3N4 passivation layer

7. Ohmic area patterning

3. N isolation implant

8. Ohmic metal definition

4. Gate area patterning

9. Ohmic anneal

5. Gate dielectric deposition

10. Metal interconnect levels

The fabricated power devices with 60 mm total gate width consist of 60 gate fingers of 1 mm each. The gate length LG is 1.5 µm, the gate-source distance LGS is 0.75 µm and the gatedrain distance LGD is 10 µm. A gate-connected field plate was formed by extending the gate metallization by 1 µm to the drain side. Figure 6 shows cross-section Scanning Electron Microscope (SEM) pictures of a power device. The top picture shows an overview of the source-gate-drain finger configuration, with the 8 µm thick source and drain Cu interconnects encapsulated by Si3N4. The bottom picture details the source-gate area. It shows the T-shaped metal gate electrode with the field plate, the gate dielectric, and the metallization stack in the ohmic source area.

Figure 4. Threshold voltage versus barrier recess etch time. Enhancement mode devices are obtained for 60 sec barrier recess. The inset figure shows the corresponding ID-VGS characteristics.

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OUTLINE OF THE GATE FIRST MISHEMT PROCESS FLOW

3

buffer

-10

0

200

400

V

DS

600

800

(V)

Figure 5. Breakdown characteristics of the GaN buffer and of the GaN MISHEMT devices with 200 µm gate width and different gate dielectrics.

B. E-mode MISHEMT demonstrator process description The MISHEMT process flow follows a Gate First approach as outlined in table 1. After GaN epilayer growth and deposition of the LPCVD Si3N4 passivation layer, device isolation is defined by a sequence of N implants. Temperatures in the subsequent processing are limited to  650°C, ensuring the integrity of the isolation. The processing continues with

Figure 6. Cross-section SEM pictures of a power device. The top picture shows an overview of the source-gate-drain finger configuration. The bottom picture details the source-gate area.

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C. Demonstration of the feasibility of AlGaN/GaN HEMT processing on 200 mm Si substrates Figure 7 shows photographs of a fully processed 200 mm GaN-on-Si MISHEMT device wafer. Figure 8 shows the layout and a microscope picture detail of a 60 mm gate width power device. Figure 9 shows the output characteristics of such a device. The maximum output current is 6 A at VGS = 8V and VDS = 10V, demonstrating the feasibility of AlGaN/GaN HEMT processing on 200 mm Si substrates.

7 V

GS

6

=8V

D

I (A)

5 4

6V

3 4V

2 1

2V 0V

0 0

5

V

DS

10

(V)

Figure 9. Pulsed ID-VDS output characteristics of a 60 mm gate width power device (pulsewidth 1 ms).

IV.

CONCLUSIONS

The feasibility of Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates in a highproductivity CMOS fab is demonstrated. Crack-free AlGaN/GaN/AlGaN double heterostructure epilayers have been grown on 200 mm diameter, 1.15 mm thick Si substrates. The GaN-on-Si wafers have been successfully processed on a typical CMOS tool set according to standard fab operation procedures. The Ga contamination is successfully controlled through existing contamination control procedures. Fully functional E-mode AlGaN/GaN MISHEMT power devices with 60mm gate width and 6 A maximum output current were demonstrated. We believe this work is an important milestone in the realization of cost-effective high performance GaN power devices, though further work is needed to compete with the more mature Si power technology. Figure 7. Photographs of a fully processed 200 mm GaN-on-Si MISHEMT device wafer. Top picture: full wafer. Bottom picture: detail.

References [1]

[2]

[3]

[4]

[5]

[6]

Figure 8. Layout (left) and microscope picture detail (right) of a 60 mm gate width power device.

[7]

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K. Cheng et al., “AlGaN/GaN/AlGaN Double Heterostructures Grown on 200 mm Silicon (111) Substrates with High Electron Mobility,” Appl. Phys. Express, Vol. 5, p. 011002 (2012). A. Malmros et al., “Electrical properties, microstructure, and thermal stability of Ta-based ohmic contacts annealed at low temperature for GaN HEMTs,” Semicond. Sci. Technol., Vol. 26, p. 075006 (2011). G. Mannaert et al., “Development of AlGaN recess etch for E-mode power HEMTs,” accepted for presentation at the Plasma Etch and Strip Strip in Microelectronics Workshop (PESM), Grenoble, France, 15-16 March, 2012. T. Imada et al., “Enhancement-Mode GaN MIS-HEMTs for Power Supplies,” in. Proc. of the International Power Electronics Conf. 2010, p. 1027. M. Kanamura et al., “Enhancement-Mode GaN MIS-HEMTs With nGaN/i-AlN/n-GaN Triple Cap Layer and High-k Gate Dielectrics”, IEEE Electron Device Lett., Vol. 31, No. 3, p. 189, March 2010. T. Oka et al., “AlGaN/GaN Recessed MIS-Gate HFET With HighThreshold-Voltage Normally-Off Operation for Power Electronics Applications,” IEEE Electron Device Lett., Vol. 29, No. 7, p. 668, July 2008. M. Van Hove et al., “CMOS Process-Compatible High-Power LowLeakage AlGaN/GaN MISHEMT on Silicon”, IEEE Electron Device Lett., Vol. 33, No. 04, April 2012 (in press).