Gate-All-Around Silicon Nanowire MOSFETs and Circuits J. W. Sleight, S. Bangsaruntip, A. Maj umdar, G. M. Cohen, Y. Zhang, S. U. Engelmann,
N. C. M. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. M. Frank, J. Chang, and M. Guillom IBM T. 1. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598 Phone: 914-945-1876; E-mail:
[email protected]
Abstract
We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaNlHf based gate stack, have high drive-current performance with NFETIPFET IosAT 825/950 f..lNf..lm (circumference-normalized) or 2592/2985 f..lA/f..lm (diameter-normalized) at supply voltage Voo I V and off-current IOFF 15 nNf..lm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits. =
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Introduction
Gate-length scaling of gate-all-around (GAA) MOSFET with sub-20 om gate length requires NW channels with diameters less than 10 om [I]. The fabrication of highly uniform, sub-100m, GAA Si nanowire (NW) MOSFETs is a key challenge in the use of these devices in a large scale technology. Fabricating NWs with current lithographic capabilities leads to large size variations, both in NW size (CD) and also in line edge roughness (LER), which is often a significant fraction of the required CD. We have previously reported a process using a combined maskless approach of hydrogen annealing and high-temperature oxidation to address this challenge [2]. MOSFETs with NW in the sub-IO om range were fabricated having tight CD control, facet-smooth sidewalls, and LER < 0.8 om (resolution limit). NW NIP-FETs show near-ideal sub-threshold slope characteristics, confirming the high surface quality of these NW channels. The GAA NW devices also exhibit strong drive currents and good short-channel control superior DIBL compared to scaled, thin planar SOl devices. Additionally, the excellent size control achieved enables us to reliably investigate diameter scaling of undoped, GAA NW channels; and we clearly observe the impact of the wire size on short-channel control. Fully functional robust CMOS ring oscillator circuits were also fabricated.
Device Fabrication
Conventional patterning techniques lead to substantial variation in NW sizes when the diameter is less than
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Fig. 1. The important role hydrogen annealing plays in LER reduction. Significant roughness remains when oxidation alone is used to reduce NW sizes (a). However, with the hydrogen anneal process incorporated, LER is reduced down to the level of our measurement limit (b). Left: SEMs; Right: corresponding edge-enhanced images and LER traces.
10 om, as required by future CMOS scaling. To reliably obtain highly uniform and smooth silicon NWs in a sub10 om range, we use sequential hydrogen annealing followed by high-temperature oxidation. The critical role of the H2 anneal process is demonstrated in Fig. I. NW size reduction by oxidation alone (Fig. la) shows much larger LER than the combined processes (Fig. Ib). While the NW channel diameter needs to be small, the source/drain (SID) extension regions must remain sufficiently thick to minimize series resistance and prevent silicide runaway [3]. To this end, we thickened the NW portions outside the gate by selective Si epitaxy [2]. Defect-free epitaxy on sub-IO om NW was performed without NW agglomeration by initiating growth at low temperature. Longer growth time merges adjacent NWs. This process was utilized to form bulk like SID regions outside the gate, similar to FinFET merging. GAA NW FET devices were fabricated, incorporating the techniques described above, through the first metal level. The key process steps are shown in Fig. 2, with accompanying structural images in Fig. 3. The gate stack utilized a Hf-based dielectric with a TaN metal capped with poly-Si. Inversion oxide thickness TINV was 1.7 om. A NiPt silicide was used.
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Figs. 4-9 detail the electrical characteristics of our undoped-body, GAA NW devices. Mid-gap metal gates lead to normally-off FETs with centered threshold voltage (Fig. 4a). The excellent wire size control of our process enables reliable investigation of size scaling in undoped, GAA channels. Dependence of short-channel effects on NW size is shown in Fig. 4. Scaling the body dimensions of NW FETs clearly improves short-channel control, as is expected for fully-depleted (FD) undoped body devices. Universal scaling behavior for GAA devices is demonstrated in Fig. 5a. When the effective channel length LEFF is normalized by the rectangular electrostatic scaling length A [4], DIBL as well as SSSAT data for all NW sizes collapse onto the same curve. This result is also consistent with the planar FDSOI data provided [5], confIrming the universality in scaling of NW devices. In addition, comparing short-channel effects of NW to planar FDSOI devices [5] with similar body dimension (Fig. 5b) shows that NW FETs provide -2.5-2.7 x LEFF scaling benefIt compared to planar FDSOI FETs. This is in fair agreement with 0.6
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