Gate Dielectrics - IEEE Xplore

JOURNAL OF DISPLAY TECHNOLOGY, VOL. 10, NO. 10, OCTOBER 2014

875

High Mobility Field-Effect Thin Film Transistor Using Room-Temperature High- Gate Dielectrics Hsiao-Hsuan Hsu, Chun-Yen Chang, Chun-Hu Cheng, Po-Chun Chen, Yu-Chien Chiu, Ping Chiou, and Chin-Pao Cheng

Abstract—This paper reports an InGaZnO thin-film transistor (TFT) that involves using fully room-temperature gate dielectrics on a flexible substrate. The wide bandgap dielectrics of HfO and Y O exhibited favorable adhesion properties on a flexible substrate compared with conventional low- SiO film. Based on the experimental results, the room-temperature IGZO/HfO TFTs demonstrated effective device integrity, and achieve a low 2 V, a low threshold voltage of 0.46 006 V, a drive voltage of low sub-threshold swing of 110 6 mV/decade and an extremely high mobility of 60.2 32 cm V s. The excellent performance of this TFT indicated that it demonstrates considerable potential for active-matrix liquid crystal display applications requiring low power consumption and a high driving current. Index Terms—Flexible, indium-gallium-zinc oxide (IGZO), thin-film transistor (TFT), room temperature.

I. INTRODUCTION

M

ETAL–OXIDE thin-film transistors (TFTs) have received substantial attention as potential substitutes for amorphous Si and/or polycrystalline Si in active-matrix liquid crystal displays, active-matrix organic light emitted diodes (AMOLEDs), and three-dimensional (3D) display applications [1]–[3]. One of the most promising candidates for the material in oxide semiconductor TFTs are indium-gallium-zinc oxide (IGZO) TFTs, which exhibit superior field-effect mobility in the range of 10–20 cm V s [4]–[10], favorable transparency to visible light [11], and a low process temperature ( 300 C [12]). In the past few years, certain groups have successfully demonstrated IGZO TFTs on flexible substrates at room temperature [9], [10], indicating that IGZO TFTs have a high potential for integration with light-weight, low cost, and Manuscript received October 23, 2013; revised March 02, 2014, June 09, 2014; accepted June 15, 2014. Date of publication June 17, 2014; date of current version September 22, 2014. This work was supported by the National Science Council (NSC) of Taiwan, Republic of China, under Contract NSC 102-2221-E003-019. H.-H. Hsu was with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan. She is now with Green Energy and Environment Research Laboratory, Industrial Technology Research Institute, Hsinchu, 31040, Taiwan C.-Y. Chang, P.-C. Chen, Y.-C. Chiu, and P. Chiou are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan. C.-P. Cheng and C.-H. Cheng are with the Department of Mechatronic Technology, National Taiwan Normal University, Taipei 10610, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures are available online at http:// ieeexplore.ieee.org. Digital Object Identifier 10.1109/JDT.2014.2331351

portable flat-panel or electronic products. However, without thermal annealing treatment after device fabrication, the electrical performance of IGZO TFTs on flexible substrates are characterized by a high operating voltage, low sub-threshold swing (SS), and low device mobility. These characteristics must be improved for IGZO TFTs on flexible substrates to be comparable with IGZO TFTs on Si substrates. Although highdielectrics for low-temperature TFT fabrication [4]–[10] were demonstrated to improve capacitance coupling, and thus reduces the operating voltage, low-mobility TFTs limit circuitry operating frequencies and corresponding response times [3] in AMOLED displays. Furthermore, few studies have investigated the adhesion capability between a flexible substrate and a gate stack, which is essential for bending stability. To address these concerns, a high performance IGZO TFTs that involve using fully room-temperature Y O and HfO gate dielectrics on a flexible substrate were fabricated in this study. The interface adhesion capability of the TFTs was also determined. High transistor performance with a low drive voltage of 2 V, a low sub-threshold swing of 110 6 mV/decade, and a high field-effect mobility of 60.2 3.2 cm V were simultaneously achieved using a fully room-temperature process. II. EXPERIMENTS TFT devices with a bottom-gate configuration were fabricated on 300-nm-thick insulating SiO grown on a flexible polycarbonate (PC) substrate. PC was chosen as the flexible substrate because it has a smoother surface than that of polyimide or polyethylene terephthalate, which is beneficial in reducing the leakage current [9], [10]. In this work, the film was deposited and patterned by metal shadow-mask process. A 35-nm-thick TaN was then deposited using sputtering and patterned as the bottom-gate electrode by using the 1st shadow mask. Subsequently, 6-nm-thick SiO , 65-nm-thick Y O and 60-nm-thick HfO gate dielectrics were deposited by e-gun evaporation with a process pressure of 1 10 torr at room temperature and patterned by using 2nd shadow mask. The Y O and HfO gate dielectrics have been proposed to have respectively high conduction band offsets of 2.39 eV and 2.63 eV in contact with the IGZO channel layer [13] High values offer the advantage of reducing gate leakage, particularly in low-temperature processes Next, 20-nm-thick IGZO film was sputtered and patterned by 3rd shadow mask as channel layer. The IGZO channel was deposited using a power of 70 W and a process pressure of 7.6 10 torr in argon ambient with 30% O . No substrate temperature was applied during sputtering. The composition ratio

1551-319X © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

876


of IGZO film was examined by Energy dispersive X-ray spectrometry (EDX). The cation ratio for In:Ga:Zn was 1:0.9:0.5. After depositing the gate stacks, 300-nm-thick Al was thermally evaporated in the active region to form the source and drain electrodes, which defined the channel size of 530 m 30 m by the fourth shadow mask. The TFT performance was characterized by current-electric field – and capacitance density-electric field – measurements conducted using an HP4156C semiconductor parameter analyzer and an HP4284A precision LCR meter, respectively. The interfacial adhesion ability between the PC substrate and the gate stacks was determined using a Hysitron Triboscope nanoindenter with a nanoscratch module. III. RESULTS AND DISCUSSION To investigate the influence of various gate dielectrics on contact with a TaN/PC substrate, a nanoscratch test was conducted by observing film delamination. Fig. 1(a) shows the scratch test results of the SiO gate dielectric on the TaN/PC substrate under a normal force of 800 N. The contact loading of the SiO /TaN/PC sample was observed to increase with the displacement. After the scratch loading was increased, the output loading exhibited an abrupt increase and a dramatic fluctuation close to a displacement of 40 nm, which was mainly ascribed to the poor adhesion ability between SiO and the TaN/PC substrate. Under mechanical stress, the accumulation of defects induced a film crack to release strain energy eventually causing delimitation. The friction coefficients calculated from the ratio of the scratch force to the normal load were obtained. Fig. 1(b) shows the friction coefficient as a function of the loading time. The friction force depends on the interfacial shear stress; therefore, the friction coefficient varied in the nanoscratch test of the SiO /TaN/PC sample. The accumulated scratch process was monitored in situ using an AFM tool as the applied load was increased, as shown as 2D and 3D images in Fig. 1(c) and (d). Surface morphologies, film buckling, and subsequent cracking along the scratch tracks may explain the fluctuation of the load–displacement and friction coefficient-time curves occurring at a low loading force of 400 N. Interface adhesion between the gate dielectric and the TaN/PC substrate is required for flexible bending or rolling. To evaluate interface adhesion, wide bandgap dielectrics of Y O and HfO were tested. Y O and HfO films were deposited using a room-temperature process. Fig. 2(a) and (b) shows the load–displacement and friction coefficient-time curves, respectively, of the nanoscratch of Y O /TaN/PC under the maximum normal load of 1000 N. The measured friction coefficient is approximately 0.14–0.15. In contrast with the poor adhesion of the SiO /TaN/PC sample, no obvious fluctuation was found in the loading test, implying that no sufficient accumulation of shear stress caused film delamination, as shown in the AFM images in Fig. 2(c) and (d). Although the scratch track along the loading force was uniform, a small pile-up region on the Y O surface was also observed, indicating strain hardness in the film stack after scratching. This surface pileup may exacerbate failure or fatigue from subsequent scratch processes. Fig. 3(a) and (b) shows the load–displacement and friction coefficient-time curves, respectively, from nanoscratch tests

Fig. 1. (a) Load–displacement curve. (b) Friction coefficient-time curve. (c) 2D image and (d) 3D image of SiO /TaN/PC under 800 N loading force.

of the HfO /TaN/PC sample under the maximum normal load of 1000 N. The friction coefficient was approximately 0.10–0.11. Fig. 3(c) and (d) shows 2D and 3D AFM images of the HfO /TaN/PC sample. Under a normal force of 1000 N, the HfO /TaN/PC film underwent elastic and then plastic transformation, and hence, a slight trace was detected without an apparent interface pile-up formation. This is because the

HSU et al.: HIGH MOBILITY TFT USING ROOM-TEMPERATURE DIELECTRICS

877

Fig. 2. (a) Load–displacement curve. (b) Friction coefficient-time curve. (c) 2D image and (d) 3D image of Y O /TaN/PC under 1000 N loading force.

Fig. 3. (a) Load–displacement curve. (b) Friction coefficient-time curve. (c) 2D image and (d) 3D image of HfO /TaN/PC under 1000 N loading force.

internal intrinsic stress originated from the growth method of the thin film and process parameters influence the surface and interface morphology [14], [15]. The existence of large internal stress possibly cause film rupture, adhesion loss, and the changes of physical and chemical properties of the films [14]. Thus, the unstable friction coefficient observed in SiO case is considered as the existence of large internal stress during

deposition. In contrast, a low intrinsic stress can reduce surface defect generation under dielectric deposition at room temperature, and thus obtain a desirable adhesive property. Therefore, using a room-temperature process revealed that the Y O and HfO exhibited adhesion properties that are superior to those of conventional low- SiO on TaN/PC substrates; this result must be further considered in flexible display applications.

878

Fig. 4. (a) Photograph and (b) schematic plot of flexible and transparent IGZO/ (HfO ,Y O TFTs on PC substrate.

A bottom-gated TFT that entails using room-temperature HfO and Y O dielectrics was also fabricated. To fabricate a room-temperature flexible TFT, transparent plastic PC was adopted as a flexible substrate. Fig. 4(a) and (b) shows a photograph and schematic plot, respectively, of flexible and transparent IGZO/(HfO or Y O ) TFT on a PC substrate. To verify the film quality of the room-temperature gate dielectrics, metal–insulator–metal (MIM) capacitors were simultaneously fabricated. The capacitance density-electric field – characteristics of the Al/HfO /TaN and Al/Y O /TaN MIM capacitors on a flexible PC substrate are shown in Fig. 5(a). The inset of Fig. 5(a) shows the schematic structure of the MIM capacitor. The capacitance density of the 60-nm-thick HfO gate dielectric, measured at 100 kHz was approximately 0.28 F/cm , which yielded a dielectric constant of 19 and a low capacitance equivalent thickness (CET) of 12.3 nm. By contrast, a thicker Y O dielectric exhibited a correspondingly lower capacitance density of 0.16 F/cm and a higher CET of 21.5 nm. This high gate capacitance density and low CET is essential for increasing the drive current and reducing the operating voltage. Fig. 5(b) shows the current density characteristics – of the two MIM capacitors. Although the top Al 4.1eV and bottom TaN eV electrodes were asymmetric, leakages at the positive and negative biases were nearly identical. Roomtemperature evaporated-gate dielectrics (HfO or Y O ) may leave defects near the interface of bottom TaN and create additional leakage paths when a positive bias is applied. Based on


Fig. 5. (a) capacitors.

–

and (b) –

curves of Al/HfO /TaN and Al/Y O /TaN MIM

the measured results, the leakage current of the HfO capacitor was 7.0 10 A/cm at MV/cm, which was slightly higher than that of the Y O capacitor. The low leakage current of the Y O capacitor can be attributed to its wider bandgap of 6.27 eV and of 2.63 eV. However, the much higher capacitance density (75% higher than that of the Y O dielectric) and low CET of room-temperature HfO confirmed its film quality, and verified that it is suitable for low-temperature flexible display applications. Fig. 6(a) and (b), respectively, depicts the output – and transfer – characteristics of the IGZO/Y O TFT. Regarding device performance, the TFT yielded an on/off current ratio of 1.6 10 , a threshold voltage of 0.84 V, a high SS of 187 mV/decade, and a high of 21 cm V s. The SS relevant to the interface state can be described using the following equation: , in which is the gate capacitance density, is the capacitance density from the charged interface traps at the IGZO/gate dielectric interface, is the depletion capacitance density of IGZO, is the elementary charge, is Boltzmann’s constant, and is the absolute temperature. was acquired from the Al/Y O /TaN MIM capacitor. Neglecting , the maximum number of interface states, , for the IGZO/Y O TFT was cm eV . High values of affect the device mobility and off current, and are unavoidable when using a fully room-temperature process. Fig. 7(a) and (b) shows the – and – characteristics, respectively, of the IGZO/HfO TFT. Compared with


879

Fig. 7. (a) Fig. 6. (a) devices.

and (b)

–

–

and (b)

–

characteristics of IGZO/HfO TFT devices.

characteristics of IGZO/Y O TFT

the IGZO/Y O TFT, the IGZO/HfO TFT exhibited a superior of 1.1 10 . This value was seven times higher than that of the IGZO/Y O TFT. The high gate capacitance of HfO facilitated gaining a high on-current, and increased the ratio. However, when the TFT turns off, the hole accumulation near source region can result in barrier height lowering and then increase off current. Accordingly, an overdrive negative gate bias (to increase source barrier height) and a large valence band offset between IGZO and gate dielectric are both necessary. Thus, the off-state current at a negative gate bias is also influenced by valence band offset , even though the for both HfO and Y O are far larger than 1 eV, which is enough to form high Schottky barrier height [16]. To achieve a low-power operation, the TFT must be biased at a low and . Therefore, improving the and is critical for large-area display applications. The low SS of 110 mV/decade extracted from the – curve of the IGZO/HfO TFT was much lower than the 187 mV/decade extracted from that of the IGZO/Y O TFT. The IGZO/HfO TFT also exhibited a low operating voltage of 2 V and a low drive voltage V, which are essential for low power applications. The extracted from the square of the – curve for the IGZO/HfO TFT, 0.46 V, was also lower than the 0.84 V extracted from that of

IGZO/Y O TFT, indicating that low gate swing contributed to the low value of . Most critically, the maximum number of interface states calculated for the IGZO/HfO TFT was 1.5 10 cm eV , which was lower than that for IGZO/Y O TFT, indicating superior interface quality between the HfO gate dielectric and -IGZO channel layer. Fig. 8(a) and (b) depicts the versus the gate voltage at V and V, respectively. The extremely high ( V) of 60 cm V s obtained using the IGZO/HfO TFT was three times higher than that obtained using the IGZO/Y O TFT, which is favorable for fabricating a high-resolution flexible display that satisfies the high performance requirements of high mobility and a high driving current. The extracted and for IGZO/HfO are 65.8 and 60.2 cm V s, respectively, whereas the and for IGZO/Y O TFT are 22.4 and 21.4 cm V s, respectively. The mobility variation is small (less than 10%), which indicates that field-effect mobility is independent on [17]. Besides, the S/D series resistance of IGZO TFT can be extracted by using gated-transmission line method (TLM), which involved plotting the total TFT on-resistance as a function of the channel length using the following equation [18]:

880


IV. CONCLUSION In comparison with conventional low- SiO gate dielectrics, the superior adhesion ability of room-temperature HfO dielectrics on a flexible PC substrate was determined using nanoscratch testing. A low SS of 110 6 mV/decade, a low of 0.46 0.06, a low of 2 V, and an extremely high of 60.2 3.2 cm V s were simultaneously achieved in a high-performance flexible IGZO/HfO TFT by using a fully room-temperature process. REFERENCES

Fig. 8. at (a)

–

characteristics of IGZO/HfO and IGZO/Y O TFT devices V and (b) V.

TABLE I COMPARISON OF FLEXIBLE TFTS WITH HFO AND Y O DIELECTRICS FABRICATED AT ROOM TEMPERATURE

where , , and are defined as channel width, the capacitance of the gate dielectric per unit area, and effective mobility, respectively. For IGZO/HfO TFT, the width-normalized is evaluated by fitting the linear curve and obtained from the intersection of y-axis, yielding 20 cm. Obviously, this value is smaller to the previous report of 34 cm [19], which indicates the good ohmic contact in the IGZO TFT processed at room temperature. Table I lists the performance levels of IGZO TFTs accompanied by HfO and Y O gate dielectrics. The standard deviations meaured from 20 devices for , SS, and are also shown here. Compared with the IGZO/Y O TFT, the IGZO/HfO TFT showed a higher of 1.1 10 , a smaller of 0.46 0.06, a lower SS of 110 6 mV/decade, and a substantially higher of 60.2 3.2 cm V s, under a low drive voltage of V.

[1] R. Fardel, M. Nagel, F. Nuesch, T. Lippert, and A. Wokaun, “Fabrication of organic light-emitting diode pixels by laser-assisted forward transfer,” Appl. Phys. Lett., vol. 91, p. 061103, Aug. 2007. [2] C. D. Muller, A. Falcou, N. Reckefuss, M. Rojahn, V. Wiederhirn, P. Ruati, H. Frohne, O. Nuyken, H. Becker, and K. Meerholz, “Multicolour organic light-emitting displays by solution processing,” Nature, vol. 421, no. 6925, pp. 829–833, Feb. 2003. [3] S. Ju, J. Li, J. Liu, P. C. Chen, Y. G. Ha, F. Ishikawa, H. Chang, C. Zhou, A. Facchetti, D. B. Janes, and T. J. Marks, “Tansparent active matrix organic light-emitting diode displays driven by nanowire transistor circuitry,” Nano. Lett., vol. 8, no. 4, pp. 997–1004, Dec. 2007. [4] C. D. Dimitrakopoulos, S. Purushothaman, J. Kymissis, A. Callegari, and J. M. Shaw, “Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators,” Science, vol. 283, no. 5403, pp. 822–824, Feb. 1999. [5] P. Barquinha, A. M. Vila, G. Goncalves, L. Pereira, R. Martins, J. R. Morante, and E. Fortunato, “Gallium-indium-zinc-oxide-based thin-film transistors: influence of the source/drain material,” IEEE Trans. Electron Devices, vol. 55, no. 4, pp. 954–960, Apr. 2008. [6] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor,” Science, vol. 300, pp. 1269–1272, May 2003. [7] A. Suresh, P. Wellenius, and J. F. Muth, “High performance transparent thin film transistors based on indium gallium zinc oxide as the channel material,” IEDM Tech. Dig., pp. 587–590, Dec. 2007. [8] M. J. Yu, Y. H. Yeh, C. C. Cheng, C. Y. Lin, G. T. Ho, B. C. M. Lai, C. M. Leu, T. H. Hou, and Y. J. Chan, “Amorphous InGaZnO thin-film transistors compatible with roll-to-roll fabrication at room temperature,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 47–49, Jan. 2012. [9] C. H. Cheng, F. S. Yeh, and A. Chin, “Low-power high-performance non-volatile memory on a flexible substrate with excellent endurance,” Adv. Mater., vol. 23, no. 7, pp. 902–905, Feb. 2011. [10] H. H. Hsu, C. Y. Chang, and C. H. Cheng, “A flexible IGZO thin-film transistor with stacked TiO -based dielectrics fabricated at room temperature,” IEEE Electron Device Lett., vol. 34, no. 6, pp. 768–770, Jun. 2013. [11] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor,” Science, vol. 300, no. 5623, pp. 1269–1272, May 2003. [12] W. Lim, S. Kim, Y. Wang, J. Lee, D. Norton, S. Pearton, F. Ren, and I. Kravchenko, “Stable room temperature deposited amorphous InGaZnO thin film transistors,” J. Vac. Sci. Technol. B, vol. 26, no. 3, pp. 959–962, May 2008. [13] H. Cho, E. A. Douglas, B. P. Gila, V. Craciun, E. S. Lambers, F. Ren, and S. J. Pearton, “Band offsets in HfO /InGaZnO heterojunctions,” Appl. Phys. Lett., vol. 100, p. 012105, Jan. 2012. [14] E. Klokholm and B. S. Berry, “Intrinsic stress in evaporated metal films,” J. Electrochem. Soc., vol. 115, no. 8, pp. 823–826, Aug. 1968. [15] R. Thielsch, A. Gatto, and N. Kaiser, “Mechanical stress and thermalelastic properties of oxide coatings for use in the deep-ultraviolet spectral region,” Appl. Opt., vol. 41, no. 16, pp. 3211–3217, June 2002. [16] J. Robertson, “Band offsets of wide-band-gap oxides and implications for future electronic devices,” J. Vac. Sci. Technol. B, vol. 18, no. 3, pp. 1785–1791, June 2000. [17] J. H. Na, M. Kitamura, and Y. Arakawa, “High field-effect mobility amorphous InGaZnO transistors with aluminum electrodes,” Appl. Phys. Lett., vol. 93, p. 063501, Aug. 2008. [18] D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. Hoboken, NJ, USA: Wiley, 2006, ch. Chap. 4, p. 208.


[19] A. Sato, K. Abe, R. Hayashi, H. Kumomi, K. Nomura, T. Kamiya, M. Hirano, and H. Hosono, “Amorphous In-Ga-Zn-O coplanar homojunction thin-film transistor,” Appl. Phys. Lett., vol. 94, p. 133502, Apr. 2009.

Hsiao-Hsuan Hsu received the M.S. degree from Department of Electronics Engineering, National Chiao Tung University (NCTU), Taiwan, and is currently working toward the Ph.D. degree in electronics engineering, NCTU. She was with Taiwan Semiconductor Manufacturing Company Ltd. (TSMC), Taiwan, where she was engaged in the development and manufacturing of SRAM devices. She is currently a researcher with the Green Energy and Environment Research Laboratory, Industrial Technology Research Institute, Hsinchu, Taiwan. Her research is focus on oxide TFTs, thermoelectric and MIM capacitors. She has published 30 journal papers and 24 conference papers.

Chun-Yen Chang, photograph and biography not available at time of publication.

881

Chun-Hu Cheng received the Ph.D. degree from Department of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan. He was with Taiwan Semiconductor Manufacturing Company Ltd. (TSMC), Hsinchu, Taiwan, where he was engaged in the development and manufacturing of metal-gate/high- CMOS devices. He is currently an assistant professor with the Department of Mechatronic Technology, National Taiwan Normal University (NTNU), Taipei, Taiwan. His current research interests include the CMOS process integration, NVM devices process (CTF, RRAM, Fe-RAM), low-power TFT, and Energy harvesting technology (GaN devices and Thermoelectric module). He has published 80 journal papers and 50 conference papers.

Po-Chun Chen, photograph and biography not available at time of publication.

Yu-Chien Chiu, photograph and biography not available at time of publication.

Ping Chiou, photograph and biography not available at time of publication.

Chin-Pao Cheng, photograph and biography not available at time of publication.