Gate-Induced Drain-Leakage (GIDL) - kaist

IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 2, FEBRUARY 2009

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Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM) Jin-Woo Han, Seong-Wan Ryu, Sung-Jin Choi, and Yang-Kyu Choi

Abstract—A soft-programming-free operation method in unified RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized according to the designer’s demand. With the utilization of the impact ionization method for 1T-DRAM programming, undesired soft charge trapping into O/N/O gradually shifts the threshold voltage, resulting in an unstable operation in the URAM. In order to avoid such problems associated with soft programming, a gate-induced drain-leakage (GIDL) program method is proposed for improved immunity to disturbance. It is found that the GIDL method effectively suppresses soft programming without sacrificing the sensing current window. Index Terms—Disturbance, FinFET, gate-induced drain leakage (GIDL), nonvolatile memory (NVM), soft program, SONOS, unified RAM (URAM), 1T-DRAM.

I. I NTRODUCTION

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IGH-SPEED 1T-DRAM and nonvolatile Flash memory have been integrated into a single memory cell transistor, thus realizing the so-called unified RAM (URAM), in order to provide versatile memory applications for embedded systems [1], [2]. By combining an oxide/nitride/oxide (O/N/O) gate dielectric as an electron-trapping layer for Flash memory and a partially depleted floating-body as a hole-storage region for 1T-DRAM, URAM operation has been realized in a single memory transistor. Unfortunately, impact ionization for programming of the 1T-DRAM mode can adversely affect trapped charges in the O/N/O layer. Whereas a faster writing speed of 1T-DRAM requires harsh impact ionization conditions, increased impact ionization current causes hot electron injection into the O/N/O layer, resulting in the threshold voltage shift after cyclic 1T-DRAM operations. Therefore, the program voltage of the 1T-DRAM mode becomes restricted as low as Manuscript received October 9, 2008; revised November 18, 2008. First published December 31, 2008; current version published January 28, 2009. This work was supported in part by the National Research Program for the 0.1-Terabit Nonvolatile Memory Development, sponsored by the Ministry of Knowledge Economy. The review of this letter was arranged by Editor T. Wang. The authors are with the Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail: jinu0707@nobelab. kaist.ac.kr; [email protected]; [email protected]; ykchoi@ ee.kaist.ac.kr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2008.2010345

Fig. 1. Schematics of excess-hole-generation method for capacitorless 1T-DRAM. (a) Impact ionization. (b) Band-to-band tunneling (GIDL). Whereas created electrons can be injected into the gate dielectric, created holes are restricted for injection due to the large effective mass and higher valenceband barrier.

possible so as not to disturb the nonvolatile memory (NVM) state. As such, development of a disturbance-free programming method is essential for reliable URAM operation. A capacitorless 1T-DRAM using gate-induced drain-leakage (GIDL) current has been presented for low-power and highspeed memory [3]. Unlike impact ionization, the GIDL method does not involve hot electron injection, and it generates an excessive amount of holes in the floating-body. As shown in Fig. 1, a device biased on the GIDL condition, i.e., a negative gate voltage and a positive drain voltage, creates excessive holes in the channel by band-to-band tunneling. Hole injection into nitride traps is restricted, however, if the NVM is in the erase state prior to the 1T-DRAM mode of URAM operation. Thus, 1T-DRAM can operate without operational interference. In this letter, GIDL current is used at the 1T-DRAM mode of URAM instead of the impact ionization current for a disturbance-free operation. The impact of the 1T-DRAM program method on soft programming is evaluated for both impact ionization and GIDL methods. Finally, a p+ poly-Si gate MOSFET built on a SOI is presented as an effective means of improving the GIDL current. II. R ESULTS AND D ISCUSSION The URAM device structure, process flow, and electrical characteristics, including NVM and 1T-DRAM properties, can be found in [2]. The fabricated FinFET has a fin width of 30 nm, a gate length of 180 nm, an O/N/O thickness of 3/8/3 nm, and a fin height of 110 nm. While the upper 60 nm of the fin is covered by the gate, the lower 50 nm is covered by SiO2 to leave the body floating. In a previous work, all measurement tests were carried out at 25 ◦ C, and the substrate (back gate) was grounded. In order to clarify the soft-programming problem arising from

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Fig. 2. Program/erase characteristics by the impact ionization method for different program voltages at the drain. The sensing current window is reduced at a high drain voltage as the stress time increases due to hot electron injection into the nitride trap layer of O/N/O.

Fig. 3. Program/erase characteristics by the GIDL method. An improved sensing current window is observed, thus supporting that the GIDL is an effective method for 1T-DRAM.

impact ionization, Fig. 2 shows the result of soft programming after 105 cyclic P/E of 1T-DRAM mode operations. The same gate voltages (VG,PGM = VG,ERS = VG,READ = 1 V) were applied for program, erase, and read conditions, and a read drain voltage (VD,READ ) of 0.5 V was applied. The write pulse duration is 100 ns. When the program drain voltage VD,PGM is 1.8 V, a sensing current window of 6 μA is attained, and interference is found to be negligible. For improvement of the sensing window and data retention time, however, the increase of VD,PGM unpropitiously causes hot electron injection into nitride traps, resulting in a gradual increase of the threshold voltage. As a result, P/E instability is triggered. Consequently, this soft program poses constraints in the selection of the programming voltage and resultant sensing current window. Hole injection by GIDL can destroy the stored NVM data if the NVM is in the programmed state. However, if the NVM is in the erased state, the additional hole injection will be suppressed due to the insufficient vertical electric field to attract the hole current into the O/N/O trapping layer. Therefore, NVM should be in the erased state prior to the selection of the 1T-DRAM mode from URAM in order to avoid the disturbance. In this letter, the initial threshold voltage is set to 0.3 V when URAM is allocated to the 1T-DRAM mode. Fig. 3 shows the P/E

IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 2, FEBRUARY 2009

Fig. 4. Threshold voltage versus stress time. Threshold voltage is an indicator to estimate the trapped charges in the nitride. GIDL does not shift the threshold voltage, while the impact ionization condition does.

pulse waveform and its resultant source current. For writing data “1,” the program conditions of VG = −2 and VD = 2 V were used. Band-to-band tunneling occurring at the gate–drain overlap region then generates holes, which are accumulated in the floating-body. For writing data “0,” the erase conditions of VG = 1 V and VD = −1.5 V were applied. Hence, a forward biased channel-to-drain current removes the excessive holes. The data states are thereby distinguished by sensing the source current difference based on the existence of excessive holes in the floating-body. A source current window of 12 μA and a data retention time of 50 ms are achieved, and hence, the stored data states can be identified. In order to verify the absence of interference, a dc stress test was carried out as well. The amount of trapped charges in the nitride can be evaluated by monitoring the shift of the threshold voltage. The proper stress conditions were chosen to the aforementioned program voltages for impact ionization and GIDL. Fig. 4 shows the impact of 1T-DRAM operation on the threshold voltage shift. Whereas 1T-DRAM operation under the impact ionization method induces trapped charges into the O/N/O layer, the 1T-DRAM operation under the GIDL method does not lead to the accumulation of trapped charges. Thus, the GIDL method is the effective means of achieving a disturbancefree operation between the NVM and 1T-DRAM modes. It is worthwhile to note that the GIDL method in URAM may be inefficient in terms of generating band-to-band tunneling current due to the thick gate dielectric (O/N/O), which results in a degraded program efficiency. A thicker gate dielectric requires a higher gate voltage to attain sufficient energy band bending for GIDL. In order to overcome this disadvantage originating from a thick O/N/O layer, a p+ poly-Si gate (or high workfunction gate), on a p-type body, is proposed. Fig. 5(a) shows the simulation results of the drain and the substrate currents’ characteristics for an n+ poly-Si versus p+ poly-Si gate on a p-type body. The device structures used in the simulation are equivalent to the fabricated devices, except that the simulation structures formed on a bulk substrate in order to extract the substrate current. The comparison of GIDL in p+ poly-Si and n+ poly-Si gated NMOS shows that the p+ poly-Si gate device induces higher GIDL than the equivalent n+ poly-Si gate device at a given supply voltage [4]. The higher GIDL in the


HAN et al.: PROGRAMMING METHOD FOR SOFT-PROGRAMMING-FREE OPERATION IN UNIFIED RAM

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It reveals that the lower programming voltage of the 1T-DRAM is at the expense of the higher programming voltage for NVM. In order to improve the programming efficiency, tunneling barrier engineering, such as the “multilayer SONOS [5],” “crested barrier [6],” and “VARIOT [7],” has been suggested. Thus, the low programming efficiency can be circumvented if the tunneling barrier engineering is introduced to the p+ poly-Si gate. III. C ONCLUSION A disturbance-free operation method in URAM is presented. In order to avoid soft programming, a GIDL program method is employed. Unlike the impact ionization method, the GIDL method does not create hot electrons, which cause the interference to the NVM state; instead, the GIDL method produces excess holes in the channel to perform 1T-DRAM. As a result, the impact of the 1T-DRAM operation on the NVM state is significantly suppressed with a sustained sensing current window. The simulation results reveal that a p+ poly-Si gate on a p-type body FinFET SONOS circumvents the reduced bandto-band tunneling current, owing to the thick gate dielectric thickness of O/N/O. R EFERENCES

Fig. 5. (a) Simulated drain and substrate current. (b) Program/erase characteristics for a n+ poly-Si versus p+ poly-Si gate on a p-type body. Considering that the GIDL current of the p+ poly-Si gate is higher than that of the n+ poly-Si gate at a given programming voltage, programming efficiency can be improved in the proposed buried-channel 1T-DRAM.

p+ poly-Si gate is due to the larger inherent flatband voltage difference between the p+ poly-Si gate and the n+ junction in the gate-to-drain overlap region. Therefore, the implementation of the p+ poly-Si or high work-function gate MOSFET can yield improved memory characteristics in URAM. The simulation data for program/erase are shown in Fig. 5(b). The program/erase voltages are the same, and the read voltages are set for VG − VT to be identical. Although the program pulse is below 10 ns, the p+ poly-Si gated device shows a superior sensing window to that of the n+ poly-Si one. It should be noted that, in the NVM mode of URAM, the p+ poly-Si gate will degrade the programming efficiency but will improve the erasing efficiency.

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