Gate Leakage in Low Standby Power 16 nm Gate ...

Gate Leakage in Low Standby Power 16 nm Gate Length Double-Gate MOSFETs Mohamed Abd El Hakim1 Yasser M. Sabry2 Yousry Elmaghraby3 Tarek M.Abdolkader4 Wael Fikry5 1,5 Department of Engineering Physics and Mathematics, Faculty of Engineering, Ain Shams University, Egypt. [email protected] 5 [email protected] 2 Department of Electronics and Communication, Faculty of Engineering, Ain Shams University, Egypt. [email protected] 3 Silicon Vision. [email protected] 4 Department of Basic Sciences, Benha Institute of Technology, Egypt. [email protected]

Abstract Leakage power, due to the tunneling gate current, increases aggressively with the scaling of the insulator thickness. Low Standby Power (LSTP) devices are typically designed for low power applications that put strict limits on the gate current. In this work a widely used model for the tunneling gate current in bulk MOSFET is modified to suits the Double-gate (DG) MOSFET. The modification is made to include quantum mechanical effects. Then, the model is used to study the gate leakage in a 16 nm gate length DG MOSFET LSTP transistor that is projected by the International Technology Roadmap for Semiconductors (ITRS) to be fabricated in the year 2015. In this study, the gate current is calculated for different candidates of dielectric materials. Specifically, nine dielectric materials were used. The simulated gate current is found to be 5.36x103 A/cm2 when SiO2 was used as a dielectric and 338.76 A/cm2 when Si3N4 was used. These two values exceed the maximum allowed gate current density (Jg,limit) projected by ITRS for this device which is 0.188 A/cm2. The lowest obtained gate current density was 2.66x10-11 A/cm2 when La2O3 and is used.

1. Introduction Silicon CMOS has emerged over the last 25 years as the predominant technology of the microelectronics industry [1]. The concept of device scaling has been consistently applied over many technology generations, resulting in continuous improvement in both device density and performance [2]. Device dimensions are now well below the micrometer scale into the nanometer regime. The International Technology Roadmap for Semiconductors (ITRS) suggests that CMOS technology is approaching fundamental physical limits in the near future. The ITRS classifies the semiconductor devices into three categories according to performance [2]: 1) high performance (HP) logic technology; 2) low operating power (LOP) technology; and 3) low stand-by power technology (LSTP). LSTP chips are typically for lower performance, lower cost consumer type applications, such as consumer cellular telephones, with lower battery capacity and an emphasis on the lowest possible static power dissipation, i.e., the lowest possible leakage current. Moreover the gate length for LSTP devices lags that of high-performance logic by four years, reflecting the ultra-low leakage current required [2]. The ITRS defined the parameter (Jg,limit) which represents the gate current density limit for a given device at 25°C. It’s measured with the gate biased to VDD while the source and the drain are tied to ground. The reduction of gate current is an important reason for the intense research being carried out to replace silicon dioxide (SiO2) with high-k material. The gate capacitance obtained in case of a high-k material equals that obtained in case of SiO2 but with a higher thickness for the high k material thus a lower gate current. In other words a high k material gives us the advantage of reaching the same oxide capacitance or the same equivalent oxide thickness (EOT) but with less leakage current. Table 1 lists a number of high-k dielectric materials which are being considered as prospective replacement for SiO 2 [3]. The suitability of a particular material not only depends on its dielectric constant (k), but also on its conduction band offset to silicon. 26th NATIONAL RADIO SCIENCE CONFERENCE, NRSC’2009 Future University, 5th Compound, New Cairo, Egypt, March 17 – 19, 2009

Table 1 Relative dielectric material constant (k) and conduction bad offset for dielectric materials used in our simulation taken from [3]. Material Dielectric constant (k) Conduction band offset (eV) Al2O3 9 2.8 HfO2 25 1.5 La2O3 30 2.3 SiO2 3.9 3.0 Si3N4 7 2.0 Ta2O5 25 1.4 TiO2 40 1.1 Y2O3 15 2.3 ZrO2 25 1.4 The continuous scaling of CMOS technology results in several problems due to short channel effects (SCEs). The boundaries set on the bulk CMOS technology were extended by the invention of alternative technologies and circuit techniques. One of the most promising of these was the silicon-on-insulator (SOI) technology [4]. SOI technology has some advantages like reduction of parasitic capacitances leading to faster and denser circuits, smaller gate lengths and better sub-threshold swing [4], [5]. At the same time, it has some disadvantages such as kink and self heating effects [5]. Double-Gate (DG) MOSFETs are attractive candidates to continue the scaling down to gate lengths in the 50 nm to 10 nm range [6], [7]. ITRS promotes ultra-thin DG MOSFETs as the ideal device structure for ultimate scaling [2]. The cross section of a DG MOSFET device is shown in figure 1 with the energy band diagram in x direction is given in figure 2. The confinement of carriers in the transverse direction of DG MOSFET device originates due to two reasons [7]: 1) structural confinement and 2) electrical confinement. The structural confinement arises from the presence of the top and bottom oxide layers. These two oxide layers form a quantum well (well (1) in figure 2) whose width equals to the Silicon film thickness (Tsi). The electrical confinement occurs due to steep band bending at the surface which is effective at large transverse electric fields (well (2) in figure 2).

Figure 1. Double-gate SOI MOSFET.

Figure 2. Double gate device energy band diagram in the x direction.

Due to carrier confinement, the energy levels available for motion in the direction normal to the interface are quantized. As a result, the conduction band will split into sub bands each of which has a minimum energy as depicted in figure 3. The quantization of energy is stronger (or the separation of energy levels is higher) for smaller Si-film thicknesses and for larger surface electric fields. Quantum transport based device simulation is carried out using self-consistent solution for Poisson and Schrödinger equations. The self-consistent solution approach is accurate approach but needs excessive computations [7]. It is an iterative algorithm (shown in figure 4) that solves the equations many times until an acceptable tolerance is achieved. First an initial guess for the potential is assumed, and then this guess is used to solve the transport equation. After that, the solution obtained from Schrödinger equation is used to solve Poisson equation. This loop continues until an acceptable tolerance is achieved. FETMOSS is a DG MOSFETs simulator that is based on the self-consistent solution method described above [8]. 26th NATIONAL RADIO SCIENCE CONFERENCE, NRSC’2009 Future University, 5th Compound, New Cairo, Egypt, March 17 – 19, 2009

Subbands

Conduction band

3 2 1 EG (DG )

EG (bulk )

Figure 3. The splitting of the conduction band into subbands due to carrier confinement.

Figure 4. Flow chart for the self consistent solution.

In this work, a gate current model for bulk MOSFETs is adapted to be suitable for DG MOSFET gate current modeling. The modifications are made to include the effect of conduction band splitting. The new model (after modifications) is implemented in the DG MOSFET simulator FETMOSS. The rest of this article is organized as follows. In section 2 the original model is described and the necessary modifications are highlighted. Tunneling gate current simulation results for the LSTP 16 nm device are presented in section 3. Finally, this article is concluded in section 4.

2. Gate Current Modeling The original model before being modified is based on Tsu Esaki relation [9], [10] as shown in (1). This formula was used recently in the gate current calculation for the bulk MOSFET in the device simulator Minimos [11]. (1) In (1) q is the electron charge, h is plank’s constant, meff is the effective mass of the electron in the dielectric, is the energy and subscript x means the energy component in the x direction normal to the interface as shown in figure 5 where and is the component parallel to the interface. is the supply function which describes the supply of carriers for tunneling and it’s given by (2) where is the energy distribution function in the channel while is that in the gate electrode considered as Polysilicon in this model. In (1) is the transmission coefficient and it describes the penetrability of the considered energy barrier. The product of the supply function and the transmission coefficient is integrated over the energy from to . is the minimum allowed energy for the electrons. In case of bulk MOSFET is the higher value of the conduction band edge (Ec) in either the gate electrode or the Silicon. is the highest energy level in the whole energy band diagram which is the conduction band of the oxide at the interface of the side of the lower bias [11].

26th NATIONAL RADIO SCIENCE CONFERENCE, NRSC’2009 Future University, 5th Compound, New Cairo, Egypt, March 17 – 19, 2009

W(x)

Constant potential approximation

A1

AN

B1

BN x W(x)

Figure 5. The energy barrier of a single-layer dielectric. The potential energy W(x) is the conduction band and it’s approximated by piece wise constant functions to calculate transmission coefficient using transfer matrix method.

2.1 Effect of Energy Quantization To make this model suitable for DG device, we made a modification to take into account the effect of energy quantization. In DG structure the minimum allowed energy for the electrons in the Silicon is not Ec. But it’s a higher energy level as if the energy gap has increased. Accordingly in (1) has to be either Ec in the gate electrode or the ground state of the eigenenergies depending on which value is higher. The formed sub-bands due to quantization differ in their carrier distribution. As a result the quasi Fermi level will differ from one sub-band to the other. To account for this in our gate current modeling, the gate current is computed for each sub-band then the total gate current is obtained by summing the gate current obtained from each sub-band.

2.2 Supply Function Modeling In Equilibrium the energy distribution function of electrons is given by the Fermi-Dirac statistics as in (3) which can be derived from statistical thermodynamics [12] separating the longitudinal and transversal energy components and splitting the integral in (2) as where and are given by (4) (3)

(4)

This expression can be integrated so (4) evaluates to (5) Finally, the total supply function becomes


(6)

2.3 Transmission Coefficient Modeling Figure 5 depicts an energy barrier for which we want to calculate the transmission coefficient. We have to solve Schrödinger equation where the domain of the solution is the dielectric material. The solution starts with assuming a wave injected from the left with amplitude A1 and results in a wave function . A portion of this wave is reflected in the negative x-direction with amplitude B1 and the other is transmitted through the barrier in the positive x-direction with amplitude AN. The transmission coefficient can be calculated as with

where W1,N is the potential in either electrode [13].

To model the transmission coefficient we used the transfer matrix method. The basic principle of the transfer matrix method is the approximation of an arbitrary shaped energy barrier by a series of piece-wise constant functions. Since the wave function in such barriers can easily be calculated, the total transfer matrix can be derived by a number of subsequent matrix computations. From the transfer matrix, the transmission coefficient can easily be derived. If an arbitrary potential barrier is segmented into N regions with constant potentials (see figure 5) the wave function in each region can be written as the sum of an incident and a reflected wave with where Wi is the potential in the segment i obtained from the self consistent solution, m eff is the effective mass in the dielectric material and is the energy of electron. Applying the conditions of continuity for ψ(x) and dψ(x)/dx between each two successive segments, we arrive at a series of matrix equations relating Ai and Bi of any segment with those of the preceding segment Ai-1 and Bi-1 as follows, (7) Where

(8)

In our tunneling problem there is no reflection in the region N thus BN=0. Since we are interested in the reflection coefficient we can simply let A1=1 and thus AN=t and BN=r (9) where

(10)

and

(11)

thus

(12)

and the transmission coefficient can be calculated from (12) as

.

Finally

(13)

Where

(14)


The main advantages of the Transfer Matrix method are being simple, easily implemented and suitable for any arbitrary barrier shape. On the other hand the computational burden in consecutive matrices multiplication increases as we increase the number of segments in the dielectric.

3. Results and Discussion 3.1 Tunneling Current Model Verification We have implemented the previously discussed model in the device simulator FETMOSS. The gate current is computed after the end of the self consistent solution of the device. The inputs to the model are the eigenenergies of electrons, the potential profile, the carrier distribution for each sub-band and the bias. The supply function and the transmission coefficient are evaluated then their product is numerically integrated to evaluate the gate current. In order to validate the implementation of the tunneling current model we compared our results against that published by the author “Saibal Mukhopadhyay” in [14]. The used geometrical and physical parameters are summarized in Table 2. Figure 6 shows a close agreement between our results and that in [14]. Table 2. Geometrical and physical parameters used in the estimation of gate current Parameter Value Lgate 20 nm Tox 10 Å Tsi 5 nm VDD 1V Channel Doping 1e17 cm-3

Figure 6. Verification of our model results against that in [14].

3.2 LSTP 16 nm Gate Current Study In this section the gate current for a LSTP device that is projected by ITRS to be fabricated in 2015 is studied. The parameters for this device are summarized in table 3. First the gate current density along the channel is calculated. Second the effects of varying the oxide thickness and the channel doping on the gate current are studied. Finally the use of high k material is investigated.

Table 3. ITRS projected values for LSTP 16 nm technology node Parameter ITRS projected value Lg 16 nm EOT 11 Å VDD 0.8 V Jg,limit 1.88E-01 A/cm2

Figure 7. Gate current density along the channel at VD=0. Figure 7 shows the gate current density along the channel at different VG bias points all with VD=0. The gate current looks symmetric along the channel because of symmetric bias of source and drain. The gate current 26th NATIONAL RADIO SCIENCE CONFERENCE, NRSC’2009 Future University, 5th Compound, New Cairo, Egypt, March 17 – 19, 2009

density is lower in the middle of the channel than the sides close to the source and drain. That is why reference [15] suggests increasing the oxide thickness in the sides near source and drain and tapering this thickness to a lower value as we move towards the channel to decrease the gate leakage. To study the effect of oxide thickness variation, we changed the oxide thickness around the expected value of the EOT from 0.8 nm to 1.4 nm. At such low oxide thickness the dominant tunneling mechanism is direct tunneling rather than Fowler-Nordheim tunneling. Direct tunneling current increases exponentially as we decrease the oxide thickness [2]. Figure 8 shows the gate current versus the oxide thickness on a semi log scale which decreases linearly (on a log scale) as we increase the oxide thickness. To study the effect of the channel doping on gate leakage, we varied the channel doping and computed the gate current. As we increase the channel doping the threshold voltage is increased [16] thus the inversion charge decreases for the same value of VG. As a result the charge available for tunneling will decrease and the gate current will decrease. Figure 9 shows the gate current versus VG at different channel doping.

Figure 8. Effect of oxide thickness variation on LSTP 16nm transistor gate current.

Figure 9. Effect of channel doping on 16nm LSTP transistor gate current.

We have investigated the use of high k materials as a replacement for Silicon dioxide. The used dielectric materials in the simulation are those tabulated in table 1. The effective mass for SiO2 is assumed to be 0.35me while that of other high-k materials is assumed to be 0.3me [3]. Figure 10 shows the gate current density calculated for each of the nine dielectric materials. The solid horizontal line represents value of J g,limit as projected by ITRS 2007 for this device. The figure shows that the simulated gate current is less than Jg,limit when materials Al2O3, HfO2, La2O3, Ta2O5, TiO2, Y2O3 and ZrO2 were used. However when SiO2 or Si3N4 was used the gate current density exceeds Jg,limit. ITRS 2007 expected that the standard technology of Silicon Dioxide can’t be used in the devices fabricated after 2008 [2]. Figure 10 also depicts that the simulated gate current is the least when Lanthanum Oxide (La2O3) is used as a dielectric. However the Hafnium Oxide (HfO2) represents one of the allowed high k materials that offers low gate current leakage with more compatibility with Silicon than other dielectric materials [17]. That is why the recent high-k metal gate technology used a Hafnium based dielectric material [18].

Figure 10. High-k material study for LSTP 16nm technology node.


4. Conclusion A model for the tunneling gate current in the bulk MOSFET was successfully adapted to suits DG MOSFETs. This model was implemented and integrated in the DG MOSFETs simulator FETMOSS. Then, the model was used to study gate leakage in LSTP 16 nm MOSFETs that are expected to be fabricated in the year 2015. The effect of varying the oxide thickness, the channel doping and the applied bias was studied. Moreover, the replacement of SiO2 with high-k materials was explored. The simulated gate current for each dielectric material was compared with the ITRS gate current density projection. The gate current obtained for SiO2 and Si3N4 was exceeding the allowable limits. La2O3 and HfO2 were found to be the most promising materials showing the lowest gate current leakage. Technological and compatibility issues may add more restrictions on the high-k material to be used in the future.

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