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which is attributed to the superior oxygen diffusion barrier property of HfN as well as the thermal stability of the HfN–HfO2 interface. Therefore, even without ...



Robust High-Quality HfN–HfO2 Gate Stack for Advanced MOS Device Applications H. Y. Yu, Student Member, IEEE, J. F. Kang, C. Ren, J. D. Chen, Y. T. Hou, Student Member, IEEE, C. Shen, M. F. Li, Senior Member, IEEE, D. S. H. Chan, K. L. Bera, C. H. Tung, and D.-L. Kwong, Senior Member, IEEE

Abstract—In this letter, a thermally stable and high-quality HfN–HfO2 gate stack for advanced MOS applications is reported for the first time. Negligible changes in both equivalent oxide thickness (EOT) and work function of HfN–HfO2 gate stack are demonstrated even after 1000 C postmetal annealing (PMA), which is attributed to the superior oxygen diffusion barrier property of HfN as well as the thermal stability of the HfN–HfO2 interface. Therefore, even without surface nitridation prior to HfO2 deposition, the EOT of HfN–HfO2 gate stack can be after 1000 C PMA successfully scaled down to less than 10 with excellent leakage and long-term reliability.


K gate dielectrics, metal gate

Index Terms—HfN, HfO2 , highelectrode, MOS devices.

I. INTRODUCTION HfO has been considered as one of the most promising high- gate dielectrics to replace conventional SiO gate dielectrics for addressing the excessive gate leakage concern [1]. However, HfO is a poor barrier to oxygen diffusion, which causes the uncontrolled growth of a low- interfacial layer between HfO and the Si substrate during high-temperature postprocessing [1], [2] and, hence, imposes serious concern to equivalent oxide thickness (EOT) scalability. Although using surface nitridation or HfO N can minimize interfacial layer growth [3], [4], they also cause severe carrier mobility degradation. Recently, we have demonstrated that HfN gate electrode exhibits superior thermal stability with SiO gate dielectrics and is an excellent barrier against oxygen diffusion [5]. In this letter, we present a thermally robust high-quality HfN–HfO gate stack with excellent EOT scalability, and investigate its performance and reliability for MOS device applications. II. EXPERIMENTAL The MOS capacitors (MOSCAPs) were fabricated using p-Si(100) substrates. After the definition of the active area with 4000- field oxide and standard diluted hydrofluoric acid Manuscript received July 22, 2003; revised October 6, 2003. This work was supported by the Singapore A-STAR under Grant EMT/TP/00/001,2. The review of this letter was arranged by Editor J.-T. King. H. Y. Yu, J. F. Kang, C. Ren, J. D. Chen, Y. T. Hou, C. Shen, M. F. Li, and D. S. H. Chan are with the Silicon Nano Device Lab, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260. M. F. Li, K. L. Bera, and C. H. Tung are with the Institute of Microelectronics, Singapore 117685. J. F. Kang is with the Institute of Microelectronics, Peking University, Beijing 100871, China. D.-L. Kwong is with the Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712 USA. Digital Object Identifier 10.1109/LED.2003.820649

(DHF)-last RCA (SC1+SC2 cleaning) pregate clean, chemical vapor deposition (CVD) HfO films were deposited at 400 C and O in a metallo-organic chemical using Hf OC CH vapor deposition (MOCVD) cluster tool, followed by an in situ postdeposition annealing (PDA) at 700 C in N ambient to nm capped with 100-nm improve film quality. HfN of TaN metal stacked layers were then deposited by dc sputtering of an Hf /Ta target in Ar N mixed gas ambient and patterned using a Cl -based RIE [5]. The MOSCAPs were then rapid thermal annealed (RTA) in N at 900 C to 1000 C for 20 s for thermal stability evaluation. For -channel MOSFETs fabrication, source/drain implantation of phosphorus with a dose of cm were performed followed by RTA activation in N 5 at 950 C for 30 s. All devices were finally subjected to back side Al metallization and forming-gas annealing (FGA) at 420 C for 30 min. EOT and flat band voltage ( ) were simulated by taking into account the quantum mechanical correction. III. RESULTS AND DISCUSSIONS Fig. 1(a) shows measured capacitance–voltage (C–V) (the symbols) of a HfN–HfO device after 1000 C postmetal annealing (PMA), which is in good agreement with the simulation (the solid line). Without surface nitridation treatment, the EOT of the HfN–HfO MOSCAP is as low as 8.2 after FGA, and it slightly increases to 8.8 /9.1 after 900 C to 1000 C PMA. Negligible variation of the gate leakage current is observed in these devices after various thermal treatments, as 1 V, shown in the inset of Fig. 1(a). At a gate voltage of HfN–HfO gate stack after 1000 C PMA exhibits gate leakage cm , showing more than a factor of reduction of compared to poly-Si/SiO benchmark [6] at the same EOT. High-resolution cross-sectional transmission electron microscopy (XTEM) is utilized to characterize these HfN–HfO gate stacks after various RTA, as shown in Fig. 1(b). Negligible change due to RTA in the physical thickness of both HfO and interfacial layer is seen, consistent with results in Fig. 1(a). From the XTEM and C–V data, and with the assumption that , the interfacial layers value HfO has a value of , and thus it is not pure SiO [2]. is calculated to be The superior thermal stability of the HfN–HfO gate stack is further demonstrated in Fig. 2, where three devices with different EOT are plotted as a function of RTA temperatures. The results show that the EOT variations in all HfN–HfO devices are negligible up to 1000 C PMA. Physical vapor deposited (PVD) TaN has been extensively studied as a promising metal gate candidate, e.g., [4]. For comparison, EOT of TaN–HfO gate stack versus PMA temperature is also included in Fig. 2.

0741-3106/04$20.00 © 2004 IEEE



Fig. 3. Lifetime projection based on SILC of HfN–HfO MOSCAP after A. The failure criterion is set at 50% 1000 C PMA with EOT = 9:1  increments of Jg . Inset shows typical SILC time evolutions at four gate voltages.


(b) Fig. 1. (a) Comparison between C–V measurement data (symbols) and simulation data (the solid line) for HfN–HfO -MOSCAP after 1000 C PMA A). No surface nitridation (SN) was performed annealing (with EOT = 9:1  before HfO deposition. The inset shows leakage comparison measured from the HfN–HfO MOSCAP after various PMA processes. (b) Cross-sectional HRTEM images of these HfN–HfO MOSCAPs after different thermal A and HfO is 23 A. treatments. For FGA sample, interfacial layer is 7 


(b) Fig. 2. Dependence of EOT for HfN gated and TaN gated MOSCAP with HfO gate dielectrics on the N RTA temperature. No surface nitridation was done prior to HfO deposition for all of the samples. Compared to HfN case, the EOT of TaN gated MOSCAP show significant increase after 900 C and 1000 C PMA.

The EOT of TaN–HfO shows significant increases after 900 and 1000 C PMA. The inferior thermal stability of PVD TaN compared to HfN might be attributed to its negatively smaller

Fig. 4. (a) I –V characteristics of an n-MOSFET using HfN–HfO gate stack (W/O surface nitridation) with EOT 1:18 nm. The inset shows HF C–V measurement of the n-MOSFET. (b) The I –V characteristics from the corresponding n-MOSFET.

heat of formation [7] and its inferior ability to block oxygen diffusion during RTA. ) of HfN on HfO is extracted from The work function ( plots of versus EOT. of HfN after FGA is 4.75 eV and



slightly increases to 4.8 eV after 1000 C PMA, and this small variation after 1000 C RTA is related to the HfN crystallization change [5]. These results suggest that the HfN–HfO interface is thermally stable. We also investigate the reliability of 1000 C annealed HfN–HfO gate stack. The typical stress-induced leakage current (SILC) time evolutions at four gate voltages (ranging from 2.8 V to 3.4 V) of the 1000 C RTA treated HfN–HfO device (EOT ) are shown in the inset of Fig. 3. Setting as failure criterion, the operating voltage for a ten-year lifetime is projected as 2.2 V, as shown in Fig. 3. Inset of Fig. 4(a) shows high-frequency (HF) C–V from an n-MOSFET (without surface nitridation treatment) with nm from the CV). The gateHfN–HfO stack (EOT depletion effect is suppressed as expected. Note that the HfO dielectric thickness in the MOSFETs is , by ellipsometer measurements. Fig. 4(a) and (b) shows the well-behaved electrical characteristics ( – and – ) of the n-MOSFET with an excellent subthreshold slope (ss) of 78 mV/dec. IV. CONCLUSION In summary, a thermally robust high-quality HfN–HfO gate stack is demonstrated for advanced MOS device applications. Due to the superior oxygen diffusion barrier property of HfN as well as the thermal stability of the HfN–HfO interface, EOT of HfN–HfO gate stack has been successfully scaled down to less

than 10 with excellent leakage and long-term reliability even after 1000 C PMA, without using surface nitridation prior to HfO deposition. Negligible variation in both the EOT and the work function of HfN–HfO gate stack are observed upon PMA treatments up to 1000 C. REFERENCES [1] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-K gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys., vol. 89, pp. 5243–5276, 2001. [2] H. Y. Yu, N. Wu, M. F. Li, C. X. Zhu, B. J. Cho, D.-L. Kwong, C. H. Tung, J. S. Pan, J. W. Chai, W. D. Wang, D. Z. Chi, C. H. Ang, J. Z. Zheng, and S. Ramanathan, “Thermal stability of (HfO ) (Al O ) on Si,” Appl. Phy. Lett., vol. 81, pp. 3618–3620, 2002. [3] C. H. Choi, S. J. Rhee, T. S. Jeon, N. Lu, J. H. Sim, R. Clark, M. Niwa, and D. L. Kwong, “Thermally stable CVD HfO N advanced gate dielectrics with poly-Si gate electrode,” in IEDM Tech Dig., 2002, pp. 857–860. [4] C. S. Kang, H. J. Cho, K. Onishi, R. Choi, Y. H. Kim, R. Nieh, J. Han, S. Krishnan, A. Shahriar, and J. C. Lee, “Nitrogen concentration effects and performance improvement of MOSFETs using thermally stable HfO N gate dielectrics,” in IEDM Tech. Dig., 2002, pp. 865–868. [5] H. Y. Yu, H. F. Lim, J. H. Chen, M.-F. Li, C. X. Zhu, C. H. Tung, A. Y. Du, W. D. Wang, D. Z. Chi, and D. L. Kwong, “Physical and electrical characteristics of HfN gate electrode for advanced MOS devices,” IEEE Electron Device Lett., vol. 24, pp. 230–232, Apr. 2003. [6] T. Watanabe, M. Takayanagi, R. Iijima, K. Ishimaru, H. Ishiuchi, and Y. Tsunashima, “Design guideline of HfSiON gate dielectrics for 65 nm CMOS generation,” Symp. VLSI Tech. Dig., pp. 19–20, 2003. [7] M. Wittmer, “Properties and microelectronic applications of thin films of refractory metal nitrides,” J. Vac. Sci. Technol. A, vol. 3, pp. 1797–1803, 1985.

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