Gated-four-probe A-Si:H TFT Structure: A New Technique To Measure ...

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Intrinsic Performance of a-Si:H TFT. Chun-ying Chen and Jerzy Kanicki. Abstract— In this letter, a new technique based on gated- four-probe hydrogenated ...
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IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 7, JULY 1997

Gated-Four-Probe a-Si:H TFT Structure: A New Technique to Measure the Intrinsic Performance of a-Si:H TFT Chun-ying Chen and Jerzy Kanicki

Abstract— In this letter, a new technique based on gatedfour-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series RESISTANCES.

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HE nonnegligible source/drain series resistances of amorphous silicon (a-Si:H) thin-film transistors (TFT’s) not only influence the electrical performance of a-Si:H TFT’s (such as extracted mobility and threshold voltage) [1], but also make it difficult to optimize channel material and a-Si:H TFT performance. To understand the intrinsic performance of aSi:H TFT, there is a need to exclude the effect of source/drain series resistances. In this letter, we introduce a new gated-fourprobe a-Si:H TFT structure to accurately measure the intrinsic performance of a-Si:H TFT’s. The conventional equations describing a-Si:H TFT performance can be derived from the charge control model [2]. In this model the concentration of free carriers, , induced into the conducting channel is given by (1) where is the geometrical capacitance of the gate insulator; is the applied gate bias; is the effective threshold voltage; is the channel potential; and is the electronic charge. In this approximation, the dependence of the charge in the depletion layer on the surface channel potential has been neglected. Based on the gradual channel approximation, the drain current then can be expressed as (2) Manuscript received November 1, 1996; revised March 17, 1997. This work was supported by the Center for Display Technology and Manufacturing, University of Michigan. The authors are with the Department of Electrical Engineering and Computer Science, Center for Display Technology and Manufacturing, University of Michigan, Ann Arbor, MI 48109 USA. Publisher Item Identifier S 0741-3106(97)05085-4.

where is the channel width and is the field-effect mobility. This equation can be rewritten as (3) Integration of the above gives

(4) where is the channel length and is the drain voltage. The above equation leads to the following equation: for For small

(5)

, this equation can be simplified to (6)

where is the normalized channel conductance. Equation (6) is traditionally used to extract the field-effect mobility and threshold voltage of a-Si:H TFT operating in a linear region. However, the above derivation does not include the effect of source/drain series resistances. In fact, the source/drain series resistances cannot be ignored in a real a-Si:H TFT. To exclude the voltage drops at source/drain series resistances, the range of integration for in (3) should to ( ), where and are start from series resistances at source and drain terminals, respectively. By assuming , the integration of (3) yields (7) This equation shows that the existence of series resistances make the – characteristics become nonlinear. If is ohmic and is independent of , , and , the intrinsic mobility, threshold voltage, and series resistances can be extracted by least square fit to (7).1 However, this ideal case is not representative for a-Si:H TFT. In a-Si:H TFT, is , , , and source/drain-gate overlap dependent, which makes the extraction of the intrinsic mobility and threshold voltage from (7) difficult.

kV V 1 Equation (7) can be expressed as I D = kVV V0(20kR V 01) = ax0b , with k = Ci W=L; x = VG ; a = kVD2kR ; b = aV ; c = 2kRS , T cx0d and d = cVT 01; the intrinsic mobility and threshold voltage can be extracted by least square fit for the four parameters a, b, c, and d. This extraction method is only valid for constant RS :

0741–3106/97$10.00  1997 IEEE

CHEN AND KANICKI: GATED-FOUR-PROBE a-Si:H TFT STRUCTURE

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Fig. 1. Top view and cross section of the gated-four-probe a-Si:H TFT structure.

In order to extract intrinsic mobility and intrinsic threshold voltage of a-Si:H TFT, the measurement must exclude the effect of source/drain series resistances. For this reason, we have developed the new gated-four-probe a-Si:H TFT structure described in this letter. Fig. 1 shows top view and cross section of this new gatedfour-probe a-Si:H TFT structure. It is similar to conventional bottom-gate back-channel-etched a-Si:H TFT but two additional narrow metal electrodes (probe A and probe B) have been added between the source and drain contacts to probe the potential at and , respectively. Integration of (3) from to yields

(8) where and are the probed channel potential at and , respectively. This equation can be rewritten as (9) where

, and or (10)

where is the effective normalized channel conductance. Since probes A and B sense only the potential but not the current, and there is no current flow through these two probes, and will represent the true channel potential without being influenced by the source/drain series resistances. The width of probes A and B should be as narrow as possible to avoid influence of these probes on the electrical field inside the conducting channel. In our case for ranging from 20 to

90 m, the probes A and B had width of 2 m. Experimentally it has been established that the a-Si:H TFT performance with or without probes A and B present within the channel was the same. However, this will not be true for a-Si:H TFT having comparable to the width of the probe. By using the gated-four-probe a-Si:H TFT structure, intrinsic mobility and intrinsic threshold voltage can be extracted from (10), without any influence from the source/drain series resistances. By plotting versus , the intrinsic mobility can be extracted from the slope, and the intrinsic threshold voltage can be extracted from the interception to the -axis. To test this structure, we have fabricated several gatedfour-probe a-Si:H TFT’s and inverted-staggered back-channeletched a-Si:H TFT’s with various channel lengths on the same glass substrates. The fabrication process of gated-four-probe a-Si:H TFT structure is fully compatible with a-Si:H TFT, and both structures can be fabricated at the same time during the fabrication of a-Si:H TFT’s without any additional process ˚ thick chromium, step. The gate electrode, made of 1600-A was formed on the Corning 7059 glass substrate, followed ˚ thick amorphous hydrogenated silicon by depositing 3500-A ˚ thick a-Si:H for nitride (a-SiN:H) for gate insulator, 2500-A ˚ the semi-conductor layer, and 700-A thick n a-Si:H for source/drain contact layer. The a-Si:H and a-SiN:H films used in this structure were deposited by a high deposition-rate plasma-enhanced chemical-vapor-deposition (PECVD) system [3], [4]. The active island for channel region was defined by dry etching, and gate via for gate contact was defined by ˚ thick molybdenum was formed as wet etching. Then, 3000-A source/drain and probe electrodes. The probe width is 2 m. The channel length was defined by etching out n a-Si:H layer in the channel region by using source/drain and probe metal as a mask. From the – or – characteristics, the mobility and threshold voltage values have been extracted for different channel lengths varying from 10 to 70 m and from 2 to 482 m for gated-four-probe a-Si:H TFT and a-Si:H TFT structures, respectively. For a-Si:H TFT’s, the mobility and threshold voltage were extracted by a least-squares fit (between 20% and 80% of the maximum normalized channel conducV. For gated-four-probe a-Si:H tance) to (6) with TFT, the mobility and threshold voltage were extracted by a least-squares fit (between 20% and 80% of the maximum effec. tive normalized channel conductance) to (10) with Fig. 2 shows the variation of extracted mobility and threshold voltage versus channel length for both devices. As expected, for a-Si:H TFT’s the extracted mobility decreases at shorter channel lengths [5]. This is due to a large drain-source voltage drop at source/drain series resistance in comparison to the channel resistance for a shorter channel-length a-Si:H TFT (the channel resistance is smaller); this results in a lower extracted mobility. Also, at larger the channel resistance becomes smaller, and consequently a larger portion of the applied drain-source voltage drops in source/drain series resischaracteristics to curve downward, tances, inducing the – which will result in a lower extracted threshold voltage. m, For a longer channel-length a-Si:H TFT, e.g., the channel resistance is much larger than source/drain series

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Fig. 2. Evolution of extracted FE and VT as a function of channel length for a-Si:H TFT and gated-four-probe (GFP) a-Si:H TFT structures.

resistances, and the extracted mobility approaches its intrinsic mobility value ( cm /Vs). However, by using gated-four-probe a-Si:H TFT, the measured mobility is independent of channel length, and is very close to the intrinsic mobility value (Fig. 2). Besides the field-effect mobility and threshold voltage, the field-effect conduction activation energy ( ) of the a-Si:H TFT has also been used to describe the quality of a-Si:H and the a-Si:H/a-SiN:H interface of a-Si:H TFT [6]. To compare the evolution of the activation energy as a function of gate bias, the – and – characteristics were measured at temperatures ranging from 27 to 100 C. The value at each gate voltage was obtained from the slope of the straight lines on Arrhenius plot ( versus for a-Si:H TFT and versus for gated-four-probe a-Si:H TFT structure). Fig. 3 shows the variation of the extracted activation energy as a function of for 20- m and 482- m channel-length a-Si:H TFT, and of for 30- m channel-length gatedfour-probe a-Si:H TFT. For 20- m channel-length a-Si:H TFT, the value of activation energy is slightly higher than the other two values, especially at higher . This is due to the temperature-dependent source/drain series resistances: the higher the temperature, the lower the source/drain series resistances. Because of this, the extracted activation energy is overestimated [6]. For shorter-channel-length a-Si:H TFT’s operating at higher gate bias, the measured activation energy is larger because the channel resistances is lower and the source/drain series resistances play a more important role in the performance of a-Si:H TFT. This overestimation does not allow the full optimization of a-Si:H TFT. In addition, this overestimation of indicates a wrong value for the slope

IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 7, JULY 1997

Fig. 3. Variation of Eact versus a-Si:H TFT structures.

VG

for a-Si:H TFT and gated-four-probe

of the conduction-band-tail states, which control the electrical performance of a-Si:H TFT. For gated-four-probe or longchannel-length a-Si:H TFT’s, the contribution of source/drain series resistances is negligible, and the measured activation energy is very close to its intrinsic value. Therefore, in the optimization process of a-Si:H TFT either long-channel-length a-Si:H TFT or gated-four-probe a-Si:H TFT structures must be used. In conclusion, we have demonstrated that the gated-fourprobe a-Si:H TFT structure can be used to measure the intrinsic performance of channel materials even for a-Si:H TFT’s having poor source/drain contact resistances. The implication of this very unique and powerful a-Si:H TFT structure is that it can be used in the optimization of a-Si:H channel material in a short-channel (small area) device configuration (relevant for AMLCD’s) which is the most influenced by parasitic source/drain series resistances. REFERENCES [1] M. J. Powell and J. W. Orton, “Characteristics of amorphous silicon staggered-electrode thin-film transistors,” Appl. Phys. Lett., vol. 45, pp. 171–173, 1984. [2] M. Shur, Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990, pp. 361–363. [3] C.-Y. Chen and J. Kanicki, “High field-effect-mobility a-Si:H TFT based on high deposition-rate PECVD materials,” IEEE Electron Device. Lett., vol. 17, pp. 437–439, Sept. 1996. [4] T. Li, C.-Y. Chen, C.-T. Malone, and J. Kanicki, “High-rate deposited amorphous silicon nitride for the hydrogenated amorphous silicon thinfilm transistors,” in Proc. Mater. Res. Soc. Symp., 1997, vol. 424, pp. 43–51. [5] J. Kanicki, F. R. Libsch, J. Griffith, and R. Polastre, “Performance of thin hydrogenated amorphous silicon thin-film transistors,” J. Appl. Phys., vol. 69, pp. 2339–2345, 1991. [6] C.-Y. Chen and J. Kanicki, “The influence of density of states and series resistance on the field-effect activation energy in a-Si:H TFT,” in Proc. Mater. Res. Soc. Symp., 1997, vol. 424, pp. 77–83.