Germanium doping challenges - IEEE Xplore

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Ext. Abs. the 13th International Workshop on Junction Technology 2013

Germanium doping challenges Ray Duffy, Maryam Shayesteh, Igor Kazadojev, Ran Yu Tyndall National Institute, University College Cork, Lee Maltings, Dyke Parade, Cork, Ireland. Phone: +353 21 4205666. E-mail: [email protected] is not fully mature yet. Ge device research has concentrated on three different architectures ; conventional MOSFETs, quantum-well field-effect transistors (QWFETs), and FinFETs. For a Ge-based technology to be compatible with the existing CMOS manufacturing process, the integration of Ge on a Si substrate is essential. As the lattice constant of Ge is ~4% greater than that of Si, Ge growth on Si will start to relax almost immediately via the formation of misfit dislocations. To counteract this, a thick SixGe1−x buffer layer is grown on the Si substrate and the active Ge layer is grown on top of that, where the defect density is significantly reduced. This buffered-growth technique provides a way of integrating Ge devices on a Si handle wafer. The Ge surface should be relaxed (or strained, depending on the buffer layer and integration strategy) and can be used to fabricate a conventional MOSFET. In the QWFET case, a thin Ge layer, which functions as the device channel, is grown biaxially strained to the SixGe1−x buffer layer. Two of the most scaled pMOS devices were recently benchmarked at a supply voltage of 0.5 V. These data show that the Ge QWFET [2] has roughly twice the saturation drive current of the Ge MOSFET [3]. In terms of scaled planar devices recent work has shown 70 nm gate length pMOS Ge devices on bulk substrates [4] while pMOS Ge devices were demonstrated down to 30 nm gate lengths using Ge-on-insulator (GeOI) wafers facilitated by thinning the Ge layer to 25 nm [5]. In 2007 Ge p-channel FinFETs were fabricated, although dimensions were very large as fin widths were 130-350 nm [6]. Very recently scaled (fin widths= 40 nm) Ge p-channel FinFET devices were fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [7]. Last year IMEC published calculations of stress enhanced mobilities in n- and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond [8]. Relaxed Ge p-FinFETs cannot outperform strained Si. However, growing the Ge channel strained on a SiGe 75 % SRB provides a 49 % mobility boost over strained Si. For Ge n-FinFETs, relaxed channels outperform strained Si by 120 %, primarily due to the 6× increase in fin sidewall mobility. Adding a SiGe 75% S/D stressor increases that benefit to 210 %.

1. Abstract Ideal source and drain regions rely on high dopant solubility in the crystalline substrate, in order to boost activation and reduce sheet resistance, and low dopant diffusivity, to facilitate device scaling. High-concentration doping of Ge can be quite a substantial problem, as it is difficult to activate impurity atoms to a high enough level, prevent them escaping during thermal treatments, while maintaining good crystalline integrity of the semiconductor substrate. With future FET devices fabricated with nanowire, fin, or ultra-thin-body architectures, as reiterated by The International Technology Roadmap for Semiconductors, this problem may be challenging for many years to come. In this paper Ge doping challenges will be reviewed, including our ability to model such materials, as well as looking at potential future solutions. 2. Introduction : Ge devices Ge and III-V compounds have emerged as candidates for future advanced digital logic applications due to material properties that could meet needs for improved density, energy efficiency, and reliability. Potentially Ge and III-Vs could produce increased electron and hole mobility over Si and would result in reduced power and higher drive currents if successfully integrated in a CMOS process without degrading the mobilities. The integration of either emerging material for CMOS applications will be challenging. These difficulties include defect control, interface chemistry control, dopant incorporation and activation, and source/drain formation with low resistance contacts. Fundamental to the integration of Ge and III-V materials, is the ability to grow or bond defect-free material onto Si handle wafers. Apart from the advantage from the mechanical strength of Si, this co-integration is also driven by the expectation that other Si components will be included in the same integrated circuits (ICs). Integrating these different materials with different process requirements is definitely not easy. In the recent past Ge has been pushed for pMOS devices while III-V has been strongly considered for nMOS, due to fundamental material issues. However from a manufacturing point-of-view process complexity and costs would be greatly reduced if the same material could be used for both nMOS and pMOS channels. The following briefly describes the Ge MOS device state-of-the-art to inform the reader of the context of this work [1]. Most of the devices fabricated to date have relatively long channels, emphasising that this technology

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3. Doping challenges 3.1 Literature review Figure 1 summarises the main characteristics of dopants in Ge. P and As are relatively difficult to activate and

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diffuse quickly [9,10]. Sb is a heavy ion, and if ion implanted it can cause severe substrate deformation. Conversely, the low diffusivity and high electrical activation of B and Ga in Ge makes them ideal p-type candidates for scaled junction formation [11]. P, As and Sb in Ge exhibit concentration-enhanced diffusion or a (n/ni)2 dependency. The resulting doping profile after a rapid thermal anneal is typically box-like in nature. P and As diffusion in Ge are reported to be vacancy-mediated [12-14]. The maximum activation of n-type dopants has been reported in the 5×1019-1×1020 cm-3 range [15-17]. Very recently Bruno et al. reported an impressive ~1021 cm-3 level of active Sb doping, using melt-laser annealing [18]. In terms of clustering behaviour, fundamental modelling and theory predicts that donors deactivate via vacancies [19,20]. In contrast, the behaviour of p-type dopants in Ge is relatively straight-forward. B and Ga implants activate to very high levels while essentially being diffusion-free. B implanted into preamorphised Ge produced a maximum activation = 5×1020 cm-3 after 360 °C solid-phase-epitaxy [21]. Ga maximum activation = 6.6×1020 cm-3 was reported after 450 °C 1 hr anneal [22]. B sheet resistance evolution versus anneal time and temperature was reported [23], and changes in sheet resistance were correlated with end-of-range defect dissolution and subsequent release of Ge interstitials. Ab-initio modelling of B in Ge predicts diffusion via self-interstitials [24]. Equilibrium solubility may not be sufficient to meet the aggressive access resistance targets at advanced device dimensions, thus above-equilibrium metastable solubility may be a requirement. Techniques to generate such metastable solubilities are well known in Si, and have been initially explored in Ge [25]. Typically the crystalline substrate is amorphised by ion implantation, and recrystallised by thermal annealing thereafter. The formation of metastable solubility requires care during subsequent processing because further supply of thermal energy, causes the metastable condition to revert back to the lower equilibrium state. Deactivation kinetics of dopants in Ge are at an early stage of exploration at this point in time. Control of diffusion can be achieved by reducing the thermal budget of the annealing process, for example by using high-temperature millisecond anneals (laser and flash). They are now being regularly applied to Ge [26-31]. As the melting point of Ge is 937 °C, a low-temperature process such as solid-phase-epitaxial- regrowth appears to be another solution [32]. An alternative approach to control diffusion, sometimes called point-defect-engineering, is by co-implantation of a non-dopant species such as C, N or F. These species can sink point defects that cause diffusion. N implants have been demonstrated experimentally to reduce P diffusion in Ge [33,34]. C also reduces P diffusion [35,36]. Recently it was shown experimentally that a F co-implant can affect the diffusion of As in certain annealing conditions [37]. With respect to the Rs vs Xj performance specification, a detailed review of public-domain data was presented last year [38], and in summary the best performing data for

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n-type resulted from plasma doping, and for p-type from ion implantation. In conclusion, there is a foundation of experimental data and physical knowledge on dopant diffusion and activation for relaxed Ge. The situation is considerably more cloudy for strained Ge and SiGe (with high Ge content) where almost no experimental data exist on dopant diffusion, activation and contact formation, and on in-situ doping and selective epitaxial growth on surfaces with different crystal orientations. n-type dopants (P, As, Sb)

p-type dopants (B, Ga)

Max. ~1020 cm-3 Activation

(Non-melt)

Max. ~1021 cm-3

Max. ~6×1020 cm-3

(Melt)

Diffusion

Fast

Slow

• Bad for scaling • Good for in -diffusion

• Good for scaling • Bad for in -diffusion

Resulting profile shape

Box-like

Gaussian

Diffusion mechanism

V-mediated

I-mediated

Clustering mechanism

V-mediated

I-mediated

Plasma doping

Ion implant

Best Rs vs Xj

Fig. 1 : Summary of n-type and p-type dopant characteristics in Ge.

3.2 Case study ; Ge desorption and dopant loss A serious concern during thermal annealing of Ge substrates is desorption of Ge from the surface, which can lead to surface roughening and dopant loss. To address the substrate desorption issue Ionnaou et al. experimentally investigated substrate loss of uncapped Ge and found it characterized by an Arrhenius equation with EA= 2.03 eV [39]. Capping the substrate is a solution as a SiO2 or a Si3N4 cap improved P dose retention. Kaiser et al. further experimentally studied this desorption effect as a function of anneal ambient. They concluded that low thermal budgets, small furnace volumes, and vacuum conditions lower substrate loss [40]. We investigated the impact of dopant impurities on the Ge desorption effect. The process flow is summarised in Fig. 2. After standard clean, n-type (100) Ge wafers with a bulk resistivity of 0.2-0.5 ohm.cm received an implant of P with the doses of either 1×1015 cm-2 or 1×1014 cm-2. In order to compare the effect of implant damage on desorption phenomenon one sample did not receive any implant. 100 nm of SiO2 was deposited by plasma enhanced chemical vapour deposition (PECVD). A lithography step was performed to pattern the oxide (see

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Fig. 3(d)) in order to cover some part of the Ge while leaving other parts exposed. Photo resist was then removed. The samples then underwent a RTA step at 600 or 700 °C for 1 min either in N2 or N2 and 10 % O2. From each set of wafers one sample was kept as control case without being subjected to RTA treatment. Finally the SiO2 mask was removed in buffered oxide etch (BOE) for 2-2.5 minutes. Samples were inspected by scanning electron microscopy (SEM) using QUANTA FEG 650. Surface roughness and step height measurements were carried out by Atomic Force Microscopy (AFM) in tapping/non contact mode at room temperature on 5×5 μm scanning area. Cross-sectional transmission electron microscopy (XTEM) was also performed using a JEOL2100.

(a)

(b)

(c)

(d)

Fig. 3 : Ge samples after (a) P implant with the dose of 1×1015 cm-2, (b) P implant with the dose of 1×1014 cm-2 and (c) no implant, all followed by a 600 °C anneal in an 90 % N2 + 10 % O2 ambient. Facets are formed on the samples with height of 300 nm. (d) Layout of the test structure. Fig. 2 : Process flow for Ge desorption study.

4. Modelling capabilities Physically-based modelling offers the following major advantages : it is relatively predictive, it provides insight to physics and chemistry that would be otherwise inaccessible, it gives a portal to theoretical knowledge in a way that is more accessible to non-experts, and it is much quicker and cheaper than performing experiments It should be noted that a key difficult challenge present across all the modelling areas is that of experimental validation. This challenge is especially difficult because for most processes many physical effects interact with each other and must be appropriately separated by well-defined experiments, in order to be able to develop predictive models and not simply fit experimental data. For doping diffusion and activation, continuum models still remain the mainstay of process simulators even if Kinetic Monte Carlo (KMC) techniques are very promising. Continuum models need continued refinement to be able to adequately capture technologies with reduced thermal budgets and a wider range of impurity species. Point-defect based diffusion models need to be continuously refined especially concerning the kinetics of dopants and defects in clustering, activation, and deactivation during post-activation processes at elevated temperatures, in addition to capturing transient effects. In terms of benchmarking future device options, and especially those of high-mobility channels, modelling

Fig. 3 shows sample implanted with (a) P with the dose of 1×1015 cm-2 , (b) P with the dose of 1×1014 cm-2 and (c) no implant followed by a 600 °C anneal in N2 and 10 % O2 ambient. For the sake of simplicity we will refer to the implant doses as low dose and high dose implants. The set of samples annealed in N2 and O2 ambient were highly oxidised, and a large height difference (more than 300 nm) was observed between covered and uncovered areas. Besides, the measured surface roughness was significantly higher. Figs. 3(a), (b), and (c) show representative SEM images, which show serious surface degradation. As in seen in the figure, in all cases regular facets are formed on the samples regardless of the implants applied to each sample. These facets are at least 300 nm tall. First it was believed they are Ge-oxide, but cross sectional XTEM confirmed that these structures are in fact patterned Ge. We found little evidence in our studies that the P implant (or lack of) changed the amount of Ge desorbing from the surface in either inert N2 or oxidising annealing conditions.

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capabilities are essential at this key moment in time, since many of these structures have not yet been fabricated at the required device dimensions. Thus, as the experimental research on all the options is at a very early stage, a properly formulated set of physics-based models would give a substantial advantage for time- and cost-effective development of Ge CMOS devices. Synopsys Sentaurus Process supports diffusion and activation in crystalline Ge with a Ge/GeO2 interface both in continuum and KMC mode. Even though a basic calibration based on literature data has been performed for Ge, it lacks the maturity of Si. Only Monte Carlo techniques are currently used for ion implantation into Ge, and at this stage are considered to be sufficiently accurate. A fundamental set of Ge models and parameters are based on literature for Ge material properties, damage accumulation, point-defects and extended defects, dopant (As, B, P) diffusion, activation, dose loss. Two case studies are presented in Figs. 4 and 5. Initially the traditional ion implantation simulation was performed. A P implant of 1015 cm-2 at 30 keV was followed by anneals at temperatures ranging from 500 – 700 °C for 1000 s. The typical characteristics of P diffusion in Ge have been reproduced, namely rapid diffusion at these temperatures, a flat-top and steep tail profile shape consistent with concentration-enhanced diffusion, and a dip towards the surface consistent with some dopant loss to outgassing or desorption.

Concentration (atoms/cm3)

1E+21 1021

In this case, there is a dynamic between in- and out-diffusion, as can be seen from the evolution of the retained dose. At higher temperatures in the simulation there is less total incorporated P dose. 1.E+20 1020

Concentration (atoms/cm3)

Phos in-diffusion from surface layer

0.2

0.3

0.4

20

30 40 Depth (nm)

50

60

With the trend towards non-planar FETs using nanowire or fin-based architectures, there has been an emphasis in the community to achieve conformal doping. Unlike ion implantation where ions are extremely mono-directional, conformal doping aims to coat the surface of the target structure uniformly with a dopant-enriched layer, from which the dopant can be evenly redistributed during a thermal anneal. Should one place a high concentration of dopant equally successfully on all surfaces, then a uniform or conformal dopant profile is a realistic outcome. Gas-phase and solid-source doping technologies have been around for many years, but there have been recent developments in plasma doping [41,42] and molecular monolayer doping [43,44] methods which would be compatible with highly scaled wires and fins with aggressively scaled pitches. One drawback of this methodology is the reliance on diffusion. In-diffusion from a high-concentration surface layer does not involve epitaxy (solid-phase or other form) which means solubility is essentially limited to the equilibrium value for that thermal anneal. The boost in solubility will not be available. Hence clever scientists and engineers will need to be creative in order to overcome this fundamental issue. Two processing techniques used in Si have yet to be fully explored in Ge; namely vacancy engineering and low-temperature implants. Vacancy engineering involves the generation of vacancy

0.5

Depth (μm) (um) Distance from interface

Fig. 4 : Simulated P diffusion in Ge using Sentaurus Process. The black curve shows a P implant : 1015 cm-2 at 30 keV. The anneals were 1000 s at temperatures ranging from 500 – 700 °C.

Following that we simulated P in-diffusing from a surface. This may be useful for non-planar device structures such as nanowires or fin-based architectures. Oxide was grown on the surface containing a high concentration of P, and during the subsequent anneals the P diffused inwards.

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5. Emerging doping methods

550 °C 600 °C 650 °C 700 °C

0.1

650 °C : 3.7e12 cm-2

Fig. 5 : Simulated P diffusion in Ge using Sentaurus Process. In this case the P is introduced from a surface layer. The anneals were 1000 s at temperatures ranging from 500 – 700 °C.

500 °C

0

550 °C : 6.3e12 cm-2 600 °C ; 4.9e12 cm-2

1.E+18 1018

0

1E+19 1019

1E+17 1017

Retained dose : 500 °C : 7.9e12 cm-2

1.E+17 1017

Anneal time = 1000 s

1018 1E+18

1.E+19 1019

700 °C : 2.8e12 cm-2

Phos diffusion after ion implant

1E+20 1020

Anneal time = 1000 s

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point defects by means of a tailored high energy ion implant. Strengths and limitations of the vacancy engineering approach for the control of dopant diffusion and activation in silicon were reviewed recently by Claverie et al. [45]. The enrichment with vacancies close to the silicon surface can be obtained by inert impurity implantation at high energy [46]. Vacancies can also be injected from populations of empty voids undergoing Ostwald ripening during annealing. Colder wafer temperatures enhance the likelihood of amorphisation as dynamic annealing is reduced, and thus damage build-up is promoted. At colder temperatures point defects are less mobile, thus an interstitial defect has less energy to move and meet a vacancy point defect with which it can recombine. As a result co-implants performed at cryogenic temperatures are an alternative to traditional preamorphising implants. The result is a deeper amorphous layer, essentially removing free-interstitials that would go on to form the EOR defect band upon thermal treatment. Murakoshi et al. used liquid nitrogen in order to control defects and impurity out diffusion [47], where 8 inch (100) silicon wafers were cooled to below -160 °C. Khaja et al. recently reported that implants at cryogenic temperatures increase dopant activation with reduced diffusion, resulting in lower sheet resistance for a lower junction depth [48].

Acknowledgements This work has been funded by the Science Foundation Ireland under Research Grant No. 09/SIRG/I1623. Ray Duffy would like to thank Nik Zographos and Christoph Zechner of Synopsys for critical discussions on Ge process modelling. References [1] R. Pillarisetty, Nature 479, 324 (2011). [2] R. Pillarisetty, et al., Tech. Digest IEEE Electron Devices Meet. 150–153 (2010). [3] J. Mitard, et al., Tech. Digest IEEE Electron Devices Meet. 873–876 (2008). [4] G. Hellings, et al., IEEE El. Dev. Lett. 30, 88 (2009). [5] L. Hutin, et al., IEEE El. Dev. Lett. 31, 234 (2010). [6] J. Feng, et al., IEEE El. Dev. Lett. 28, 637 (2007). [7] M. J. H. van Dal, et al., Tech. Digest IEEE Electron Devices Meet. 521–524 (2012). [8] G. Eneman, et al., Tech. Digest IEEE Electron Devices Meet. 131–134 (2012). [9] C. O. Chui, et al., Appl. Phys. Lett. 83, 3275 (2003). [10] C. O. Chui, et al., Appl. Phys. Lett. 87, 091909 (2005). [11] A. Satta, et al., Appl. Phys. Lett. 87, 172109 (2005). [12] M. Naganawa, et al., Appl. Phys. Lett. 93, 191905 (2008). [13] S. Koffel, et al., Mat. Sci. Eng. B 154-155, 60 (2008). [14] S. Brotzmann and H. Bracht, J. Appl. Phys. 103, 033508 (2008). [15] G. Hellings, et al., Elec. Sol. St. Lett. 14, H39 (2011). [16] J. Kim, et al., Elec. Sol. State Lett. 13, H12 (2010). [17] Y. –L. Chao and J. C. S. Woo, IEEE Trans. El. Dev. 57, 665 (2010). [18] E. Bruno, et al., Appl. Phys. Lett. 101, 172110 (2012). [19] A. R. Peaker, et al., Thin Solid Films 517, 152 (2008). [20] A. Chroneos, et al., J. Appl. Phys. 104, 113724 (2008). [21] S. Mirabella, et al., Appl. Phys. Lett. 92, 251909 (2008). [22] G. Impellizzeri, et al., J. Appl. Phys. 106, 013518 (2009). [23] F. Panciera, et al., Appl. Phys. Lett. 97, 012105 (2010). [24] A. Janke, et al., Phys. Rev. B. 77, 075208 (2008). [25] Y.-L. Chao, et al., Appl. Phys. Lett. 87, 142102 (2005). [26] C. Wündisch, et al., Appl. Phys. Lett. 95, 252107 (2009). [27] A. Satta, et al., Nuc. Instr. Meth. Phys. Res. 257, 157 (2007). [28] E. Bruno, et al., J. Appl. Phys. 108, 124902 (2010). [29] Q. Zhang, et al., IEEE El. Dev. Lett. 27, 728 (2006). [30] G. Impellizzeri, et al., J. Appl. Phys. 113, 113505 (2013) [31] S. Heo, et al., Electrochemical and Solid-State Letters, 9(4) G136-G137 (2006). [32] R. Duffy, et al., Appl. Phys. Lett. 96, 231909 (2010). [33] E. Simoen, et al., Mat. Sci. Semi. Proc. 9, 634 (2006). [34] A. Satta, et al., Proceedings of INSIGHT (2007). [35] V. Mazzocchi, et al., RTP International Conference 2009, Albany (2009). [36] S. Brotzmann, et al., Phys. Rev. B 77, 235207 (2008). [37] G. Impellizzeri, et al., J. Appl. Phys. 109, 113527 (2011). [38] R. Duffy, et al., ECS Transactions, 45 (4) 189-201 (2012). [39] N. Ioannou, et al., Appl. Phys. Lett. 93, 101910 (2008). [40] R. J. Kaiser, et al., Micro. Eng. 88, 499 (2011).

6. Conclusions The International Technology Roadmap for Semiconductors has been very thorough in mapping out the potential logic and memory devices of the future, in particular in the Emerging Research Devices and Emerging Research Materials chapters [49,50]. New information processing technologies may deviate from the traditional silicon scaled complimentary field-effect-transistor (FET) path with its electronic charge state variable and digital data representation. With respect to future logic devices a dazzling array of options have been benchmarked, and range from Nanowire FETs, Carbon-nanoribbon FETs, Tunnel FETs, Atomic switches, to Spin FETs and Mott transistors. The cornerstone of the semiconductor industry since the 1960s has been the incremental scaling of device dimensions to achieve integrated-circuit performance gains. However, the continuing increase of current density per area has caused the dynamic power density to climb with scaling to an unacceptable level. Alternate high-mobility channel materials, such as Ge or III-Vs, can provide some relief in this area. A major challenge facing high volume production of high-mobility-substrate devices includes the need for low-resistivity defect-free high-concentration doped regions, junctions, and low-resistivity contacts. The effect of dopant activation and diffusion in these emerging materials is a fascinating subject, and an area in which we should expect to see creative work in the years to come.

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[41] S. Felch, et al., Extended Abstracts of the 11th International Workshop on Junction Technology, IWJT 2011 , art. no. 5969992, pp. 22-25. [42] D. Lenoble, et al., Digest of Technical Papers - Symposium on VLSI Technology 2006, art. no. 1705270 , pp. 168-169. [43] J. C. Ho, et al., Nature Materials 7, 62 (2008). [44] J. C. Ho, et al, Nanoletters 9, 725 (2009). [45] A. Claverie, et al., Mat. Res. Soc. Symp. Proc. 1070, pp. 3-14 (2008). [46] V. C. Venezia, et al., Appl. Phys. Lett. 74, 1299 (1999). [47] A. Murakoshi, et al., Mat. Res. Soc. Symp. Proc. 610, pp. B3.8.1-B3.8.6 (2000). [48] F. A. Khaja, B. Colombeau, T. Thanigaivelan, D. Ramappa, and T. Henry, Appl. Phys. Lett. 100, 112102 (2012). [49] International Technology Roadmap For Semiconductors, 2011 Edition, Emerging Research Devices. [50] International Technology Roadmap For Semiconductors, 2011 Edition, Emerging Research Materials.

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