Graphene Field-Effect Transistors with Aluminium

Graphene Field-Effect Transistors with Aluminium Bottom-gate Electrodes and its Natural Oxide as Dielectrics W. Wei, X. Zhou, G. Deokar, H. Kim, M. Belhaj, E. Galopin, E. Pallecchi, D. Vignaud and H. Happy Published on IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015 

saturation velocity [7][8]. Indeed, graphene field effect transistor (GFET) with a large intrinsic cut-off frequency (ft-int) > 300 GHz have been reported [9]. The study of gate length (LG) scaling has revealed that ft in GFET generally increases with decreasing LG [10], similarly to conventional semiconductor based FET transistors. Another critical parameter of GFET is the maximum oscillation frequency (fmax), which is mainly limited by weak drain current saturation and thus large output conductance. The current record oscillating frequency fmax = 38 GHz has been recently reported for gate length 70 nm with self-aligned T-shaped gate geometry (fmax = 70 GHz after de-embedding) [11]. Thanks to its inherent mechanical robustness and flexible nature, monolayer graphene can be transferred from host substrates to various target substrates, including flexible and transparent objects, which further broaden its applications for large scale functional devices. Graphene flexible transistors have been recently achieved [12] [13] [14]. Here, we describe an approach to fabricate bottom gated GFET on rigid substrate by using transfer techniques and natural oxidation process of aluminum. Our process avoids high temperature deposition process of dielectrics in atomic layer deposition (ALD), which greatly reduces the risk of damaging flexible substrates and provides an alternative fabrication method for future flexible electronics. From measurements of scattering parameters (S-parameters), both the total gate capacitance and stray capacitance due to the graphene partially suspended in lateral sides of bottom-gate have been evaluated. The maximum oscillations frequencies of our FETs are competitive with results in literature, demonstrating the potential of our fabrication scheme, especially for flexible electronics. [12] [13] [14].

Abstract—In this work, we present fabrication process of graphene field effect transistors by using natural oxidation of aluminum as dielectrics, which provide an alternative fabrication choice for future flexible electronics with large scale and arbitrary substrates. The high quality monolayer graphene is preserved by our process and the mobility up to 3250 cm2/Vs is measured after whole device fabrication. Graphene field effect transistors with double bottom-gate structure varying from 300 nm to 100 nm in gate length have been characterized by both static and dynamic measurements. The total gate capacitances of our device structure are evaluated based on the measurement results of scattering parameters. We report an intrinsic current gain cut-off frequency (ft-int) of 11 GHz and maximum oscillation frequency (fmax) of 8 GHz in devices with 100 nm gate length. Moreover, both values of ft-int and fmax for different gate lengths are also discussed. Our results indicate that the full process exhibits great potential, especially for graphene based flexible electronics. Index Terms—graphene, natural characterization, transfer, transistor

oxide,

radio-frequency

I. INTRODUCTION

G

raphene, a two dimensional lattice of carbon atoms arranged in a honeycomb lattice, has attracted enormous attentions for the development of novel optoelectronic devices [1][2][3]. The interest for this material stems from the unique electronic and mechanical properties of graphene which derive from its truly two-dimensional nature, the high Fermi velocity and massless Dirac fermions character of the charge carriers [4]. Moreover, large area graphene with high quality can be obtained either by graphitization of silicon carbide or by chemical vapor deposition (CVD) on metals, which make mass production of graphene based electronics possible [5][6]. One of the most promising applications of graphene in electronics is to be used as a channel material for radio frequency field effect transistors (RF-FET), a critical element in wireless communications. This is because graphene has extraordinarily high mobility (200000 cm2 V-1 s-1) and large

II. EXPERIMENT A. Graphene growth and transfer technique In this work, graphene grown by CVD on copper foil was used. A wet chemical transfer process was developed to transfer graphene monolayer from host substrates to various target substrates. Fig.1 (a~e) show the whole transfer process: (a) a polymethyl methacrylate (PMMA) layer of 200 nm thickness, the transfer medium, was spin-coated on top of the graphene/Cu foil. Here, Cu foil is the host substrate. Before

This work was supported by EU FP7-ICT-2013-FET-F GRAPHENE Flagship project (no. 604391) H. HAPPY is with Institute of Electronics, Microelectronics and Nanotechnology, CNRS UMR8520, Villeneuve d’Ascq, cedex, France (e-mail: [email protected])

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Fig. 2 Raman spectra of graphene (a) after transfer onto Si/SiO 2 substrate and (b) after device fabrication process.

etching the Cu foil, graphene on back side of the Cu foil was removed by reactive ion etching (RIE) in a O2 plasma. (b) Then, Cu foil was etched by use of copper etchant for several hours. (c) After etching, the graphene/PMMA layer was placed on target substrates. (d) The sample was treated by an exposure process of UV light. (e) Then the PMMA layer was effectively removed by flooding into methyl isobutyl ketone (MIBK) solution and finally the sample would be rinsed by immersing into Acetone. Fig.1(f) shows a final optical image of transferred graphene with area of 1.5 cm × 1.5 cm on SiO 2/Si substrate. The quality of the monolayer graphene was verified by Raman spectroscopy, both after transfer on SiO2/Si substrate and at the end of the GFET fabrication process.

B. Device fabrication The schematic of a GFET device fabricated in this work is shown in Fig.3 (a). The device fabrication was started by patterning bottom-gate on a SiO2 (300 nm thick)/Si (resistivity > 8000 Ω·cm) substrate by e-beam lithography, followed with the 40 nm Al deposition and lift-off process. The bottom-gate structure was finished with natural oxidation process of Al obtained by exposing the substrates with bottom-gate structure to the air for 24 hours [15]. The thickness of Al2O3, formed by this natural oxidation process, was confirmed to be 4.3 nm by spectroscopic ellipsometer [16]. This natural oxidation process avoids high temperature deposition of dielectric layer, which is compatible with the GFET fabrication process on various flexible substrates. This natural oxidation technique has been already used in fabrication of GFET with top-gate structure [17][18][19]. In our work, bottom-gate structure was used in order to further reduce the possibilities of degrading graphene mobility due to electron irradiation which could happen in directly e-beam writing on the top of graphene channel [20]. The 1.5×1.5 cm2 monolayer graphene was transferred on top of the pre-patterned bottom-gate by using the wet chemical transfer technique mentioned above. RIE O2 plasma was used to etch graphene to obtain isolated patterns. Source and drain contacts were defined by depositing Ni/Au (20nm/30nm thickness) followed by a lift-off process. Figure 3(a) shows a cross section schematic of a GFET device with double bottom-gate structure. There is small air gap existing between lateral sides of bottom-gate and graphene layer, which is induced in the graphene transfer process, as shown in the Fig.3 (b) in both schematic and scanning electron microscope (SEM) image. The value of the stray capacitance Cx which is due to this air gap will be evaluated in ‘Discussion’ part. In order to make these devices compatible with on-chip probe measurements, the device fabrication were finished by depositing Ni/Au (50nm/300nm in thickness) for gate, source and drain pads (coplanar wave guide access). A typical GFET device completed is shown in Fig.3 (c) and in the inset of Fig.4 (a). Figure 3 (c) shows the SEM image of a completed device structure with coplanar wave guide access and zoom of part of the gate which was covered with a monolayer graphene. Three sets of samples with the same gate width (W = 12 μm) and drain source length (Lds = 1μm) but different gate lengths (LG = 100 nm, 200 nm and 300 nm) have been fabricated and measured. Here using Lds of 1µm makes our process tolerant to the misalignment induced by electron beam lithography, which is a problem in the fabrication process on flexible substrates. Together with devices, Van der Pauw and transmission line method structures dedicated to DC characterization were also fabricated on chip.

Fig. 1 (a-e) Schematic of the graphene wet transfer process. (f) the optical image of graphene on SiO2/Si substrate after transfer process.

Figure 2(a) shows that the Raman intensity ratio between 2D band and G band after transfer is 3.2, indicating the high quality of the graphene material and transfer technique. Moreover, after the GFET fabrication process, the intensity ratio between 2D band and G band is around 2.6 as shown in Fig.2(b), which indicates that our fabrication process does not degrade significantly the graphene quality.

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measurements [22][23]. Thus, in this paper, GFETs have been fabricated based on p-type monolayer graphene. From the curve of gm - Vgs, the maximum static transconductance of gm = dIds/dVgs = -116 µS/µm was extracted. (a)

(b) Vds=1V

300 Vgs=-0,75V

200 Step by 0.25 V

100

200

100 Ids

350 0 gm

-100

300 0 0.0

0.5

gm (µS/µm)

400

Ids (µA/µm)

Ids (µA/µm)

400

-0.5

1.0

0.0

0.5

Vds (V) Vgs (V) Fig. 4 DC transport characteristics of the device with gate length of 100 nm. (a) Ids - Vds characteristics correspond to different Vgs which varies from -0.75V to 0.25 V stepped by 0.25 V. The inset image shows a final device with probes on its coplanar wave guide access and (b) Both Ids and gm curves as function of Vgs at Vds = 1V.

Fig. 3 (a) Schematic of the cross section of GFET device. (b) Top: Schematic of the cross section of gate structure with air gap existing between graphene and the bottom-gate. Bottom: SEM image of a single bottom-gate covered with graphene layer. (c) SEM image of the graphene transistor with double gate structure

The electrical properties of our graphene after the device fabrication were investigated by Hall measurements and transmission line method. Indeed our graphene exhibits excellent transport properties, with hole mobility of 3250 cm2/Vs and carriers density of 1.2×1012 cm-2. The average sheet resistivity measured on 10 test structures was 1600±200 Ω/square with an average contact resistance around 2200 Ω ∙µm.

The high frequency performance of our GFET was characterized by using a PNA Network Analyzer (Agilent, E8361A) under ambient conditions in the frequency range of 0.1-67 GHz. A common calibration procedure of Line-Reflect-Reflect-Match (LRRM) was performed before measurements. The de-embedding procedure is implemented to extract the extrinsic and intrinsic performances from measured result of DUT (device under test), as described in [24][25]. The “pad” and “open” structure were fabricated on the same chip. The “pad” structure has only the coplanar access of GFET. The “open” structure has the same geometrical structure as the active part of device but without graphene between source and drain. Based on this measurement method, the DUT, extrinsic and intrinsic current gain |H21| of the GFET devices were obtained from the S-parameters obtained before and after de-embedding operations.

III. DISCUSSION All GFET devices were firstly characterized by DC measurement at room temperature with an Agilent DC parametric Analyzer (E5260B). We fully characterized around 60 transistors obtained on two batches. Here, we show detailed measurement results of a typical device with 100 nm gate length. Figure 4 shows DC characterization: the drain-source current (Ids) as function of drain voltage (Vds) was measured by varying gate voltage (Vgs) from -0.75 V to 0.25 V, by step of 0.25 V, shown in Fig.4 (a). The drain current reaches a maximum value of 406 μA/μm at drain voltage Vds = 1V and Vgs = -0.75V. We did not observe the phenomenon of current saturation, even in the higher Vds region. Indeed saturation is difficult to obtain in graphene due to the effect of contact resistance and the absence of a proper bandgap [21]. Figure 4(b) shows both the transconductance (gm) and Ids characteristics as function of Vgs, measured using a constant bias Vds = 1V. Note that all the values shown here were normalized by the device effective gate width, W = 12 μm. Our device exhibits ambipolar characteristics. The minimum Ids was found around Vgs = 0.6 V, which indicates the Dirac point. The increase of Ids before and after this point indicates the accumulation of holes or electrons as controlled by the gate voltage. In addition, Ids - Vgs measurement results also indicate a p-type behavior, in agreement with Hall effect

(a) 30

(b) 20

10

0 0.1

-20dB/dec

-20dB/dec

U (dB)

H21 (dB)

20

DUT Extrinsic Intrinsic ft = 11 GHz 1

10

0 10

Frequency (GHz)

0.1

fmax= 8 GHz 1

10

Frequency (GHz)

Fig.5 (a) The DUT, extrinsic and intrinsic current gain |H21| of GFET device with 100 nm gate length as function of frequency. Here, intrinsic current gain was deduced after de-embedded operations. (b) Unilateral gain (U) of the same device.

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Figure 5 (a) shows the DUT, extrinsic and intrinsic current gain of the same device (gate length of 100 nm) discussed in the DC measurement section, for which an intrinsic current gain cut-off frequency (ft-int) of 11 GHz was found. Figure 5 (b) shows unilateral gain U measured from the same device, and the maximum oscillation frequency (fmax) of 8 GHz was obtained. The fmax is much less sensitive to the open de-embedding procedure [26]. Therefore, we only explored the value of fmax without de-embedding here. It must be noted that both ft-int and fmax of this device were obtained at Vds = 1V and Vgs = 0.2 V, based on the previous DC measurements. With the same method, performances of devices with different gate length, varied from 100 nm to 300 nm, have been characterized.

preserved the quality of graphene, which is confirmed by the comparison of 2D/G ratio in Raman spectra before and after device fabrication. Based on these techniques, GFET devices with different gate length were fabricated and characterized. The fmax of 8 GHz and ft-int of 11 GHz were obtained in devices with 100 nm gate length. The scaling of ft-int with decreasing gate length was clearly observed. Both total gate capacitance CgT and stray capacitance Cx have been evaluated based on S-parameters. Reliable graphene transfer and device fabrication techniques in this work provide another opportunity for further development of GFET on flexible substrates. REFERENCES [1]

In Table I, both the best and average values of ft-int, fmax and gm are shown. The clear tendency that ft-int increases with decreasing gate length has been observed, in accordance with previous reports [10]. The values of gm decrease slightly with the gate length decreasing, which can be attributed to the competition between decreases of effective gating area and the increase of the non-gating area. Increases of non-gating area will increase access resistance between source and drain contacts. The total gate capacitance CgT includes geometric capacitance Cge, quantum capacitance and a stray capacitance Cx (see Fig. 3 (b)). By S-parameters measurement [27], the values of CgT were obtained to be 16±0.8 fF, 28±1 fF and 42±1.4 fF, corresponding to different gate length Lg=100 nm, 200 nm and 300 nm. The linear scaling allows for the extraction of the stray capacitance Cx ≈ 0.65 fF, which is constant for different values of Lg. The gate capacitance decreases relatively faster than gm, as previously reported [21]. Consequently, we observed that ft-int is inversely proportional to the device gate length. The most critical parameter for applications of G-FET is the extrinsic fmax: in our devices competitive values of 5.3 GHz, 8.0 GHz and 8.0 GHz for different Lg (see Table I). The values of fmax are determined not only by gm but also by the competition among gate resistance Rg, the drain source resistance Rds, and total gate capacitance CgT [21]. Thus, fmax is not simply scaling with the gate length, as shown in our measurement results. For a further improvement of the performances, an optimized design which minimizes access resistance is required.

[2] [3] [4] [5]

[6]

[7] [8]

[9]

[10]

[11]

[12]

[13]

TABLE I SUMMARY OF DEVICE PERFORMANCE WITH DIFFERENT GATE LENGTH. Gate length (nm)

CgT average (fF)

gm average (µS/µm)

gm best (µS/µm)

ft-int average (GHz)

ft-int best (GHz)

fmax average (GHz)

fmax best (GHz)

300

42±1.4

155

208

200

28±1

128

167

4.5

6.5

2.9

5.3

9.3

10.0

6.4

8.0

100

16±0.8

100

150

11.2

13.5

7.2

8.0

[14]

[15]

[16] [17]

IV. CONCLUSION We have developed a fabrication process suitable for flexible devices based on natural oxidation of aluminum as dielectrics with bottom-gate structure. This fabrication process also

[18]

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H. Kim received his PhD degree in materials science and engineering from Illinois Institute of Technology (IIT) in Chicago, in 1992. His current research interests are on the GaAs/InP/GaN devices, MMICs, and their system applications. He was a visiting scholar at IEMN, working on graphene from 2011 to 2012. Mohamed Moez BELHAJ He received his master degree in Micro-nanotechnologies and telecommunication in University of Lille 1, France in 2012. He is currently working toward the Ph.D degree at IEMN and his main research interests are concerned with modeling and characterization of passive and active electronics.

Elisabeth Galopin received the Ph.D. degree in micro and nanotechnology from the Université des Sciences et Technologies de Lille, France, in 2007. She is now focusing on graphene growth for devices at IEMN.

Wei WEI received his master degree in Materials Science and Engineering in Hunan University, China in 2011. He is currently working toward the Ph.D degree at Institute of Electronics, Microelectronics and Nanotechnology (IEMN), Lille 1 University for domain of passive and active flexible electronics.

Emiliano Pallecchi received Ph.D degree in physics from the University of Regensburg, Germany in 2008. He is currently Maitre de Conference (Associate Professor) in the Carbon group at IEMN, Lille 1 University, France.

Dominique Vignaud obtained his Ph.D. in 1983 and the “These d’Etat” in 1989, both from the University of Lille, for works on the optical properties of plastically deformed III–V compounds (InSb and GaAs). He was hired by the CNRS in 1983. His current interest stands in the elaboration and characterization of epitaxial graphene and of graphene on metals.

Xin ZHOU, she received Ph.D from Tokyo Institute of Technology, department of physical electronics.

Henri Happy received the Ph.D. degree in Electrical Engineering from the University of Lille 1, in 1992. He is currently Full Professor of Electronics of University Lille 1. Since 2004, he has focused on carbon nanodevices (carbon nanotube, graphene). The Carbon group is involved in the European Graphene Flagship program.

G. Deokar received her doctorate from the Institute of Nanosciences of Paris, University of Pierre and Marie Curie in 2012. She is working on CVD graphene growth and its transfer on arbitrary substrates for various applications.

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